Reklam
Reklam
STS5NF60L
N-channel 60V - 0.045
Ω
- 5A - SO-8
STripFET™ Power MOSFET
General features
Type
STS5NF60L
V
DSS
60V
R
DS(on)
<0.055
Ω
I
D
5A
■
■
Standard outline for easy automated surface mount assembly
Low threshold drive
Description
This Power MOSFET is the latest development of
STMicroelectronis unique "Single Feature Size™" strip-based process. The resulting transistor shows extremely high packing density for low onresistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility.
Applications
■ Switching application
SO-8
Internal schematic diagram
Order codes
Part number
STS5NF60L
Marking
S5NF60L
Package
SO-8
Packaging
Tape&reel
January 2007 Rev 4 1/12 www.st.com
12
5
1
2
Contents
Contents
STS5NF60L
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2/12
STS5NF60L Electrical ratings
Table 1.
Symbol
Absolute maximum ratings
Parameter
V
DS
V
GS
I
D
I
D
I
DM
(1)
P
TOT
Drain-source voltage (v
Gate- source voltage gs
= 0)
Drain current (continuous) at T
C
Drain current (continuous) at T
C
Drain current (pulsed)
= 25°C
= 100°C
Total dissipation at T
C
= 25°C
Derating factor
Peak diode recovery voltage slope dv/dt
(2)
T stg
T j
Storage Temperature
Max operating junction temperature
1.
Pulse width limited by safe operating area
2.
I
SD
≤
5A, di/dt
≤
100A/µs, V
DD
≤
V
(BR)DSS
, T j
≤
T
JMAX
Table 2.
R thj-a
Thermal data
(1)
Thermal resistance junction-ambient Max
T l
Maximum lead temperature for soldering purpose
Typ
1.
Mounted on FR-4 board (t 10 sec.).
Value
60
±20
5
3
20
2.5
0.02
5.5
-55 to 150
150
50
150
Unit
V
V
A
A
A
W
W/°C
V/ns
°C
°C
°C/W
°C
3/12
Electrical characteristics STS5NF60L
(T
CASE
=25°C unless otherwise specified)
Table 3.
Symbol
On/off states
Parameter
V
(BR)DSS
Drain-source
Breakdown voltage
Test conditions
I
D
= 250 µA, V
GS
= 0
I
DSS
Zero gate voltage
Drain current (V
GS
= 0)
V
DS
= Max rating
V
DS
= Max rating,
T
C
=125°C
I
GSS
V
GS(th)
R
DS(on)
Gate-body leakage current (V
DS
= 0)
Gate threshold voltage
Static drain-source on resistance
V
GS
= ± 20V
V
DS
= V
GS
, I
D
= 250µA
V
GS
= 10V, I
D
= 2.5A
V
GS
= 4.5V, I
D
= 2.5A
Table 4.
Symbol g fs
(1)
C iss
C oss
C rss
Dynamic
Parameter Test conditions
Forward transconductance V
DS
= 15V, I
D
=2.5 A
Input capacitance
Output capacitance V
DS
= 25V, f = 1 MHz,
V
GS
= 0
Reverse transfer capacitance
Q g
Q gs
Q gd
Total gate charge
Gate-source charge
Gate-drain charge
V
DD
V
GS
= 48V, I
D
= 5V
= 5A,
1.
Pulsed: Pulse duration = 300 µs, duty cycle 1.5.
Table 5.
Symbol
Switching times
Parameter t d(on) t r t d(off) t f
Turn-on delay time
Rise time
Turn-off Delay Time
Fall Time
Min.
Typ.
Max.
Unit
60
1
10
V
µA
µA
1 1.7
0.045
0.050
±100 nA
2.5
0.055
0.065
V
Ω
Ω
Min.
Typ.
Max.
Unit
7
1250
130
S pF pF
26
17
4.5
6 pF nC nC nC
Test conditions
V
DD
=30 V, I
D
=2.5A,
R
G
=4.7
Ω, V
GS
= 4.5V
V
DD
= 30 V, I
D
= 2.5A
R
G
=4.7
Ω,
V
GS
= 4.5V
Min.
Typ.
Max.
Unit
13
28 ns ns
45
10 ns ns
4/12
STS5NF60L
Table 6.
Symbol
Source drain diode
Parameter Test conditions
I
SD
I
SDM
(1)
V
SD
(2)
I t
Q rr rr
RRM
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
1.
Pulse width limited by safe operating area.
2.
Pulsed: Pulse duration = 300 µs, duty cycle 1.5%
I
SD
= 5A, V
GS
= 0
I
SD
= 5A, V
DD
= 40V di/dt = 100A/µs,
T j
= 150°C
Electrical characteristics
Min Typ.
Max Unit
5
20
1.2
A
A
V
85
85
2 ns nC
A
5/12
Electrical characteristics
Figure 1.
Safe operating area Figure 2.
Thermal impedance
STS5NF60L
Figure 3.
Output characteristics Figure 4.
Transfer characteristics
Figure 5.
Transconductance Figure 6.
Static drain-source on resistance
6/12
STS5NF60L Electrical characteristics
Figure 7.
Gate charge vs. gate-source voltage Figure 8.
Capacitance variations
Figure 9.
Normalized gate threshold voltage vs. temperature
Figure 10. Normalized on resistance vs. temperature
Figure 11. Source-drain diode forward characteristics
7/12
Test circuit
3 Test circuit
Figure 12. Switching times test circuit for resistive load
Figure 13. Gate charge test circuit
STS5NF60L
Figure 14. Test circuit for inductive load switching and diode recovery times
Figure 15. Unclamped Inductive load test circuit
Figure 16. Unclamped inductive waveform Figure 17. Switching time waveform
8/12
STS5NF60L
4 Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at : www.st.com
9/12
Package mechanical data STS5NF60L
DIM.
M
S
F
L
D
E e e3 b b1
C c1
A a1 a2 a3
MIN.
0.1
0.65
0.35
0.19
0.25
4.8
5.8
3.8
0.4
SO-8 MECHANICAL DATA mm.
TYP MAX.
1.75
0.25
1.65
0.85
0.48
0.25
0.5
5.0
6.2
MIN.
0.003
0.025
0.013
0.007
0.010
45 (typ.)
0.188
0.228
1.27
3.81
4.0
1.27
0.6
8 (max.)
0.14
0.015
inch
TYP.
0.050
0.150
MAX.
0.068
0.009
0.064
0.033
0.018
0.010
0.019
0.196
0.244
0.157
0.050
0.023
10/12
STS5NF60L
Table 7.
Date
21-Jun-2004
06-Nov-2006
30-Jan-2007
Revision history
Revision
2
3
4
Changes
First release
The document has been reformatted
Typo mistake on
Revision history
11/12
STS5NF60L
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