STB8N90K5
Nchannel 900 V, 0.60 Ω typ., 8 A MDmesh™ K5
Power MOSFET in a D
2
PAK package
Datasheet - production data
TAB
2
1
3
D²PAK
Figure 1: Internal schematic diagram
Features
Order code V
DS
R
DS(on)
max.
STB8N90K5 900 V 0.68 Ω
Industry’s lowest R
DS(on)
x area
Industry’s best FoM (figure of merit)
Ultra-low gate charge
100% avalanche tested
Zener-protected
I
D
8 A
Applications
Switching applications
Description
This very high voltage N-channel Power
MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency.
Order code
STB8N90K5
Table 1: Device summary
Marking Package
8N90K5 D 2 PAK
Packing
Tape and reel
November 2016 DocID030104 Rev 1
This is information on a product in full production.
1/15 www.st.com
Contents
Contents
STB8N90K5
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
3 Test circuits ..................................................................................... 8
4 Package information ....................................................................... 9
4.1
4.2
D²PAK (TO-263) type A package information ................................... 9
D²PAK packing information ............................................................. 12
5 Revision history ............................................................................ 14
2/15 DocID030104 Rev 1
STB8N90K5
1 Electrical ratings
Symbol
Table 2: Absolute maximum ratings
Parameter
V
GS
I
D
(1)
I
D
(1)
I
D
(2)
P
TOT
dv/dt (3) dv/dt (4)
T
J
T stg
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current pulsed
Total dissipation at T
C
= 25 °C
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
Operating junction temperature range
Storage temperature range
Notes:
(1)
Limited by maximum junction temperature
(2)
Pulse width limited by safe operating area
(3)
I
SD
≤ 8 A, di/dt ≤ 100 A/μs; V
DS peak ≤ V
(BR)DSS
(4)
V
DS
≤ 720 V
Symbol
Table 3: Thermal data
Parameter
R thj-case
R
thj-pcb
(1)
Thermal resistance junction-case
Thermal resistance junction-pcb
Notes:
(1)
When mounted on FR-4 board of 1 inch², 2 oz Cu
Symbol
Table 4: Avalanche characteristics
Parameter
I
AR
E
AS
Avalanche current, repetitive or not repetitive
(pulse width limited by T
J max)
Single pulse avalanche energy
(starting T
J
= 25 °C, I
D
= I
AR
, V
DD
= 50 V)
Electrical ratings
Value
±30
8
5
32
130
4.5
50
-55 to 150
Unit
V
A
A
A
W
V/ns
°C
Value
0.96
30
Unit
°C/W
°C/W
Value
2.7
250
Unit
A mJ
DocID030104 Rev 1 3/15
Electrical characteristics
2 Electrical characteristics
T
C
= 25 °C unless otherwise specified
Symbol Parameter
Table 5: On/off-state
Test conditions
V
(BR)DSS
Drain-source breakdown voltage V
GS
= 0 V, I
D
= 1 mA
V
GS
= 0 V, V
DS
= 900 V
I
DSS
Zero gate voltage drain current V
GS
= 0 V, V
DS
T
C
= 125 °C (1)
= 900 V,
I
GSS
Gate body leakage current
V
GS(th)
Gate threshold voltage
V
V
DS
DS
= 0 V, V
= V
GS
, I
D
GS
= ±20 V
= 100 µA
R
DS(on)
Static drain-source on-resistance V
GS
= 10 V, I
D
= 4 A
Notes:
(1)
Defined by design, not subject to production test.
Symbol Parameter
Table 6: Dynamic
Test conditions
C iss
C oss
C rss
C
o(tr)
(1)
C
o(er)
(2)
R g
Q g
Q gs
Q gd
Input capacitance
Output capacitance
Reverse transfer capacitance
Equivalent capacitance time related
Equivalent capacitance energy related
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
V
DS
= 100 V, f = 1 MHz,
V
GS
= 0 V
V
DS
= 0 to 720 V,
V
GS
= 0 V f = 1 MHz , I
D
= 0 A
V
DD
= 720 V, I
D
= 8 A,
V
GS
= 10 V
(see Figure 15: "Test circuit for gate charge behavior" )
STB8N90K5
Min. Typ. Max. Unit
900 V
1 µA
50 µA
±10 µA
4 5 V
0.60 0.68
Ω
3
Min. Typ. Max. Unit
-
-
-
426
41
1.2
-
-
- pF pF pF
-
-
-
-
-
-
75
28
7
11
3.5
4.8
-
-
-
-
-
- pF pF
Notes:
(1)
Time related is defined as a constant equivalent capacitance giving the same charging time as Coss when V
DS increases from 0 to 80% V
DSS
(2)
Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when
V
DS
increases from 0 to 80% V
DSS
Ω nC nC nC
4/15 DocID030104 Rev 1
STB8N90K5
Symbol Parameter t d(on)
Turn-on delay time t r
Rise time t d(off)
Turn-off delay time t f
Fall time
Table 7: Switching times
Test conditions
V
DD
= 450 V, I
D
= 4 A,
R
G
= 4.7 Ω, V
GS
= 10 V
(see Figure 14: "Test circuit for resistive load switching times" and Figure 19: "Switching time waveform" )
Electrical characteristics
Min. Typ. Max. Unit
-
-
-
-
14.7
13.2
36.4
13.5
-
-
-
- ns ns ns ns
Symbol
I
SD
Source-drain current
I
SDM
(1)
Source-drain current
(pulsed)
V
SD
(2)
Forward on voltage t rr
Q rr
Reverse recovery time
Reverse recovery charge
I
I
RRM t
Q rr rr
RRM
Parameter
Reverse recovery current
Reverse recovery time
Table 8: Source-drain diode
Test conditions
Reverse recovery charge
Reverse recovery current
I
I
SD
SD
= 8 A, V
GS
= 0 V
= 8 A, di/dt = 100 A/µs,
V
DD
= 60 V
(see Figure 16: "Test circuit for inductive load switching and diode recovery times" )
I
SD
= 8 A, di/dt = 100 A/µs,
V
DD
= 60 V, T j
= 150 °C
(see Figure 16: "Test circuit for inductive load switching and diode recovery times" )
Min. Typ. Max. Unit
- 8 A
- 32 A
-
-
-
371
4.27
1.5 V ns
µC
-
-
-
-
23
582
5.73
19.7
A ns
µC
A
Notes:
(1)
Pulse width limited by safe operating area
(2)
Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Symbol
Table 9: Gate-source Zener diode
Parameter Test conditions Min Typ. Max Unit
V
(BR)GSO
Gate-source breakdown voltage I
GS
= ± 1mA, I
D
= 0A 30 - - V
The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection,thus eliminating the need for additional external componentry.
DocID030104 Rev 1 5/15
Electrical characteristics
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area
STB8N90K5
Figure 3: Thermal impedance
Figure 4: Output characteristics Figure 5: Transfer characteristics
Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance
6/15 DocID030104 Rev 1
STB8N90K5
Figure 8: Capacitance variations
Electrical characteristics
Figure 9: Normalized gate threshold voltage vs temperature
Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V
(BR)DSS
vs temperature
Figure 12: Source-drain diode forward characteristics
Figure 13: Maximum avalanche energy vs starting T
J
DocID030104 Rev 1 7/15
Test circuits
3 Test circuits
Figure 14: Test circuit for resistive load switching times
STB8N90K5
Figure 15: Test circuit for gate charge behavior
V
DD
RL
V
GS pulse width
2200
μF
+
1 kΩ
I
G
= CONST
2.7 kΩ
47 kΩ
100 Ω D.U.T.
V
G
AM01469v10
Figure 16: Test circuit for inductive load switching and diode recovery times
Figure 17: Unclamped inductive load test circuit
Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform
8/15 DocID030104 Rev 1
STB8N90K5
4
4.1
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
D²PAK (TO-263) type A package information
Figure 20: D²PAK (TO-263) type A package outline
DocID030104 Rev 1
0079457_A_rev22
9/15
Package information
Dim.
D2
E
E1
E2 e e1
H c c2
D
D1
A
A1 b b2
J1
L
L1
L2
R
V2
STB8N90K5
Table 10: D²PAK (TO-263) type A package mechanical data mm
Min. Typ.
4.40
0.03
0.70
1.14
0.45
1.23
8.95
7.50
1.10
10
8.50
6.85
8.70
7.05
2.54
4.88
15
2.49
2.29
1.27
1.30
7.75
1.30
0.4
0°
5.28
15.85
2.69
2.79
1.40
1.75
Max.
4.60
0.23
0.93
1.70
0.60
1.36
9.35
8.00
1.50
10.40
8.90
7.25
8°
10/15 DocID030104 Rev 1
STB8N90K5 Package information
Figure 21: D²PAK (TO-263) recommended footprint (dimensions are in mm)
DocID030104 Rev 1 11/15
Package information
4.2 D²PAK packing information
Figure 22: Tape outline
STB8N90K5
12/15 DocID030104 Rev 1
STB8N90K5
Figure 23: Reel outline
Package information
Dim.
K0
P0
P1
P2
R
T
W
A0
B0
D
D1
E
F
Min.
4.8
3.9
11.9
1.9
50
0.25
23.7
10.5
15.7
1.5
1.59
1.65
11.4
Table 11: D²PAK tape and reel mechanical data
Tape Reel mm
Max.
10.7
15.9
1.6
1.61
1.85
11.6
5.0
4.1
12.1
2.1
Dim.
Min.
A
B
C
D
G
N
T
Base quantity
Bulk quantity
1.5
12.8
20.2
24.4
100
0.35
24.3 mm
Max.
330
13.2
26.4
30.4
1000
1000
DocID030104 Rev 1 13/15
Revision history
5 Revision history
Date
28-Nov-2016
Revision
1
Table 12: Document revision history
Changes
First release
STB8N90K5
14/15 DocID030104 Rev 1
STB8N90K5
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DocID030104 Rev 1 15/15
