STB30N80K5
Nchannel 800 V, 0.15 Ω typ., 24 A, MDmesh™ K5
Power MOSFET in a D²PAK package
Datasheet - production data
TAB
2
1
3
D²PAK
Figure 1: Internal schematic diagram
Order code
STB30N80K5
Features
Order code V
DS
R
DS(on)
max.
STB30N80K5 800 V 0.18 Ω
Industry’s lowest R
DS(on)
x area
Industry’s best FoM (figure of merit)
Ultra-low gate charge
100% avalanche tested
Zener-protected
I
D
24 A
Applications
Switching applications
Description
This very high voltage N-channel Power
MOSFET is designed u sing MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency.
Table 1: Device summary
Marking Package
30N80K5 D²PAK
Packaging
Tape and reel
July 2016 DocID028737 Rev 2
This is information on a product in full production.
1/16 www.st.com
Contents
Contents
STB30N80K5
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
3 Test circuits ..................................................................................... 9
4 Package information ..................................................................... 10
4.1
4.2
D2PAK package information ........................................................... 10
D2PAK packaging information ........................................................ 13
5 Revision history ............................................................................ 15
2/16 DocID028737 Rev 2
STB30N80K5
1 Electrical ratings
Symbol
Table 2: Absolute maximum ratings
Parameter
V
DS
V
GS
I
D
I
D
I
DM
(1)
P
TOT
dv/dt (2) dv/dt (3)
T stg
T j
Drain-source voltage
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
Storage temperature range
Operating junction temperature range
Notes:
(1)
Pulse width limited by safe operating area.
(2)
I
SD
< 24 A, di/dt < 100 A/µs, V
DSpeak
< V
(BR)DSS
, V
DD
= 80% V
(BR)DSS
(3)
V
DS
= 640 V
Symbol
Table 3: Thermal data
Parameter
R thj-case
R
thj-pcb
(1)
Thermal resistance junction-case
Thermal resistance junction-pcb
Notes:
(1)
When mounted on FR-4 board of 1 inch², 2 oz Cu
Symbol
Table 4: Avalanche characteristics
Parameter
I
AR
E
AS
Avalanche current, repetitive or not repetitive
(pulse width limited by T jmax
.)
Single pulse avalanche energy
(starting T j
= 25 °C, I
D
= I
AR
, V
DD
= 50 V)
Electrical ratings
Value
800
±30
24
15
96
250
4.5
50
- 55 to 150
Unit
V
V
A
A
A
W
V/ns
°C
Value
0.5
30
Unit
°C/W
°C/W
Value
8
440
Unit
A mJ
DocID028737 Rev 2 3/16
Electrical characteristics
2 Electrical characteristics
(T
CASE
= 25 °C unless otherwise specified)
Symbol Parameter
Table 5: On/off states
Test conditions
V
(BR)DSS
Drain-source breakdown voltage
I
D
= 1 mA, V
GS
= 0 V
V
GS
= 0 V, V
DS
= 800 V
I
DSS
Zero gate voltage drain current
V
GS
= 0 V, V
DS
= 800 V,
T
C
= 125 °C (1)
I
GSS
Gate source leakage current
V
GS(th)
Gate threshold voltage
R
DS(on)
Static drain-source on-resistance
V
DS
= 0 V, V
GS
= ± 20 V
V
DD
= V
GS
, I
D
= 100 µA
V
GS
= 10 V, I
D
= 12 A
STB30N80K5
Min. Typ. Max. Unit
800 V
1 µA
50 µA
±10 µA
4 5 V
0.15 0.18 Ω
3
Notes:
(1)
Defined by design, not subject to production test.
Symbol Parameter
Table 6: Dynamic
Test conditions
C iss
C oss
C rss
C
o(er)
(1)
C
o(tr)
(2)
Q g
Q gs
Q gd
R g
Input capacitance
Output capacitance
Reverse transfer capacitance
Equivalent capacitance energy related
Equivalent capacitance time related
Total gate charge
Gate-source charge
Gate-drain charge
Gate input resistance
V
DS
= 100 V, f = 1 MHz,
V
GS
= 0 V
V
GS
= 0 V,
V
DS
= 0 to 640 V
V
DD
= 640 V, I
D
= 24 A,
V
GS
= 10 V
(see Figure 16: "Test circuit for gate charge behavior" )
f =1 MHz, I
D
= 0 A
Min. Typ. Max. Unit
-
-
1530
145
-
- pF pF
-
-
-
-
-
-
-
1.2
91
244
43
12.8
24.2
3.5
-
-
-
-
-
-
- pF pF pF nC nC nC
Ω
Notes:
(1)
Energy related is defined as a constant equivalent capacitance giving the same stored energy as C oss
when V
DS increases from 0 to 80% V
DSS
(2)
Time related is defined as a constant equivalent capacitance giving the same stored energy as C oss
when V
DS increases from 0 to 80% V
DSS
4/16 DocID028737 Rev 2
STB30N80K5
Symbol Parameter
Table 7: Switching times
Test conditions t d(on)
Turn-on delay time t r
Rise time t d(off)
Turn-off delay time t f
Fall time
V
DS
= 400 V, I
D
= 12 A,
R
G
=
4.7 Ω,
V
GS
= 10 V
(see Figure 15: "Test circuit for resistive load switching times" )
Symbol
I
SD
Source-drain current
I
SDM
(1)
Source-drain current
(pulsed)
V
SD
(2)
Forward on voltage t rr
Q rr
Reverse recovery time
Reverse recovery charge
I
I
RRM t
Q rr rr
RRM
Parameter
Reverse recovery current
Reverse recovery time
Table 8: Source-drain diode
Test conditions
Reverse recovery charge
Reverse recovery current
I
SD
= 24 A, V
GS
= 0 V
I
SD
= 24 A, di/dt = 100 A/µs
V
DD
= 60 V
(see Figure 17: "Test circuit for inductive load switching and diode recovery times" )
I
SD
= 24 A, di/dt = 100 A/µs
V
DD
= 60 V, T j
= 150 °C
(see Figure 17: "Test circuit for inductive load switching and diode recovery times" )
Electrical characteristics
Min. Typ. Max. Unit
-
-
-
-
21
15
100
13.5
-
-
-
- ns ns ns ns
Min. Typ. Max. Unit
- 24 A
- 96 A
-
-
-
555
9.95
1.5 V ns
µC
-
-
-
-
36
765
13.2
34.5
A ns
µC
A
Notes:
(1)
Pulse width limited by safe operating area.
(2)
Pulsed: pulse duration = 300 µs, duty cycle 1.5%.
Symbol
Table 9: Gate-source Zener diode
Parameter Test conditions
V
(BR)GSO
Gate-source breakdown voltage I
GS
= ±1 mA, I
D
= 0 A
Min. Typ. Max. Unit
30 - - V
The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry.
DocID028737 Rev 2 5/16
Electrical characteristics
2.2 Electrical characteristics (curves)
Figure 2: Safe operating area
STB30N80K5
Figure 3: Thermal impedance
K
δ=0.5
0.2
0.1
10 -1
0.05
0.02
Zth= K*Rthj-c
δ= tp/ Ƭ
0.01
Single pulse
10 -2
10 -5 10 -4 10 -3 10 -2 tp
Ƭ
10 -1 t
P
(s)
Figure 4: Output characteristics Figure 5: Transfer characteristics
6/16
Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance
DocID028737 Rev 2
STB30N80K5
Figure 8: Capacitance variations
Electrical characteristics
Figure 9: Normalized gate threshold voltage vs temperature
Figure 10: Normalized on-resistance vs temperature
Figure 11: Normalized V
(BR)DSS
vs temperature
Figure 12: Maximum avalanche energy vs starting T
J
Figure 13: Source-drain diode forward characteristics
DocID028737 Rev 2 7/16
Electrical characteristics
Figure 14: Output capacitance stored energy
STB30N80K5
8/16 DocID028737 Rev 2
STB30N80K5
3 Test circuits
Figure 15: Test circuit for resistive load switching times
Test circuits
Figure 16: Test circuit for gate charge behavior
Figure 17: Test circuit for inductive load switching and diode recovery times
Figure 18: Unclamped inductive load test circuit
Figure 19: Unclamped inductive waveform Figure 20: Switching time waveform
DocID028737 Rev 2 9/16
Package information
4
4.1
Package information
STB30N80K5
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
D 2 PAK package information
Figure 21: D²PAK (TO-263) type A package outline
10/16 DocID028737 Rev 2
0079457_A_rev22
STB30N80K5
Dim.
D2
E
E1
E2 e e1
H c c2
D
D1
A
A1 b b2
J1
L
L1
L2
R
V2
Package information
Table 10: D²PAK (TO-263) type A package mechanical data mm
Min. Typ. Max.
4.88
15
2.49
2.29
1.27
1.30
4.40
0.03
0.70
1.14
0.45
1.23
8.95
7.50
1.10
10
8.50
6.85
0.4
7.75
1.30
8.70
7.05
2.54
5.28
15.85
2.69
2.79
1.40
1.75
4.60
0.23
0.93
1.70
0.60
1.36
9.35
8.00
1.50
10.40
8.90
7.25
0° 8°
DocID028737 Rev 2 11/16
Package information STB30N80K5
Figure 22: D²PAK (TO-263) recommended footprint (dimensions are in mm)
12/16 DocID028737 Rev 2
STB30N80K5
4.2 D 2 PAK packaging information
Figure 23: Tape outline
Package information
DocID028737 Rev 2 13/16
Package information
Figure 24: Reel outline
STB30N80K5
14/16
Dim.
K0
P0
P1
P2
R
T
W
A0
B0
D
D1
E
F
Min.
4.8
3.9
11.9
1.9
50
0.25
23.7
10.5
15.7
1.5
1.59
1.65
11.4
Table 11: D²PAK tape and reel mechanical data
Tape Reel mm
Max.
10.7
15.9
1.6
1.61
1.85
11.6
5.0
4.1
12.1
2.1
Dim.
Min.
A
B
C
D
G
N
T
Base quantity
Bulk quantity
1.5
12.8
20.2
24.4
100
0.35
24.3 mm
Max.
330
13.2
26.4
30.4
1000
1000
DocID028737 Rev 2
STB30N80K5
5 Revision history
Date
Table 12: Document revision history
Revision Changes
14-Dec-2015
06-Jul-2016
1
2
First release.
Modified: features in cover page.
Added: note in Table 5: "On/off states" .
Modified: Figure 3: "Thermal impedance" .
Minor text changes.
Revision history
DocID028737 Rev 2 15/16
STB30N80K5
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16/16 DocID028737 Rev 2
