STF11NM50N
Nchannel 500 V, 0.40 Ω typ., 8.5 A MDmesh™ II
Power MOSFET in a TO-220FP package
Datasheet - production data
TO-220FP
Figure 1: Internal schematic diagram
Features
Order code V
DS
@ T
J max R
DS(on) max I
D
STF11NM50N 550 V 0.47 Ω
100% avalanche tested
Low input capacitance and gate charge
Low gate input resistance
8.5 A
Applications
Switching applications
Description
This device is an N-channel Power MOSFET developed using the second generation of
MDmesh™ technology. This revolutionary Power
MOSFET associates a vertical structure to the company’s strip layout to yield one of the world’s lowest on-resistance and gate charge. It is therefore suitable for the most demanding high efficiency converters.
Order code
STF11NM50N
Table 1: Device summary
Marking Package
11NM50N TO-220FP
Packaging
Tube
June 2016 DocID028675 Rev 2
This is information on a product in full production.
1/13 www.st.com
Contents
Contents
STF11NM50N
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
3 Test circuits ..................................................................................... 8
4 Package information ....................................................................... 9
4.1
TO-220FP package information ...................................................... 10
5 Revision history ............................................................................ 12
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STF11NM50N
1
Electrical ratings
Electrical ratings
Symbol
Table 2: Absolute maximum ratings
Parameter
V
DS
Drain-source voltage
V
GS
I
D
(1)
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
I
D
(1)
Drain current (continuous) at T
C
= 100 °C
I
DM
(1)(2)
Drain current (pulsed)
P
TOT
Total dissipation at T
C
= 25 °C
dv/dt (3)
Peak diode recovery voltage slope
V
ISO
Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1 s; T
C
= 25 °C)
T stg
T j
Storage temperature range
Operating junction temperature range
Notes:
(1)
Limited by maximum junction temperature
(2)
Pulse width limited by safe operating area.
(3)
I
SD
≤ 8.5 A, di/dt ≤ 400 A/µs, V
DS(peak)
≤ V
(BR)DSS,
V
DD
≤ 80% V
(BR)DSS
Symbol
Table 3: Thermal data
Parameter
R thj-case
R thj-amb
Thermal resistance junction-case max
Thermal resistance junction-ambient max
Symbol
I
AR
E
AS
Table 4: Avalanche characteristics
Parameter
Avalanche current, repetitive or not-repetitive
(pulse width limited by T j max
)
Single pulse avalanche energy
(starting T
J
=25 °C, I
D
=I
AR
, V
DD
=50 V)
Value
500
±25
8.5
6
34
25
15
2500
-55 to 150 °C
Value
5
62.5
Value
3
150
Unit
°C/W
°C/W mJ
Unit
V
V
A
A
A
W
V/ns
V
Unit
A
DocID028675 Rev 2 3/13
Electrical characteristics
2 Electrical characteristics
(T
CASE
= 25 °C unless otherwise specified)
Symbol Parameter
Table 5: On/off states
Test conditions
V
(BR)DSS
Drain-source breakdown voltage
I
D
= 1 mA, V
GS
= 0 V
I
DSS
Zero gate voltage drain current
I
GSS
Gate-body leakage current
V
GS(th)
Gate threshold voltage
R
DS(on)
Static drain-source onresistance
V
GS
= 0 V, V
DS
= 500 V
V
GS
= 0 V, V
DS
= 500 V,
T
C
= 125 °C (1)
V
DS
= 0 V, V
GS
= ±25 V
V
DS
= V
GS
, I
D
= 250 µA
V
GS
= 10 V, I
D
= 4.5 A
STF11NM50N
Min. Typ. Max. Unit
500 V
1
µA
100
3
±100 nA
4 V
0.40 0.47 Ω
2
Notes:
(1)
Defined by design, not subject to production test.
Symbol Parameter
Table 6: Dynamic
Test conditions
C iss
C oss
C rss
C oss eq.
(1)
Q g
Q gs
Q gd
R
G
Input capacitance
Output capacitance
Reverse transfer capacitance
Total gate charge
Gate-source charge
Gate-drain charge
Gate input resistance
V
DS
= 50 V, f = 1 MHz,
V
GS
= 0 V
Equivalent output capacitance V
GS
= 0 V, V
DS
= 0 to 400 V
V
DD
= 400 V, I
D
= 8.5 A,
V
GS
= 10 V (see Figure 14:
"Test circuit for gate charge behavior"
f=1 MHz, I
D
=0 A
-
-
-
-
Min. Typ. Max. Unit
-
-
-
547
42
2
-
-
- pF pF pF
- 210
19
3.7
10
5.8
-
-
-
-
- pF nC nC nC
Ω
Notes:
(1)
C oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C oss
when V
DS increases from 0 to 80% V
DS
Symbol Parameter
Table 7: Switching times
Test conditions Min. Typ. Max. Unit t d(on)
Turn-on delay time t r
Rise time t d(off)
Turn-off delay time t f
Fall time
V
DD
= 250 V, I
D
= 4.25 A,
R
G
= 4.7 Ω, V
GS
= 10 V
(see Figure 13: "Test circuit for resistive load switching times" and Figure 18: "Switching time waveform" )
-
-
-
-
8
10
33
10
-
-
-
- ns ns ns ns
4/13 DocID028675 Rev 2
STF11NM50N
Symbol Parameter
Table 8: Source-drain diode
Test conditions
I
I
SD
(1)
SDM
Source-drain current
Source-drain current (pulsed)
V
SD
(2)
Forward on voltage I
SD
= 8.5 A, V
GS
= 0 V t rr
Q rr
I
RRM t rr
Q rr
I
RRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
SD
= 8.5 A, di/dt = 100 A/µs
V
DD
= 60 V (see Figure 15:
"Test circuit for inductive load switching and diode recovery times" )
I
SD
= 8.5 A, di/dt = 100 A/µs
V
DD
= 60 V, T j
= 150 °C
(see Figure 15: "Test circuit for inductive load switching and diode recovery times" )
Electrical characteristics
Min. Typ. Max. Unit
-
-
-
-
-
-
-
-
230
2.1
18
275
2.5
18
8.5
34
1.5
A
A
V ns
µC
A ns
µC
A
Notes:
(1)
Pulse width limited by safe operating area.
(2)
Pulsed: pulse duration = 300 µs, duty cycle 1.5%
DocID028675 Rev 2 5/13
Electrical characteristics
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area
STF11NM50N
Figure 3: Thermal impedance
Figure 4: Output characteristics Figure 5: Transfer characteristics
Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on resistance
6/13 DocID028675 Rev 2
STF11NM50N
Figure 8: Capacitance variations
Electrical characteristics
Figure 9: Output capacitance stored energy
Figure 10: Normalized gate threshold voltage vs temperature
Figure 11: Normalized on-resistance vs temperature
Figure 12: Normalized V(BR)DSS vs temperature
DocID028675 Rev 2 7/13
Test circuits
3 Test circuits
Figure 13: Test circuit for resistive load switching times
STF11NM50N
Figure 14: Test circuit for gate charge behavior
8/13
Figure 15: Test circuit for inductive load switching and diode recovery times
Figure 16: Unclamped inductive load test circuit
Figure 17: Unclamped inductive waveform
Figure 18: Switching time waveform
DocID028675 Rev 2
STF11NM50N
4
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
DocID028675 Rev 2 9/13
Package information
4.1 TO-220FP package information
Figure 19: TO-220FP package outline
STF11NM50N
10/13 DocID028675 Rev 2
STF11NM50N
Dim.
G1
H
L2
L3
L4
L5
L6
L7
Dia
F
F1
F2
G
A
B
D
E
Table 9: TO-220FP package mechanical data mm
Min. Typ.
4.4
2.5
2.5
0.45
0.75
1.15
1.15
4.95
2.4
10
16
28.6
9.8
2.9
15.9
9
3
Package information
Max.
4.6
2.7
2.75
0.7
1
1.70
1.70
5.2
2.7
10.4
30.6
10.6
3.6
16.4
9.3
3.2
DocID028675 Rev 2 11/13
Revision history
5
STF11NM50N
Revision history
Date Revision
Table 10: Document revision history
Changes
25-Nov-2015
09-Jun-2016
1
2
First release. Part number previously included in datasheet
DocID17156.
Updated I
GSS
unit from µA to nA in Table 5: "On/off states" .
Updated Table 7: "Switching times" modifying references in test
conditions.
Document reformatted with the current standard with minor text changes to improve readability.
12/13 DocID028675 Rev 2
STF11NM50N
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DocID028675 Rev 2 13/13
