I/O ports ST7L34 ST7L35 ST7L38 ST7L39
10.1 Introduction
The I/O ports allow data transfer. An I/O port contains up to eight pins. Each pin can be programmed independently either as a digital input or digital output. In addition, specific pins may have several other functions. These functions can include external interrupt, alternate signal input/output for on-chip peripherals or analog input.
A data register (DR) and a data direction register (DDR) are always associated with each port. The option register (OR), which allows input/output options, may or may not be implemented. The following description takes into account the OR register. Refer
to Section 10.7: Device-specific I/O port configuration on page 73
for device specific information.
An I/O pin is programmed using the corresponding bits in the DDR, DR and OR registers:
Bit x corresponding to pin x of the port.
Figure 32: I/O port general block diagram on page 70
shows the generic I/O block diagram.
Clearing the DDRx bit selects input mode. In this mode, reading its DR bit returns the digital value from that I/O pin.
If an OR bit is available, different input modes can be configured by software: Floating or pull-up. Refer to
Section 10.3: I/O port implementation on page 72
for configuration.
Note: 1 Writing to the DR modifies the latch value but does not change the state of the input pin.
2 Do not use read/modify/write instructions (BSET/BRES) to modify the DR register.
External interrupt function
Depending on the device, setting the ORx bit while in input mode can configure an I/O as an input with interrupt. In this configuration, a signal edge or level input on the I/O generates an interrupt request via the corresponding interrupt vector (eix).Falling or rising edge sensitivity is programmed independently for each interrupt vector. The external interrupt control register (EICR) or the miscellaneous register controls this sensitivity, depending on the device.
description in
Section 2: Pin description on page 16
and interrupt section).If several I/O interrupt pins on the same interrupt vector are selected simultaneously, they are logically combined. For this reason, if one of the interrupt pins is tied low, it may mask the others.
External interrupts are hardware interrupts. Fetching the corresponding interrupt vector automatically clears the request latch. Changing the sensitivity bits clears any pending interrupts.
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Setting the DDRx bit selects output mode. Writing to the DR bits applies a digital value to the
I/O through the latch. Reading the DR bits returns the previously stored value.
If an OR bit is available, different output modes can be selected by software: Push-pull or open-drain. Refer to
Section 10.3: I/O port implementation on page 72
for configuration.
Table 23.
DR value and output pin status
DR Push-pull
0
1
V
OL
V
OH
Open-drain
V
OL
Floating
Many ST7 I/Os have one or more alternate functions. These may include output signals
from, or input signals to, on-chip peripherals. Table 2: Device pin description on page 17
describes which peripheral signals can be input/output to which ports.
A signal coming from an on-chip peripheral can be output on an I/O. To do this, enable the on-chip peripheral as an output (enable bit in the peripheral’s control register). The peripheral configures the I/O as an output and takes priority over standard I/O programming.
The I/O’s state is readable by addressing the corresponding I/O data register.
Configuring an I/O as floating enables alternate function input. It is not recommended to configure an I/O as pull-up as this increases current consumption. Before using an I/O as an alternate input, configure it without interrupt. Otherwise spurious interrupts can occur.
Configure an I/O as input floating for an on-chip peripheral signal which can be input and output.
Caution: I/Os which can be configured as both an analog and digital alternate function need special attention. The user must control the peripherals so that the signals do not arrive at the same time on the same pin. If an external clock is used, only the clock alternate function should be employed on that I/O pin and not the other alternate function.
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ST7L34 ST7L35 ST7L38 ST7L39 I/O ports
Figure 32.
I/O port general block diagram
Register access
Alternate output from on-chip peripheral
1
0
Alternate enable bit
DR
V
DD
P-buffer
(see table below)
Pull-up
(see table below
V
DD
DDR
Pad
Pull-up condition
If implemented
OR
OR SEL
N-buffer
DDR SEL
Diodes
(see table below)
Analog input
DR SEL
1
0
External
Interrupt request (eix)
Sensitivity selection
Combinational
Logic From other bits
CMOS
Schmitt trigger
Alternate input to on-chip peripheral
Table 24.
I/O port mode options
(1)
Diodes
Configuration mode Pull-up P-buffer to V
DD
(2) to V
SS
Floating with/without interrupt Off
Input
Pull-up with/without interrupt On
Off
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On Push-pull On
Off
Output Open drain (logic level) Off
NI
(3)
True open drain NI NI
1.
Legend: Off = implemented not activated; On = implemented and activated
2.
The diode to V
DD
is not implemented in the true open drain pads. A local protection between the pad and V
OL
is implemented to protect the device against positive stress.
3.
For further details on port configuration, please refer to
Table 28: Port configuration (standard ports) and Table 29: Port configuration (external interrupts) on page 73 .
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