On-chip peripherals ST7L34 ST7L35 ST7L38 ST7L39
Extended prescaler mode
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Two additional prescalers are available in extended prescaler mode. They are shown in
Figure 58: SCI baud rate and extended prescaler block diagram on page 131
.
An extended prescaler receiver register (SCIERPR)
An extended prescaler transmitter register (SCIETPR)
Serial data format
Word length may be selected as being either 8 or 9 bits by programming the M bit in the
SCICR1 register (see
Figure 57 ).
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
An idle character is interpreted as a continuous logic high level for 10 (or 11) full bit times.
A break character is a character with a sufficient number of low level bits to break the normal data format followed by an extra “1” bit to acknowledge the start bit.
Figure 57.
Word length programming
9-bit word length (M bit is set)
Start bit
Bit0 Bit1
Data character
Bit2 Bit3 Bit4 Bit5 Bit6
Possible parity bit
Bit7 Bit8 Stop bit
Next start bit
Next data character
Idle line
Start
Bit
Break character
Extra
’1’
Start bit
8-bit word length (M bit is reset)
Data character
Start bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6
Possible parity bit
Bit7
Stop bit
Next start bit
Next data character
Idle line
Start bit
Start
Break character
Extra
’1’ bit Obsolete Product(s) - Obsolete Product(s)
Transmitter
The transmitter can send data words of either 8 or 9 bits depending on the M bit status.
When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the
T8 bit in the SCICR1 register.
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ST7L34 ST7L35 ST7L38 ST7L39
Note:
On-chip peripherals
Character transmission
During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this mode, the SCIDR register consists of a buffer (TDR) between the internal bus and the
transmit shift register (see Figure 56 ).
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Procedure
Select the M bit to define the word length.
Select the desired baud rate using the SCIBRR and the SCIETPR registers.
Set the TE bit to send a preamble of 10 (M = 0) or 11 (M = 1) consecutive ones (idle line) as first transmission.
● Access the SCISR register and write the data to send in the SCIDR register (this sequence clears the TDRE bit). Repeat this sequence for each data to be transmitted.
Clearing the TDRE bit is always performed by the following software sequence:
1.
An access to the SCISR register
2. A write to the SCIDR register
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The TDRE bit is set by hardware and it indicates:
The TDR register is empty
The data transfer is beginning
The next data can be written in the SCIDR register without overwriting the previous data
This flag generates an interrupt if the TIE bit is set and the I[|1:0] bits are cleared in the CCR register.
When a transmission is taking place, a write instruction to the SCIDR register stores the data in the TDR register and which is copied in the shift register at the end of the current transmission.
When no transmission is taking place, a write instruction to the SCIDR register places the data directly in the shift register, the data transmission starts, and the TDRE bit is immediately set.
When a character transmission is complete (after the stop bit) the TC bit is set and an interrupt is generated if the TCIE is set and the I[1:0] bits are cleared in the CCR register.
Clearing the TC bit is performed by the following software sequence:
1.
An access to the SCISR register
2. A write to the SCIDR register
The TDRE and TC bits are cleared by the same software sequence.
Setting the SBK bit loads the shift register with a break character. The break character length depends on the M bit (see
Figure 57: Word length programming on page 126
).
As long as the SBK bit is set, the SCI sends break characters to the TDO pin. After clearing this bit by software, the SCI inserts a logic 1 bit at the end of the last break character to guarantee the recognition of the start bit of the next character.
Idle line
Setting the TE bit drives the SCI to send a preamble of 10 (M = 0) or 11 (M = 1) consecutive
‘1’s (idle line) before the first character.
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