STMicroelectronics ST7LITE49M Datasheet
Iklan
Iklan
ST7LITE49M
8-bit MCU with single voltage Flash memory data EEPROM, ADC, 8/12-bit timers, and I²C interface
Features
■
■
■
Memories
– 4 Kbytes single voltage extended Flash
(XFlash) Program memory with
Read-Out Protection
In-circuit programming and in-application programming (ICP and IAP)
Endurance: 10k write/erase cycles guaranteed
Data retention: 20 years at 55 °C
– 384 bytes RAM
– 128 bytes data EEPROM with Read-Out
Protection.
300K write/erase cycles guaranteed, data retention: 20 years at 55 °C.
Clock, reset and supply management
– 3-level low voltage supervisor (LVD) for main supply and an auxiliary voltage detector (AVD) for safe power-on/off
– Clock sources: Internal trimmable 8 MHz
RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
– Five power saving modes: Halt, Active-halt,
Auto-wakeup from Halt, Wait and Slow
I/O Ports
– Up to 24 multifunctional bidirectional I/Os
– 8 high sink outputs
Table 1.
Device summary
Features
Program memory
RAM (stack) - bytes
Data EEPROM - bytes
Operating supply
CPU frequency
Operating temperature
Packages
LQFP32
(7x7mm)
SDIP32
■
■
■
■
■
■
5 timers
– Configurable watchdog timer
– Dual 8-bit Lite timers with prescaler,
1 real-time base and 1 input capture
– Dual 12-bit Auto-reload timers with 4 PWM outputs, input capture, output compare, dead-time generation and enhanced one- pulse mode functions
Communication interface:
– I²C multimaster interface
A/D converter: 10 input channels
Interrupt management
– 13 interrupt vectors plus TRAP and RESET
Instruction set
– 8-bit data manipulation
– 63 basic instructions with illegal opcode detection
– 17 main addressing modes
– 8 x 8 unsigned multiply instructions
Development tools
– Full HW/SW development package
– DM (Debug Module)
ST7LITE49M
4 Kbytes
384 (128)
128
2.4 to 5.5 V
Up to 8 MHz
-40 to +125 °C
LQFP32, SDIP32
November 2009 Doc ID 13562 Rev 3 1/188 www.st.com
1
Contents
Contents
ST7LITE49M
Register and memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Flash programmable memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
In-circuit programming (ICP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
In-application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Flash write/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Description of Flash control/status register (FCSR) . . . . . . . . . . . . . . . . . 23
Read operation (E2LAT=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Write operation (E2LAT=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Data EEPROM read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
EEPROM control/status register (EECSR) . . . . . . . . . . . . . . . . . . . . . . . . 27
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ST7LITE49M
Contents
Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Condition code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Auto-wakeup RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Crystal/ceramic oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
External power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Internal low voltage detector (LVD) reset . . . . . . . . . . . . . . . . . . . . . . . . 39
Internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Auxiliary voltage detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Main clock control/status register (MCCSR) . . . . . . . . . . . . . . . . . . . . . 44
RC control register (RCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
System integrity (SI) control/status register (SICSR) . . . . . . . . . . . . . . . 45
AVD threshold selection register (AVDTHCR) . . . . . . . . . . . . . . . . . . . . 46
Clock controller control/status register (CKCNTCSR) . . . . . . . . . . . . . . 47
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Contents
ST7LITE49M
Masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Servicing pending interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Concurrent and nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Description of interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
CPU CC register interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Interrupt software priority registers (ISPRx) . . . . . . . . . . . . . . . . . . . . . . 53
External interrupt control register (EICR) . . . . . . . . . . . . . . . . . . . . . . . . 56
Active-halt and Halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Auto-wakeup from Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
AWUFH control/status register (AWUCSR) . . . . . . . . . . . . . . . . . . . . . . 66
AWUFH prescaler register (AWUPR) . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Analog alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Device-specific I/O port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
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ST7LITE49M
Contents
Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
C bus interface (I
2
C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Doc ID 13562 Rev 3 5/188
Contents
ST7LITE49M
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Immediate mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Indexed modes (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . 132
Indirect modes (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Indirect indexed modes (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Relative modes (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Operating conditions with low voltage detector (LVD) . . . . . . . . . . . . . 142
Auxiliary voltage detector (AVD) thresholds . . . . . . . . . . . . . . . . . . . . . 143
Voltage drop between AVD flag setting and LVD reset generation . . . 143
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 150
6/188 Doc ID 13562 Rev 3
ST7LITE49M Contents
2
C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Auto-wakeup from Halt oscillator (AWU) . . . . . . . . . . . . . . . . . . . . . . . 152
Crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 153
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
EMC (electromagnetic compatibility) characteristics . . . . . . . . . . . . . . . 156
Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . 156
EMI (electromagnetic interference) . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 157
General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
14 Device configuration and ordering information . . . . . . . . . . . . . . . . . 173
Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Order codes for development and programming tools . . . . . . . . . . . . . 177
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Doc ID 13562 Rev 3 7/188
List of tables
List of tables
ST7LITE49M
Effect of low power modes on the I
C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
2
C delay times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
2
C register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
8/188 Doc ID 13562 Rev 3
ST7LITE49M List of tables
Instructions supporting direct, indexed, indirect and indirect indexed addressing modes 133
2
C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
2
C interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
32-pin plastic dual in-line package, shrink 400-mil width,
Doc ID 13562 Rev 3 9/188
List of figures
List of figures
ST7LITE49M
10/188 Doc ID 13562 Rev 3
ST7LITE49M List of figures
2
2
C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
C interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
fCPU maximum operating frequency versus VDD
supply voltage . . . . . . . . . . . . . . . . . . 142
Frequency vs voltage at four different ambient temperatures (RC at 5 V) . . . . . . . . . . . . 145
Frequency vs voltage at four different ambient temperatures (RC at 3.3 V). . . . . . . . . . . 145
Accuracy in % vs voltage at 4 different ambient temperatures (RC at 5 V) . . . . . . . . . . . 146
Accuracy in % vs voltage at 4 different ambient temperatures
resistance versus voltage at four different temperatures . . . . . . . . . . . . . . . . . . . . . . 159
pu
current versus voltage at four different temperatures . . . . . . . . . . . . . . . . . . . . . . . . . 159
= 2 mA (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
= 4 mA (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
= 2 mA (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
IO
= 8 mA (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
= 12 mA (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
DD
at IIO = 2 mA (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Doc ID 13562 Rev 3 11/188
List of figures ST7LITE49M
12/188 Doc ID 13562 Rev 3
ST7LITE49M
1 Description
Description
The ST7LITE49M is a member of the ST7 microcontroller family. All ST7 devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set.
The ST7LITE49M features Flash memory with byte-by-byte in-circuit programming (ICP) and in-application programming (IAP) capability.
Under software control, the ST7LITE49M device can be placed in Wait, Slow, or Halt mode, reducing power consumption when the application is in idle or standby state.
The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.
The ST7LITE49M features an on-chip Debug Module (DM) to support in-circuit debugging
(ICD). For a description of the DM registers, refer to the ST7 ICC protocol reference manual.
Figure 1.
ST7LITE49M general block diagram
CLKIN
OSC1
OSC2
V
DD
V
SS
RESET
/ 2
Ext.
OSC
1MHz to
16MHz
Int.
8 MHz
RC OSC
Int.
32 kHz
RC OSC
/ 2
LVD, AVD
Power
Supply
Control
8-bit core
ALU
Flash program memory
(4K bytes)
RAM
(384 bytes)
Data EEPROM
(128 bytes)
Internal clock
12-bit
Auto-reload dual timer
8-bit dual Lite timer
Port A
Port B
Port C
10-bit ADC
I
2
C
Watchdog
Debug module
PA7:0
(8 bits)
PB7:0
(8 bits)
PC7:0
(8 bits)
Doc ID 13562 Rev 3 13/188
Pin description ST7LITE49M
Figure 2.
32-pin SDIP package pinout
BREAK/PC7
PA0(HS)
ATIC/PA1(HS)
ATPWM0/PA2(HS)
ATPWM1/PA3(HS)
ATPWM2/MCO/PA4(HS)
ATPWM3/PA5(HS)
I2CDATA/PA6(HS)
I2CCLK/PA7(HS)
RESET
NC
V
DD
V
SS
OSC1/CLKIN
OSC2
V
SSA
10
11
12
13
14
15
16
8
9
6
7
3
4
5
1
2 ei2 ei0 ei2 ei2 ei1
26
25
24
23
22
21
20
19
18
17
32
31
30
29
28
27
PC6
PC5
PC4/LTIC
PC3/ICCCLK
PC2/ICCDATA
PC1/AIN9
PC0/AIN8
PB7/AIN7
PB6/AIN6
PB5/AIN5
PB4/AIN4
PB3/AIN3
PB2/AIN2
PB1/AIN1/CLKIN
PB0/AIN0
V
DDA
(HS) 20 mA high sink capability eix associated external interrupt vector
Note 1: Available on 8 Kbytes version only
Figure 3.
32-pin LQFP 7x7 package pinout
14/188
ATPWM1/PA3(HS)
ATPWM2/MCO/PA4(HS)
ATPWM3/PA5(HS)
I2CDATA/PA6(HS)
I2CCLK/PA7(HS)
RESET
NC
V
DD
4
5
6
7
8
2
3
1
32 31 30 29 28 27 26 25
24 ei0 ei2 23
22 ei1
21
20
19
18
9 10 11 12 13 14 15 16
17
PC2/ICCDATA
PC1/AIN9
PC0/AIN8
PB7/AIN7
PB6/AIN6
PB5/AIN5
PB4/AIN4
PB3/AIN3
(HS) 20 mA high sink capability eix associated external interrupt vector
Doc ID 13562 Rev 3
ST7LITE49M
Legend / Abbreviations for Table 2
:
Type: I = input, O = output, S = supply
In/Output level: C
T
= CMOS 0.3V
DD
/0.7V
DD
with input trigger
Output level: HS = 20 mA high sink (on N-buffer only)
Pin description
Table 2.
Pin number
●
●
Port and control configuration:
Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog
Output: OD = open-drain, PP = push-pull
The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state.
Device pin description
Level Port/control
Pin name Input Output
Main function
(after reset)
Alternate function
1
2
3
4
5
6
7
8
5 9
6 10
8 12
9 13
PA3(HS)/ATPWM1 I/O C
T
HS x
PA4(HS)/
ATPWM2/MCO
I/O C
T
HS x
PA5 (HS)ATPWM3 I/O C
T
HS x
PA6(HS)/
I2CDATA
I/O C
T
HS x
PA7(HS)/I2CCLK I/O C
T
HS x
RESET
V
DD
(2)
V
SS
(2) x ei0 ei0
10 14 OSC1/CLKIN I
11 15
12 16
13 17
OSC2
V
SSA
(2)
V
DDA
(2)
O
T
T x x x x x x x
Port A3
(HS)
Port A4
(HS)
Port A5
(HS)
ATPWM1
ATPWM2/
MCO
ATPWM3
Port A6
(HS)
Port A7
(HS)
Reset
I2CDATA
I2CCLK
Resonator oscillator inverter input or external clock input
Resonator oscillator output
Doc ID 13562 Rev 3 15/188
Pin description
Table 2.
Pin number
Device pin description
Pin name
Level
ST7LITE49M
Port/control
Input Output
Main function
(after reset)
Alternate function
14
15
18
19
16 20
17 21
18 22
19 23
20 24
21 25
22 26
23 27
24 28
25 29
26 30
27 31
28 32
29 1
30 2
31
32
3
4
PB0/AIN0
PB1/AIN1/CLKIN
PB2/AIN2
PB3/AIN3
PB4/AIN4
PB5/AIN5
PB6/AIN6
PB7/AIN7
PC0/AIN8
PC1/AIN9
PC2/ICCDATA
PC3/ICCCLK
PC4/LTIC
PC5
PC6
PC7/BREAK
PA0 (HS)
PA1 (HS)/ATIC
PA2 (HS)/ATPWM0
I/O
I/O
I/O C
I/O C
I/O C
I/O C
I/O C
I/O C
I/O C
I/O C
I/O
I/O C
T
I/O C
T
I/O C
T
I/O C
T
I/O C
I/O C
I/O
I/O
C
C
C
C
C
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
HS
HS
HS x x x x x x x x x x x x x x x x x x x x ei1 ei2 ei2 ei0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
Port B0
Port B1
Port B2
Port B3
Port B4
Port B5
Port B6
Port B7
Port C0
Port C1
Port C2
AIN0
AIN1/
External clock source
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
ICCDATA
Port C3
Port C4
Port C5
ICCCLK
LTIC
Port C7
Port C6
BREAK
Port A0 (HS)
Port A1
(HS)
Port A2
(HS)
ATIC
ATPWM0
1.
In the open-drain output column, T defines a true open-drain I/O (P-Buffer and protection diode to V implemented).
DD
are not
2.
It is mandatory to connect all available V
DD
and V
DDA
pins to the supply voltage and all V
SS
and V
SSA
pins to ground.
16/188 Doc ID 13562 Rev 3
ST7LITE49M
3 Register and memory mapping
Register and memory mapping
As shown in
Figure 4 , the MCU is capable of addressing 64 Kbytes of memories and I/O
registers.
The available memory locations consist of 128 bytes of register locations, 384 bytes of
RAM, 128 bytes of data EEPROM and 4 Kbytes of Flash program memory. The RAM space includes up to 128 bytes for the stack from 180h to 1FFh.
The highest address bytes contain the user reset and interrupt vectors.
The Flash memory contains two sectors (see
Figure 4 ) mapped in the upper part of the ST7
addressing space so the reset and interrupt vectors are located in Sector 0 (FFE0h-FFFFh).
The size of Flash Sector 0 and other device options are configurable by option bytes (refer to
Caution: Memory locations marked as “Reserved” must never be accessed. Accessing a reserved area can have unpredictable effects on the device.
Figure 4.
ST7LITE49M memory map
0000h
007Fh
0080h
HW registers
(
)
01FFh
0200h
RAM
(384 bytes)
0080h
00FFh
0100h
017Fh
0180h
01FFh
Short addressing
RAM (zero page)
RAM
128 bytes Stack
Reserved
0FFFh
1000h
Data EEPROM
(128 bytes)
107Fh
1080h
Reserved
EFFFh
F000h
Flash memory
(4K)
FFDFh
FFE0h
FFFFh
Interrupt & reset vectors
(see
)
4K Flash program memory
3 Kbytes
(SECTOR 1)
1 Kbytes
(SECTOR 0)
DEE0h
DEE1h
DEE2h
DEE3h
F000h
FFFFh
RCCRH0
RCCRL0
RCCRH1
RCCRL1 see
Doc ID 13562 Rev 3 17/188
Register and memory mapping ST7LITE49M
Table 3.
Address
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh to
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h to
000Bh
Hardware register map
(1)
Block Register label
Port A
Port B
Port C
PADR
PADDR
PAOR
PBDR
PBDDR
PBOR
PCDR
PCDDR
PCOR
LITE
TIMER
AUTO-
RELOAD
TIMER
ITC
ISPR0
ISPR1
ISPR2
ISPR3
EICR
LTCSR2
LTARR
LTCNTR
LTCSR1
LTICR
ATCSR
CNTR1H
CNTR1L
ATR1H
ATR1L
PWMCR
PWM0CSR
PWM1CSR
PWM2CSR
PWM3CSR
DCR0H
DCR0L
DCR1H
DCR1L
DCR2H
DCR2L
DCR3H
DCR3L
ATICRH
ATICRL
ATCSR2
BREAKCR
ATR2H
ATR2L
DTGR
BREAKEN
Register name
Port A data register
Port A Data direction register
Port A option register
Port B data register
Port B data direction register
Port B option register
Port C data register
Port C data direction register
Port C option register
Reserved area (3 bytes)
Lite timer control/status register 2
Lite timer auto-reload register
Lite timer counter register
Lite timer control/status register 1
Lite timer input capture register
Timer control/status register
Counter register 1 High
Counter register 1 Low
Auto-reload register 1 High
Auto-reload register 1 Low
PWM output control register
PWM 0 control/status register
PWM 1 control/status register
PWM 2 control/status register
PWM 3 control/status register
PWM 0 duty cycle register High
PWM 0 duty cycle register Low
PWM 1 duty cycle register High
PWM 1 duty cycle register Low
PWM 2 duty cycle register High
PWM 2 duty cycle register Low
PWM 3 duty cycle register High
PWM 3 duty cycle register Low
Input capture register High
Input capture register Low
Timer control/status register 2
Break control register
Auto-reload register 2 High
Auto-reload register 2 Low
Dead time generation register
Break enable register
Reserved area (2 bytes)
Interrupt software priority register 0
Interrupt software priority register 1
Interrupt software priority register 2
Interrupt software priority register 3
External interrupt control register
Reset status Remarks
00h
00h
00h
00h
00h
00h
00h
00h
08h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FFh
FFh
FFh
FFh
00h
R/W
R/W
R/W
R/W
R/W
0Fh
00h
00h
0x00 0000b xxh
0x00 0000b
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
03h
00h
00h
00h
00h
03h
R/W
R/W
Read Only
R/W
Read Only
R/W
Read Only
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
18/188 Doc ID 13562 Rev 3
ST7LITE49M Register and memory mapping
Table 3.
Address
Hardware register map
(1)
(continued)
Block Register label Register name
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
WDG
FLASH
EEPROM
ADC
MCC
WDGCR
FCSR
EECSR
ADCCSR
ADCDRH
ADCDRL
MCCSR
RCCR
SICSR
Clock and reset
003Dh AVDTHCR
Reserved area (1 byte)
Watchdog control register
Flash control/status register
Data EEPROM control/status register
A/D control status register
A/D data register high
Reserved area (1 byte)
Main Clock Control/Status register
RC oscillator control register
System integrity control/status register
AVD threshold selection register / RC prescaler
003Eh to
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
AWU
DM
(2)
AWUCSR
AWUPR
DMCR
DMSR
DMBK1H
DMBK1L
DMBK2H
DMBK2L
DMCR2
Reserved area (10 bytes)
AWU control/status register
AWU Preload register
DM control register
DM status register
DM breakpoint register 1 High
DM breakpoint register 1 Low
DM breakpoint register 2 High
DM breakpoint register 2 Low
DM control register 2
0051h
Clock
Controller
CKCNTCSR Clock controller status register
0052h to
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
I2C
I2CCR
I2CSR1
I2CSR2
I2CCCR
I2COAR1
I2COAR2
I2CDR
Reserved area (18 bytes)
I
2
C control register
I
2
C status register 1
I
2
C status register 2
I
2
C clock control register
I
2
C own address register 1
I
2
C own address register 2
I
2
C data register
1.
Legend: x=undefined, R/W=read/write.
2.
For a description of the debug module registers, see ICC protocol reference manual.
Reset status Remarks
7Fh
00h
00h
00h xxh
0xh
00h
FFh
011x 0x00b
00h
FFh
00h
00h
00h
00h
00h
00h
00h
00h
09h
00h
00h
00h
00h
00h
40h
00h
R/W
R/W
R/W
R/W
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read only
Read only
R/W
R/W
R/W
R/W
Doc ID 13562 Rev 3 19/188
Flash programmable memory
4 Flash programmable memory
ST7LITE49M
4.1 Introduction
The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel.
The XFlash devices can be programmed off-board (plugged in a programming tool) or onboard using in-circuit programming or in-application programming.
The array matrix organization allows each sector to be erased and reprogrammed without affecting other sectors.
●
●
●
●
●
ICP (in-circuit programming)
IAP (in-application programming)
ICt (in-circuit testing) for downloading and executing user application test patterns in
RAM
Sector 0 size configurable by option byte
Read-out and write protection
The ST7 can be programmed in three different ways:
● Insertion in a programming tool. In this mode, Flash sectors 0 and 1, option byte row and data EEPROM (if present) can be programmed or erased.
● In-circuit programming. In this mode, Flash sectors 0 and 1, option byte row and data
EEPROM (if present) can be programmed or erased without removing the device from the application board.
● In-application programming. In this mode, sector 1 and data EEPROM (if present) can be programmed or erased without removing the device from the application board and while the application is running.
20/188
ICP uses a protocol called ICC (in-circuit communication) which allows an ST7 plugged on a printed circuit board (PCB) to communicate with an external programming device connected via cable. ICP is performed in three steps:
●
●
Switch the ST7 to ICC mode (in-circuit communications). This is done by driving a specific signal sequence on the ICCCLK/DATA pins while the RESET pin is pulled low. When the
ST7 enters ICC mode, it fetches a specific reset vector which points to the ST7 System
Memory containing the ICC protocol routine. This routine enables the ST7 to receive bytes from the ICC interface.
Download ICP Driver code in RAM from the ICCDATA pin
Execute ICP Driver code in RAM to program the Flash memory
Doc ID 13562 Rev 3
ST7LITE49M Flash programmable memory
Depending on the ICP Driver code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading).
4.3.2 In-application programming (IAP)
This mode uses an IAP Driver program previously programmed in Sector 0 by the user (in
ICP mode).
This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored etc.)
IAP mode can be used to program any memory areas except Sector 0, which is Write/Erase protected to allow recovery in case errors occur during the programming operation.
●
●
●
●
●
●
ICP needs a minimum of 4 and up to 6 pins to be connected to the programming tool. These pins are:
RESET: device reset
V
SS
: device power supply ground
ICCCLK: ICC output serial clock pin
ICCDATA: ICC input serial data pin
OSC1: main clock input for external source
V
DD
: application board power supply (optional, see Note 3)
Note: 1 If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an
ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another device forces the signal. Refer to the Programming
Tool documentation for recommended resistor values.
2 During the ICP session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than
5 mA at high level (push pull output or pull-up resistor<1 k
Ω
.). A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical RC network with
R>1 k
Ω
or a reset management IC with open-drain output and pull-up resistor>1 k
Ω
, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session.
3 The use of pin 7 of the ICC connector depends on the Programming Tool architecture. This pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual.
4 In “enabled option byte” mode (38-pulse ICC mode), the internal RC oscillator is forced as a clock source, regardless of the selection in the option byte. In “disabled option byte” mode
(35-pulse ICC mode), pin 9 has to be connected to the PB1/CLKIN pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte.
Caution: During normal operation the ICCCLK pin must be internally or externally pulled- up (external pull-up of 10 k Ω mandatory in noisy environment) to avoid entering ICC mode unexpectedly
Doc ID 13562 Rev 3 21/188
Flash programmable memory ST7LITE49M during a reset. In the application, even if the pin is configured as output, any reset will put it back in input pull-up.
Figure 5.
Typical ICC interface
(See Note 3)
PROGRAMMING TOOL
ICC CONNECTOR
ICC Cable
ICC CONNECTOR
HE10 CONNECTOR TYPE
OPTIONAL
(See Note 4) 9 7 5
10 8 6
3
4
1
2
APPLICATION BOARD
APPLICATION
RESET SOURCE
See Note 2
APPLICATION
POWER SUPPLY
See Note 1 and Caution
See Note 1
APPLICATION
I/O
ST7
22/188 Doc ID 13562 Rev 3
ST7LITE49M Flash programmable memory
There are two different types of memory protection: Read-out protection and Write/Erase
Protection which can be applied individually.
Read-out protection, when selected provides a protection against program memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. Both program and data EEPROM memory are protected.
In Flash devices, this protection is removed by reprogramming the option. In this case, both program and data EEPROM memory are automatically erased and the device can be reprogrammed.
●
●
Read-Out Protection selection depends on the device type:
In Flash devices it is enabled and removed through the FMP_R bit in the option byte.
In ROM devices it is enabled by mask option specified in the option list.
Write/erase protection, when set, makes it impossible to both overwrite and erase program memory. It does not apply to EEPROM data. Its purpose is to provide advanced security to applications and prevent any change being made to the memory content. Write/erase protection is enabled through the FMP_W bit in the option byte.
Caution: Once set, write/erase protection can never be removed. A write-protected Flash device is no longer reprogrammable.
4.7
For details on Flash programming and ICC protocol, refer to the ST7 Flash programming reference manual and to the ST7 ICC protocol reference manual .
Description of Flash control/status register (FCSR)
This register controls the XFlash erasing and programming using ICP, IAP or other programming methods.
1st RASS Key: 0101 0110 (56h)
2nd RASS Key: 1010 1110 (AEh)
When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys are sent automatically.
Reset value: 000 0000 (00h)
7
0 0 0 OPT LAT
0
PGM 0
Read/write
0
Doc ID 13562 Rev 3 23/188
Data EEPROM ST7LITE49M
5.1 Introduction
The electrically erasable programmable read only memory can be used as a non volatile back-up for storing data. Using the EEPROM requires a basic access protocol described in this chapter.
●
●
●
●
●
●
Up to 32 bytes programmed in the same cycle
EEPROM mono-voltage (charge pump)
Chained erase and programming cycles
Internal control of the global programming cycle duration
Wait mode management
Read-out protection
Figure 6.
EEPROM block diagram
HIGH VOLTAGE
PUMP
EECSR
0 0 0 0 0 0 E2LAT E2PGM
ADDRESS
DECODER
4 ROW
DECODER
4
4
EEPROM
MEMORY MATRIX
(1 ROW = 32 x 8 BITS)
128
DATA
MULTIPLEXER
128
32 x 8 BITS
DATA LATCHES
ADDRESS BUS DATA BUS
24/188 Doc ID 13562 Rev 3
ST7LITE49M Data EEPROM
5.3.1
5.3.2
Note:
The data EEPROM memory read/write access modes are controlled by the E2LAT bit of the
EEPROM Control/Status register (EECSR). The flowchart in Figure 7
describes these different memory access modes.
Read operation (E2LAT=0)
The EEPROM can be read as a normal ROM location when the E2LAT bit of the EECSR register is cleared.
On this device, data EEPROM can also be used to execute machine code. Take care not to write to the data EEPROM while executing from it. This would result in an unexpected code being executed.
Write operation (E2LAT=1)
To access the write mode, the E2LAT bit has to be set by software (the E2PGM bit remains cleared). When a write access to the EEPROM area occurs, the value is latched inside the
32 data latches according to its address.
When PGM bit is set by the software, all the previous bytes written in the data latches (up to
32) are programmed in the EEPROM cells. The effective high address (row) is determined by the last EEPROM write sequence. To avoid wrong programming, the user must take care that all the bytes written between two programming sequences have the same high address: only the five Least Significant Bits of the address can change.
At the end of the programming cycle, the PGM and LAT bits are cleared simultaneously.
Care should be taken during the programming cycle. Writing to the same memory location will over-program the memory (logical AND between the two write access data result) because the data latches are only cleared at the end of the programming cycle and by the falling edge of the E2LAT bit. It is not possible to read the latched data (see
Figure 7.
Data EEPROM programming flowchart
READ MODE
E2LAT=0
E2PGM=0
WRITE MODE
E2LAT=1
E2PGM=0
READ BYTES
IN EEPROM AREA
WRITE UP TO 32 BYTES
IN EEPROM AREA
(with the same 11 MSB of the address)
START PROGRAMMING CYCLE
E2LAT=1
E2PGM=1 (set by software)
0
E2LAT
1
CLEARED BY HARDWARE
Doc ID 13562 Rev 3 25/188
Data EEPROM ST7LITE49M
Figure 8.
Data EEPROM write operation
ROW
DEFINITION
⇓ Row / byte ⇒
0
1
...
N
0 1 2 3 ...
30 31 Physical Address
00h...1Fh
20h...3Fh
Nx20h...Nx20h+1Fh
5.4
Read operation impossible Read operation possible
E2LAT bit
Byte 1 Byte 2 Byte 32
PHASE 1
Writing data latches
Programming cycle
PHASE 2
Waiting E2PGM and E2LAT to fall
Set by USER application
Cleared by hardware
E2PGM bit
1.
If a programming cycle is interrupted (by a reset action), the integrity of the data in memory is not guaranteed.
Power saving modes
The data EEPROM can enter Wait mode on execution of the WFI instruction of the microcontroller or when the microcontroller enters Active-halt mode.The data EEPROM will immediately enter this mode if there is no programming in progress, otherwise the data
EEPROM will finish the cycle and then enter Wait mode.
Refer to Wait mode.
5.5
26/188
The data EEPROM immediately enters Halt mode if the microcontroller executes the Halt instruction. Therefore the EEPROM will stop the function in progress, and data may be corrupted.
Access error handling
If a read access occurs while E2LAT=1, then the data bus will not be driven.
If a write access occurs while E2LAT=0, then the data on the bus will not be latched.
If a programming cycle is interrupted (by a RESET action), the integrity of the data in memory will not be guaranteed.
Doc ID 13562 Rev 3
ST7LITE49M
5.6
Note:
Data EEPROM
Data EEPROM read-out protection
The read-out protection is enabled through an option bit (see Section 14.1: Option bytes ).
When this option is selected, the programs and data stored in the EEPROM memory are protected against Read-out (including a re-write protection). In Flash devices, when this protection is removed by reprogramming the option byte, the entire Program memory and
EEPROM is first automatically erased.
Both program memory and data EEPROM are protected using the same option bit.
Figure 9.
Data EEPROM programming cycle
READ OPERATION NOT POSSIBLE
Internal
Programming voltage
WRITE OF
DATA LATCHES
ERASE CYCLE t
PROG
WRITE CYCLE
READ OPERATION POSSIBLE
LAT
PGM
5.7
Note:
EEPROM control/status register (EECSR)
Address: 0035h
Reset value: 0000 0000 (00h)
7
0 0 0 0
Read/write
0 0 E2LAT
0
E2PGM
Bits 7:2 = Reserved, forced by hardware to 0
0: Read mode
1: Write mode
Bit 1 = E2LAT Latch access transfer bit: this bit is set by software.
It is cleared by hardware at the end of the programming cycle. It can only be cleared by software if the E2PGM bit is cleared
Bit 0 = E2PGM Programming control and status bit
This bit is set by software to begin the programming cycle. At the end of the programming cycle, this bit is cleared by hardware.
0: Programming finished or not yet started
1: Programming cycle is in progress
If the E2PGM bit is cleared during the programming cycle, the memory data is not guaranteed.
Doc ID 13562 Rev 3 27/188
Central processing unit
6 Central processing unit
ST7LITE49M
6.1 Introduction
This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8bit data manipulation.
●
●
●
●
●
●
●
●
63 basic instructions
Fast 8-bit by 8-bit multiply
17 main addressing modes
Two 8-bit index registers
16-bit stack pointer
Low power modes
Maskable hardware interrupts
Non-maskable software interrupt
The six CPU registers shown in Figure 10
. They are not present in the memory mapping and are accessed by specific instructions.
Figure 10.
CPU registers
7 0
ACCUMULATOR
RESET VALUE = XXh
7 0
X INDEX REGISTER
RESET VALUE = XXh
7 0
Y INDEX REGISTER
15 PCH 8
RESET VALUE = XXh
7 PCL 0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
1
RESET VALUE = 1
1 1 H I N Z
1 1 X 1 X X X
0
C
15 8 7 0
CONDITION CODE REGISTER
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
28/188 Doc ID 13562 Rev 3
ST7LITE49M Central processing unit
6.3.2
The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data.
Index registers (X and Y)
In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the
Y register.)
The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack).
The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (program counter low which is the LSB) and PCH (program counter high which is the MSB).
The 8-bit condition code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions.
Reset value: 111x 1xxx
7
1 1 I1 N Z
0
C H
Read/write
I0
These bits can be individually tested and/or controlled by specific instructions.
Arithmetic management bits
Bit 4 = H Half carry bit
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.
Doc ID 13562 Rev 3 29/188
Central processing unit
Note:
ST7LITE49M
Bit 3 = I Interrupt mask bit
This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions.
Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptible because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine.
Bit 2 = N Negative bit
This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7 th
bit of the result.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative (that is, the most significant bit is a logic
1).
This bit is accessed by the JRMI and JRPL instructions.
Bit 1 = Z Zero bit
This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero.
0: The result of the last operation is different from zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test instructions.
Bit 0 = C Carry/borrow bit
This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.
Interrupt management bits
Bits 5,3 = I1, I0 Interrupt bits
The combination of the I1 and I0 bits gives the current interrupt software priority.
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers
(IxSPR). They can be also set/cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions. See
Section 10.6: Interrupts for more details.
30/188 Doc ID 13562 Rev 3
ST7LITE49M
6.3.5
Note:
Central processing unit
*
Table 4.
Interrupt software priority truth table
Interrupt software priority
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable)
I1
1
0
0
1
I0
0
1
0
1
Stack pointer (SP)
Reset value: 01FFh
15
0 0 0 0 0 0 0
8
1
7 0
1 SP6 SP5 SP4 SP3 SP2 SP1 SP0
Read/write
The stack pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see
).
Since the stack is 128 bytes deep, the 9 most significant bits are forced by hardware.
Following an MCU reset, or after a reset stack pointer instruction (RSP), the stack pointer contains its reset value (the SP6 to SP0 bits are set) which is the stack higher address.
The least significant byte of the stack pointer (called S) can be directly accessed by a LD instruction.
When the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in
.
● When an interrupt is received, the SP is decremented and the context is pushed on the stack.
● On return from interrupt, the SP is incremented and the context is popped from the stack.
A subroutine call occupies two locations and an interrupt five locations in the stack area.
Doc ID 13562 Rev 3 31/188
Central processing unit
Figure 11.
Stack manipulation example
CALL
Subroutine
Interrupt
Event
PUSH Y
@ 0180h
POP Y IRET
SP
SP
@ 01FFh
PCH
PCL
CC
A
X
PCH
PCL
PCH
PCL
Stack Higher Address = 01FFh
Stack Lower Address = 0180h
SP
Y
CC
A
X
PCH
PCL
PCH
PCL
SP
CC
A
X
PCH
PCL
PCH
PCL
SP
PCH
PCL
SP
ST7LITE49M
RET or RSP
32/188 Doc ID 13562 Rev 3
ST7LITE49M
7
Supply, reset and clock management
Supply, reset and clock management
●
●
The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. The main features are the following:
● Clock management
– 8 MHz internal RC oscillator (enabled by option byte)
– Auto-wakeup RC oscillator (enabled by option byte)
– 1 to 16 MHz or 32 kHz External crystal/ceramic resonator (selected by option byte)
– External clock input (enabled by option byte)
Reset sequence manager (RSM)
System integrity management (SI)
– Main supply low voltage detection (LVD) with reset generation (enabled by option byte)
– Auxiliary voltage detector (AVD) with interrupt capability for monitoring the main supply (enabled by option byte)
The device contains an internal RC oscillator with a specific accuracy for a given device, temperature and voltage range (4.5 V - 5.5 V). It must be calibrated to obtain the frequency required in the application. This is done by software writing a 10-bit calibration value in the
RCCR (RC control register) and in the bits 6:5 in the SICSR (SI control status register).
Whenever the microcontroller is reset, the RCCR returns to its default value (FFh), i.e. each time the device is reset, the calibration value must be loaded in the RCCR. Predefined calibration values are stored in EEPROM for 3 and 5 V V
DD supply voltages at 25 °C (see
Table 5.
Predefined RC oscillator calibration values
RCCR Conditions
ST7LITE49M
Address
RCCRH0
RCCRL0
RCCRH1
RCCRL1
V
DD
= 5V
T
A
= 25°C f
RC
= 8 MHz
V
DD
= 3.3 V
T
A
= 25°C f
RC
= 8 MHz
DEE0h
DEE1h
DEE2h
DEE3h
(1)
(CR[9:2])
1.
The DEE0h, DEE1h, DEE2h and DEE3h addresses are located in a reserved area in non-volatile memory.
They are read-only bytes for the application code. This area cannot be erased or programmed by any ICC operations.
For compatibility reasons with the SICSR register, CR[1:0] bits are stored in the 5th and 6th position of
DEE1 and DEE3 addresses.
Doc ID 13562 Rev 3 33/188
Supply, reset and clock management ST7LITE49M
In 38-pulse ICC mode, the internal RC oscillator is forced as a clock source, regardless of the selection in the option byte.
Section 13: Electrical characteristics on page 139 for more information on the frequency
and accuracy of the RC oscillator.
To improve clock stability and frequency accuracy, it is recommended to place a decoupling capacitor, typically 100 nF, between the V
DD
and V
SS pins and also between the V
DDA
and
V
SSA pins as close as possible to the ST7 device.
These bytes are systematically programmed by ST, including on FASTROM devices.
Caution: If the voltage or temperature conditions change in the application, the frequency may need to be recalibrated. Refer to application note AN1324 for information on how to calibrate the
RC frequency using an external reference signal.
The ST7LITE49M also contains an Auto-wakeup RC oscillator. This RC oscillator should be enabled to enter auto-wakeup from halt mode.
The auto-wakeup (AWU) RC oscillator can also be configured as the startup clock through
the CKSEL[1:0] option bits (see Section 14.1: Option bytes on page 173
).
This is recommended for applications where very low power consumption is required.
Switching from one startup clock to another can be done in run mode as follows (see
):
Case 1 Switching from internal RC to AWU
1.
Set the RC/AWU bit in the CKCNTCSR register to enable the AWU RC oscillator
2. The RC_FLAG is cleared and the clock output is at 1.
3. Wait 3 AWU RC cycles till the AWU_FLAG is set
4. The switch to the AWU clock is made at the positive edge of the AWU clock signal
5. Once the switch is made, the internal RC is stopped
Case 2 Switching from AWU RC to internal RC
1.
Reset the RC/AWU bit to enable the internal RC oscillator
2. Using a 4-bit counter, wait until 8 internal RC cycles have elapsed. The counter is running on internal RC clock.
3. Wait till the AWU_FLAG is cleared (1AWU RC cycle) and the RC_FLAG is set (2 RC cycles)
4. The switch to the internal RC clock is made at the positive edge of the internal RC clock signal
5. Once the switch is made, the AWU RC is stopped
Note: 1 When the internal RC is not selected, it is stopped so as to save power consumption.
2 When the internal RC is selected, the AWU RC is turned on by hardware when entering
Auto-wakeup from Halt mode.
3 When the external clock is selected, the AWU RC oscillator is always on.
34/188 Doc ID 13562 Rev 3
ST7LITE49M
Figure 12.
Clock switching
Supply, reset and clock management
Internal RC
Set RC/AWU
Poll AWU_FLAG until set
AWU RC
AWU RC
Reset RC/AWU
Poll RC_FLAG until set
Internal RC
Figure 13.
Clock management block diagram
CK2 CK1 CK0
CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2
RCCR
CLKIN
CLKIN
/OSC1
OSC2 f
CR1 CR0
RC
Tunable
Oscillator
8 MHz (f
RC
)
Prescaler
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
CLKSEL[1:0]
Option bits
CLKIN
CLKIN
RC OSC
/2
DIVIDER
CLKIN/2
AWU RC OSC
Clock controller f
CPU
OSC
1-16 MHz or 32kHz
OSC /2
DIVIDER
RC/AWU
12-BIT
AT TIMER 2
CLKIN/2
OSC/2
CKCNTCSR f
OSC
OSC
/32 DIVIDER
8-BIT
LITE TIMER 2 COUNTER f
OSC
/32
1
CLKSEL[1:0]
Option bits f
LTIMER
(1ms timebase @ 8 MHz f
OSC
) f
OSC 0 f
CPU
TO CPU AND
PERIPHERALS
MCO SMS MCCSR f
CPU
MCO
Doc ID 13562 Rev 3 35/188
Supply, reset and clock management ST7LITE49M
●
●
●
The main clock of the ST7 can be generated by four different source types coming from the multi-oscillator block (1 to 16 MHz):
An external source
5 different configurations for crystal or ceramic resonator oscillators
An internal high frequency RC oscillator
Each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. The associated hardware configurations are shown in
Table 6 . Refer to the electrical characteristics section for more details.
Note:
In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground.
When the Multi-Oscillator is not used OSCI1 and OSCI2 must be tied to ground, and PB1 is selected by default as the external clock.
7.2.2 Crystal/ceramic oscillators
In this mode, with a self-controlled gain feature, oscillator of any frequency from 1 to 16 MHz can be placed on OSC1 and OSC2 pins. This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. In this mode of the multioscillator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.
These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase.
In this mode, the tunable 1% RC oscillator is used as main clock source. The two oscillator pins have to be tied to ground.
The calibration is done through the RCCR[7:0] and SICSR[6:5] registers.
36/188 Doc ID 13562 Rev 3
ST7LITE49M
Table 6.
ST7 clock sources
Supply, reset and clock management
Hardware configuration
OSC1
ST7
OSC2
EXTERNAL
SOURCE
OSC1
ST7
OSC2
C
L1
LOAD
CAPACITORS
C
L2
OSC1
ST7
OSC2
7.3 Reset sequence manager (RSM)
7.3.1 Introduction
Note:
The reset sequence manager includes three RESET sources as shown in Figure 15 :
●
●
●
External RESET source pulse
Internal LVD RESET (low voltage detection)
Internal WATCHDOG RESET
A reset can also be triggered following the detection of an illegal opcode or prebyte code.
Refer to
for further details.
These sources act on the RESET pin and it is always kept low during the delay phase.
The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory mapping.
●
●
The basic RESET sequence consists of 3 phases as shown in
Active phase depending on the RESET source
256 CPU clock cycle delay (see Table 7 )
Doc ID 13562 Rev 3 37/188
Supply, reset and clock management ST7LITE49M
Caution: When the ST7 is unprogrammed or fully erased, the Flash is blank and the reset vector is not programmed. For this reason, it is recommended to keep the RESET pin in low state until programming mode is entered, in order to avoid unwanted behavior.
The 256 CPU clock cycle delay allows the oscillator to stabilize and ensures that recovery has taken place from the reset state. The shorter or longer clock cycle delay is automatically selected depending on the clock source chosen by option byte.
The reset vector fetch phase duration is 2 clock cycles.
Table 7.
CPU clock delay during reset sequence
Clock source
Internal RC 8 MHz oscillator
Internal RC 32 kHz oscillator
External clock (connected to CLKIN/PB1 pin)
External crystal/ceramic oscillator (connected to OSC1/OSC2 pins)
External crystal/ceramic 1-16 MHz oscillator
External crystal/ceramic 32 kHz oscillator
CPU clock cycle delay
4096
256
4096
4096
4096
256
Figure 14.
Reset sequence phases active phase
RESET
Internal reset
256 or 4096 clock cycles
Fetch vector
38/188 Doc ID 13562 Rev 3
ST7LITE49M
7.3.2
Supply, reset and clock management
Asynchronous external RESET pin
The RESET pin is both an input and an open-drain output with integrated R
ON
weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See Electrical Characteristics section for more details.
A RESET signal originating from an external source must have a duration of at least t h(RSTL)in
in order to be recognized (see Figure 16: Reset sequences ). This detection is
asynchronous and therefore the MCU can enter reset state even in Halt mode.
The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section.
Figure 15.
Reset block diagram
V
DD
R
ON
RESET Filter
PULSE
GENERATOR
INTERNAL
RESET
___
WATCHDOG RESET
___
ILLEGAL OPCODE RESET
1)
___
LVD RESET
7.3.3
7.3.4
1.
See
Section 12.2.1: Illegal opcode reset on page 136
for more details on illegal opcode reset conditions.
External power-on reset
If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until V
DD
is over the minimum level specified for the selected f
OSC
frequency.
A proper reset signal for a slow rising V
DD
RC network connected to the RESET pin.
supply can generally be provided by an external
Internal low voltage detector (LVD) reset
Two different reset sequences caused by the internal LVD circuitry can be distinguished:
●
●
Power-on reset
Voltage drop reset
The device RESET pin acts as an output that is pulled low when V
DD is lower than V
IT+
(rising edge) or V
DD lower than V
IT-
(falling edge) as shown in Figure 16.
The LVD filters spikes on V
DD larger than t g(VDD) to avoid parasitic resets.
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Supply, reset and clock management ST7LITE49M
The reset sequence generated by an internal watchdog counter overflow is shown in
Starting from the watchdog counter underflow, the device RESET pin acts as an output that is pulled low during at least t w(RSTL)out
.
Figure 16.
Reset sequences
V
DD
V
IT+(LVD)
V
IT-(LVD)
RUN
LVD
RESET
ACTIVE PHASE
RUN
EXTERNAL
RESET
ACTIVE
PHASE
RUN
WATCHDOG
RESET
ACTIVE
PHASE
RUN t h(RSTL)in t w(RSTL)out
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
WATCHDOG UNDERFLOW
INTERNAL RESET (256 or 4096 T
CPU
VECTOR FETCH
)
40/188 Doc ID 13562 Rev 3
ST7LITE49M Supply, reset and clock management
7.4
Note:
System integrity management (SI)
The system integrity management block contains the low voltage detector (LVD) and auxiliary voltage detector (AVD) functions. It is managed by the SICSR register.
A reset can also be triggered following the detection of an illegal opcode or prebyte code.
Refer to
for further details.
7.4.1 Low voltage detector (LVD)
The low voltage detector function (LVD) generates a static reset when the V
DD
supply voltage is below a V
IT-(LVD)
reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset.
The V
IT-(LVD)
reference value for a voltage drop is lower than the V
IT+(LVD)
reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis).
The LVD reset circuitry generates a reset when V
DD
is below:
● V
IT+(LVD) when V
DD
is rising
● V
IT-(LVD)
when V
DD
is falling
The LVD function is illustrated in Figure 17 .
The voltage threshold can be configured by option byte to be low, medium or high. See
●
●
Provided the minimum V
DD
value (guaranteed for the oscillator frequency) is above V
IT-(LVD)
, the MCU can only be in two modes:
Under full software control
In static safe reset
In these conditions, secure operation is always ensured for the application without the need for external reset hardware.
Note:
During a low voltage detector reset, the RESET pin is held low, thus permitting the MCU to reset other devices.
Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the application, it is recommended to pull V
DD
down to 0 V to ensure optimum restart
conditions. Refer to circuit example in Figure 96 on page 169 and note 4.
The LVD is an optional function which can be selected by option byte. See Section 14.1 on page 173
.
It allows the device to be used without any external RESET circuitry.
If the LVD is disabled, an external circuitry must be used to ensure a proper power-on reset.
It is recommended to make sure that the V
DD supply voltage rises monotonously when the device is exiting from reset, to ensure the application functions properly.
Make sure that the right combination of LVD and AVD thresholds is used as LVD and AVD
levels are not correlated. Refer to section Section 13.3.2 on page 142
and Section 13.3.3 on page 143
for more details.
Caution: If an LVD reset occurs after a watchdog reset has occurred, the LVD will take priority and will clear the watchdog flag.
Doc ID 13562 Rev 3 41/188
Supply, reset and clock management
Figure 17.
Low voltage detector vs reset
V
DD
V hys
V
IT+(LVD)
V
IT-(LVD)
ST7LITE49M
RESET
Figure 18.
Reset and supply management block diagram
WATCHDOG
TIMER (WDG)
STATUS FLAG
RESET
RESET SEQUENCE
MANAGER
(RSM)
SYSTEM INTEGRITY MANAGEMENT
AVD Interrupt Request
SICSR
0 CR1 CR0 WDGF 0 LVDRF AVDF AVDIE
V
SS
V
DD
LOW VOLTAGE
DETECTOR
(LVD)
AUXILIARY VOLTAGE
DETECTOR
(AVD)
7.4.2 Auxiliary voltage detector (AVD)
The voltage detector function (AVD) is based on an analog comparison between a V
IT-(AVD) and V
IT+(AVD)
reference value and the V
DD
main supply voltage (V
AVD
). The V
IT-(AVD) reference value for falling voltage is lower than the V
IT+(AVD)
reference value for rising voltage in order to avoid parasitic detection (hysteresis).
The output of the AVD comparator is directly readable by the application software through a real-time status bit (AVDF) in the SICSR register. This bit is read only.
Monitoring the V
DD
main supply
The AVD threshold is selected by the AVD[1:0] bits in the AVDTHCR register.
If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the
V
IT+(AVD)
or V
IT-(AVD)
threshold (AVDF bit is set).
In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing
software to shut down safely before the LVD resets the microcontroller. See Figure 19
.
The interrupt on the rising edge is used to inform the application that the V
DD
warning state is over.
42/188 Doc ID 13562 Rev 3
ST7LITE49M
Note:
Supply, reset and clock management
Make sure that the right combination of LVD and AVD thresholds is used as LVD and AVD
levels are not correlated. Refer to Section 13.3.2 on page 142
Figure 19.
Using the AVD to monitor V
DD
V
DD
Early Warning Interrupt
(Power has dropped, MCU not not yet in reset)
V hyst
V
IT+(AVD)
V
IT-(AVD)
V
IT+(LVD)
V
IT-(LVD)
AVDF bit
AVD INTERRUPT
REQUEST
IF AVDIE bit = 1
0
LVD RESET
1 RESET
INTERRUPT Cleared by reset
1 0
INTERRUPT Cleared by hardware
7.4.3 Low power modes
Table 8.
Low power modes
Mode Description
Wait
Halt
No effect on SI. AVD interrupts cause the device to exit from Wait mode.
The SICSR register is frozen.
The AVD remains active but the AVD interrupt cannot be used to exit from Halt mode.
Interrupts
The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit
(AVDIE) is set and the interrupt mask in the CC register is reset (RIM instruction).
Table 9.
Description of interrupt events
Interrupt event
AVD event
Event flag
AVDF
Enable
Control bit
AVDIE
Exit from
Wait
Yes
Exit from
Halt
No
Doc ID 13562 Rev 3 43/188
Supply, reset and clock management ST7LITE49M
7.5.2
Note:
Reset value: 0000 0000 (00h)
7
0 0 0 0
Read/write
0 0 MCO
0
SMS
Bits 7:2 = Reserved, must be kept cleared.
Bit 1 = MCO Main clock out enable bit
This bit is read/write by software and cleared by hardware after a reset. This bit allows to enable the MCO output clock.
0: MCO clock disabled, I/O port free for general purpose I/O.
1: MCO clock enabled.
Bit 0 = SMS Slow mode selection bit
This bit is read/write by software and cleared by hardware after a reset. This bit selects the input clock f
OSC
or f
OSC
/32.
0: Normal mode (f
CPU = f
OSC
1: Slow mode (f
CPU = f
OSC
/32)
RC control register (RCCR)
Reset value: 1111 1111 (FFh)
7
CR9 CR8 CR7 CR6 CR5
Read/write
CR4 CR3
0
CR2
Bits 7:0 = CR[9:2] RC oscillator frequency adjustment bits
These bits must be written immediately after reset to adjust the RC oscillator frequency and to obtain an accuracy of 1%. The application can store the correct value for each voltage range in Flash memory and write it to this register at start-up.
00h = maximum available frequency
FFh = lowest available frequency
These bits are used with the CR[1:0] bits in the SICSR register. Refer to
To tune the oscillator, write a series of different values in the register until the correct frequency is reached. The fastest method is to use a dichotomy starting with 80h.
44/188 Doc ID 13562 Rev 3
ST7LITE49M
7.5.3
Supply, reset and clock management
System integrity (SI) control/status register (SICSR)
Reset value: 011x 0x00 (xxh)
7
0 CR1 CR0 LVDRF WDGRF 0
Read/write
AVDF
0
AVDIE
Bit 7 = Reserved, must be kept cleared
Bits 6:5 = CR[1:0] RC oscillator frequency adjustment bits
These bits, as well as CR[9:2] bits in the RCCR register must be written immediately after reset to adjust the RC oscillator frequency and to obtain an accuracy of 1%. Refer to
Section 7.1.1: Internal RC oscillator on page 33
.
Bit 4 = WDGRF Watchdog reset flag
This bit indicates that the last reset was generated by the watchdog peripheral. It is set by hardware (watchdog reset) and cleared by software (writing zero) or an LVD reset (to ensure a stable cleared state of the WDGRF flag when CPU starts). The WDGRF and the LVDRF
flags areis used to select the reset source (see Table 10: Reset source selection on page 45
).
Table 10.
Reset source selection
RESET source
External RESET pin
Watchdog
LVD
LVDRF
0
0
1
WDGRF
0
1
X
Bit 3 = Reserved, must be kept cleared
Bit 2 = LVDRF LVD reset flag
This bit indicates that the last reset was generated by the LVD block. It is set by hardware (LVD reset) and cleared by software (by reading). When the LVD is disabled by option byte, the LVDRF bit value is undefined.
The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the LVDRF flag remains set to keep trace of the original failure.
In this case, a watchdog reset can be detected by software while an external reset can not.
Bit 1 = AVDF Voltage detector flag
This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt
request is generated when the AVDF bit is set. Refer to Figure 19
and to Section for additional details.
0: V
DD
over AVD threshold
1: V
DD
under AVD threshold
Doc ID 13562 Rev 3 45/188
Supply, reset and clock management ST7LITE49M
Bit 0 = AVDIE Voltage detector interrupt enable bit
This bit is set and cleared by software. It enables an interrupt to be generated when the
AVDF flag is set. The pending interrupt information is automatically cleared when software enters the AVD interrupt routine.
0: AVD interrupt disabled
1: AVD interrupt enabled
Reset value: 0000 0000 (00h)
7
CK2 CK1 CK0
0
AVD0 0 0
Read/write
0 AVD1
Bits 7:5 = CK[2:0] internal RC prescaler selection
These bits are set by software and cleared by hardware after a reset. These bits select
.
If the internal RC is used with a supply operating range below 3.3 V, a division ratio of at least 2 must be enabled in the RC prescaler.
Table 11.
Internal RC prescaler selection bits
CK2 CK1 CK0
0
1
0
0
0
1
1
0 others
1
0
1
0 f
OSC f
RC/2 f
RC/4 f
RC/8 f
RC/16 f
RC
Bits 4:2 = Reserved, must be cleared.
Bits 1:0 = AVD[1:0] AVD threshold selection. These bits are used to select the AVD threshold. They are set and cleared by software. They are set by hardware after a reset.
Table 12.
AVD threshold selection bits
AVD1 AVD0
1
1
0
0
0
1
0
1
Functionality
Low
Medium
High
AVD off
46/188 Doc ID 13562 Rev 3
ST7LITE49M Supply, reset and clock management
Reset value: 0000 1001 (09h)
7
0 0 0 0 AWU_FLAG
Read/write
RC_FLAG
Bits 7:4 = Reserved, must be kept cleared.
Bit 3 = AWU_FLAG AWU selection bit
This bit is set and cleared by hardware.
0: No switch from AWU to RC requested
1: AWU clock activated and temporization completed
Bit 2 = RC_FLAG RC selection bit
This bit is set and cleared by hardware.
0: No switch from RC to AWU requested
1: RC clock activated and temporization completed
Bit 1 = Reserved, must be kept cleared.
Bit 0 = RC/AWU RC/AWU selection bit
0: RC enabled
1: AWU enabled (default value)
0
0
RC/AWU
Table 13.
Clock register mapping and reset values
Address
(Hex.)
Register label
7 6 5 4
003Ah
003Bh
003Ch
003Dh
MCCSR
Reset value
RCCR
Reset value
SICSR
Reset value
AVDTHCR
Reset value
-
0
CR9
1
-
0
CK2
0
-
0
CR8
1
CR1
1
CK1
0
-
0
CR7
1
CR0
1
CK0
0
-
0
CR6
1
WDGRF
0
-
0
0051h
CKCNTCSR
Reset value
-
0
-
0
-
0
-
0
3 2
-
0
CR5
1
-
0
-
0
AWU_
FLAG
1
-
0
CR4
1
LVDRF x
-
0
RC_FLA
G
0
1
MCO
0
CR3
1
AVDF x
AVD1
0
-
0
0
SMS
0
CR2
1
AVDIE x
AVD0
0
RC/AWU
1
Doc ID 13562 Rev 3 47/188
Interrupts
8 Interrupts
ST7LITE49M
8.1 Introduction
The ST7 enhanced interrupt management provides the following features:
●
●
●
Hardware interrupts
Software interrupt (TRAP)
Nested or concurrent interrupt management with flexible interrupt priority and level management:
– Up to 4 software programmable nesting levels
– 13 interrupt vectors fixed by hardware
– 2 non maskable events: RESET, TRAP
This interrupt management is based on:
●
●
●
Bit 5 and bit 3 of the CPU CC register (I1:0),
Interrupt software priority registers (ISPRx),
Fixed interrupt vector addresses located at the high addresses of the memory mapping
(FFE0h to FFFFh) sorted by hardware priority order.
This enhanced interrupt controller guarantees full upward compatibility with the standard
(not nested) ST7 interrupt controller.
8.2
Note:
Masking and processing flow
The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx registers which give the interrupt software priority level of each interrupt vector (see
). The processing flow is shown in
.
When an interrupt request has to be serviced:
●
●
●
Normal processing is suspended at the end of the current instruction execution.
The PC, X, A and CC registers are saved onto the stack.
●
I1 and I0 bits of CC register are set according to the corresponding values in the ISPRx registers of the serviced interrupt vector.
The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to interrupt mapping table for vector addresses).
The interrupt service routine should end with the IRET instruction which causes the contents of the saved registers to be recovered from the stack.
As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack and the program in the previous level will resume.
48/188 Doc ID 13562 Rev 3
ST7LITE49M Interrupts
Table 14.
Interrupt software priority levels
Interrupt software priority
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable)
Figure 20.
Interrupt processing flowchart
RESET
Level
Low
High
0
1
I1
1
PENDING
INTERRUPT
N
FETCH NEXT
INSTRUCTION
Y
Interrupt has the same or a lower software priority than current one
TLI
I1:0
N
Y
THE INTERRUPT
STAYS PENDING
I0
0
1
0
1
RESTORE PC, X, A, CC
FROM STACK
Y
“IRET”
N
EXECUTE
INSTRUCTION STACK PC, X, A, CC
LOAD I1:0 FROM INTERRUPT SW REG.
LOAD PC FROM INTERRUPT VECTOR
Doc ID 13562 Rev 3 49/188
Interrupts
8.2.1
ST7LITE49M
Servicing pending interrupts
●
●
As several interrupts can be pending at the same time, the interrupt to be taken into account is determined by the following two-step process:
The highest software priority interrupt is serviced,
If several interrupts have the same software priority then the interrupt with the highest hardware priority is serviced first.
describes this decision process.
Figure 21.
Priority decision process
PENDING
INTERRUPTS
Same SOFTWARE
PRIORITY
Different
HIGHEST SOFTWARE
PRIORITY SERVICED
HIGHEST HARDWARE
PRIORITY SERVICED
When an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one.
Note: 1 The hardware priority is exclusive while the software one is not. This allows the previous process to succeed with only one interrupt.
2 RESET and TRAP can be considered as having the highest software priority in the decision process.
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Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable type (RESET, TRAP) and the maskable type (external or from internal peripherals).
Non-maskable sources
These sources are processed regardless of the state of the I1 and I0 bits of the CC register
(see Figure 20 ). After stacking the PC, X, A and CC registers (except for RESET), the
corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to disable interrupts (level 3). These sources allow the processor to exit Halt mode.
● TRAP (non maskable software interrupt)
This software interrupt is serviced when the TRAP instruction is executed. It will be
serviced according to the flowchart in Figure 20 .
● RESET
The RESET source has the highest priority in the ST7. This means that the first current routine has the highest software priority (level 3) and the highest hardware priority.
See the RESET chapter for more details.
Doc ID 13562 Rev 3
ST7LITE49M
Note:
Interrupts
Maskable sources
Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in ISPRx registers) is higher than the one currently being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt is latched and thus remains pending.
● External interrupts
External interrupts allow the processor to exit from Halt low power mode.
External interrupt sensitivity is software selectable through the external interrupt control register (EICR).
External interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine.
If several input pins of a group connected to the same interrupt line are selected simultaneously, these will be logically ORed.
● Peripheral interrupts
Usually the peripheral interrupts cause the MCU to exit from Halt mode except those mentioned in
Table 18: ST7LITE49M interrupt mapping .
A peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register.
The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register.
The clearing sequence resets the internal latch. A pending interrupt (that is, waiting for being serviced) will therefore be lost if the clear sequence is executed.
8.3
Note:
Interrupts and low power modes
All interrupts allow the processor to exit the Wait low power mode. On the contrary, only external and other specified interrupts allow the processor to exit from the Halt modes (see column “Exit from Halt” in
Table 18: ST7LITE49M interrupt mapping
). When several pending interrupts are present while exiting Halt mode, the first one serviced can only be an interrupt with exit from Halt mode capability and it is selected through the same decision process
.
If an interrupt, that is not able to Exit from Halt mode, is pending with the highest priority when exiting Halt mode, this interrupt is serviced after the first one serviced.
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Interrupts ST7LITE49M
8.4 Concurrent and nested management
The following Figure 22 and Figure 23 show two different interrupt management modes. The
first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in
Figure 23 . The interrupt hardware priority is given in this order from the
lowest to the highest: MAIN, IT5, IT4, IT3, IT2, IT1, IT0. The software priority is given for each interrupt.
Caution: A stack overflow may occur without notifying the software of the failure.
Figure 22.
Concurrent interrupt management
RIM
MAIN
11 / 10
IT3
IT2
IT0
IT2
IT1
IT4
IT5
SOFTWARE
PRIORITY
LEVEL
I1
3
3
3
3
3
3
3/0
1 1
1 1
1 1
1 1
1 1
1 1
10
MAIN
I0
Figure 23.
Nested interrupt management
RIM
MAIN
11 / 10
IT2
IT1
IT4
TLI
IT4
IT0
IT3
IT1
IT2
SOFTWARE
PRIORITY
LEVEL
I1
3
3
2
1
3
3
3/0
1 1
1 1
0 0
0 1
1 1
1 1
10
MAIN
I0
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ST7LITE49M
8.5
8.5.1
Interrupts
Description of interrupt registers
CPU CC register interrupt bits
Reset value: 111x 1010(xAh)
7
1 1 I1 H
Read/write
I0 N Z
0
C
Bits 5, 3 = I1, I0 Software interrupt priority bits
These two bits indicate the current interrupt software priority (see Table 15
).
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers
(ISPRx).
They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and
PUSH/POP instructions (see Table 17: Dedicated interrupt instruction set
).
TRAP and RESET events can interrupt a level 3 program.
Table 15.
Setting the interrupt software priority
Interrupt software priority Level
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable*)
Low
High
I1
1
0
1
I0
0
1
0
1
All ISPRx register bits are read/write except bit 7:4 of ISPR3 which are read only.
Reset value: 1111 1111 (FFh)
ISPR0
ISPR1
ISPR2
ISPR3
7
I1_3
I1_7
I1_11
1
I0_3
I0_7
I0_11
1
I1_2
I1_6
I1_10
1
I0_2
I0_6
I0_10
1
I1_1
I1_5
I1_9
1
I0_1
I0_5
I0_9
1
I1_0
I1_4
I1_8
I1_12
0
I0_0
I0_4
I0_8
I0_12
ISPRx registers contain the interrupt software priority of each interrupt vector. Each interrupt vector (except RESET and TRAP) has corresponding bits in these registers to define its
software priority. This correspondence is shown in Table 16
.
Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1 and I0 bits in the CC register.
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Interrupts ST7LITE49M
The RESET and TRAP vectors have no software priorities. When one is serviced, the I1 and
I0 bits of the CC register are both set.
Level 0 cannot be written (I1_x = 1, I0_x = 0). In this case, the previously stored value is kept (Example: previous = CFh, write = 64h, result = 44h).
Table 16.
Interrupt vector vs. ISPRx bits
Vector address
FFFBh-FFFAh
FFF9h-FFF8h
...
FFE1h-FFE0h
ISPRx bits
I1_0 and I0_0 bits
(1)
I1_1 and I0_1 bits
...
I1_13 and I0_13 bits
1.
Bits in the ISPRx registers can be read and written but they are not significant in the interrupt process management.
Caution: If the I1_x and I0_x bits are modified while the interrupt x is executed the following behavior has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previous one, the interrupt x is re-entered.
Otherwise, the software priority stays unchanged up to the next interrupt request (after the
IRET of the interrupt x).
Table 17.
Dedicated interrupt instruction set
(1)
Instruction New description Function/example I1 H I0 N Z C
HALT
IRET
JRM
JRNM
POP CC
RIM
SIM
TRAP
WFI
Entering Halt mode
Interrupt routine return
Jump if I1:0 = 11 (level 3)
Jump if I1:0 <> 11
Pop CC from the stack
Pop CC, A, X, PC
I1:0 = 11
I1:0 <> 11
Mem => CC
1
I1 H
0
I0 N Z C
Enable interrupt (level 0 set) Load 10 in I1:0 of CC 1
Disable interrupt (level 3 set) Load 11 in I1:0 of CC 1
Software trap Software NMI 1
Wait for interrupt
I1 H I0 N Z C
1
0
1
1
0
1.
During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current software priority up to the next IRET instruction or one of the previously mentioned instructions.
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ST7LITE49M Interrupts
Table 18.
ST7LITE49M interrupt mapping
Number
Source block
Description
Register label
Priority order
Exit from
HALT or
AWUFH
(1)
Address vector
4
5
6
7
(3)
8
9
10
(3)
11
12
2
3
0
1
RESET
TRAP
AWU
AVD
AT TIMER
I ei0 ei1 ei2
2
C
LITE TIMER
Reset
Software interrupt
Auto-wakeup interrupt
Auxiliary voltage detector interrupt
External interrupt 0 (Port A)
External interrupt 1 (Port B)
External interrupt 2 (Port C)
AT timer output compare interrupt
AT timer input capture interrupt
AT timer overflow 1 interrupt
AT timer Overflow 2 interrupt
I
2
C interrupt
Lite timer RTC interrupt
Lite timer Input Capture interrupt
Lite timer RTC2 interrupt
N/A
AWUCSR
N/A
N/A
ATCSR
N/A
LTCSR2
Highest
Priority
Lowest
Priority yes no yes no no no no no no yes no no
(2) yes
1.
For an interrupt, all events do not have the same capability to wake up the MCU from Halt, Active-halt or Auto-wakeup from
Halt modes. Refer to the description of interrupt events for more details.
2.
This interrupt exits the MCU from Auto Wake-up from Halt mode only.
3.
These interrupts exit the MCU from Active-halt mode only.
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
FFF8h-FFF9h
FFF6h-FFF7
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
FFECh-FFEDh
FFEAh-FFEBh
FFE8h-FFE9h
FFE6h-FFE7h
FFE4h-FFE5h
FFE2h-FFE3h
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Interrupts ST7LITE49M
Reset value: 0000 0000 (00h)
7
0 0 IS21
0
IS00 IS20 IS11
Read/write
IS10 IS01
Bits 7:6 = Reserved, must be kept cleared.
Bits 5:4 = IS2[1:0] ei2 sensitivity bits
These bits define the interrupt sensitivity for ei2 (Port C) according to Table 19 .
Bits 3:2 = IS1[1:0] ei1 sensitivity bits
These bits define the interrupt sensitivity for ei1 (Port B) according to
Bits 1:0 = IS0[1:0] ei0 sensitivity bits
These bits define the interrupt sensitivity for ei0 (Port A) according to
Note: 1 These 8 bits can be written only when the I bit in the CC register is set.
2 Changing the sensitivity of a particular external interrupt clears this pending interrupt. This can be used to clear unwanted pending interrupts. Refer to Section : External interrupt function .
Table 19.
Interrupt sensitivity bits
ISx1 ISx0
1
1
0
0
0
1
0
1
External interrupt sensitivity
Falling edge & low level
Rising edge only
Falling edge only
Rising and falling edge
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ST7LITE49M Power saving modes
9.1 Introduction
●
●
●
●
●
To give a large measure of flexibility to the application in terms of power consumption, four
main power saving modes are implemented in the ST7 (see Figure 24 ):
Slow
Wait (and Slow-wait)
Active-halt
Auto-wakeup from Halt (AWUFH)
Halt
After a reset the normal operating mode is selected by default (Run mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency (f
OSC
).
From Run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status.
Figure 24.
Power saving mode transitions
High
Run
Slow
Wait
Slow Wait
Active Halt
Halt
Low
POWER CONSUMPTION
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Power saving modes ST7LITE49M
Note:
This mode has two targets:
●
●
To reduce power consumption by decreasing the internal clock in the device,
To adapt the internal clock frequency (f
CPU
) to the available supply voltage.
Slow mode is controlled by the SMS bit in the MCCSR register which enables or disables
Slow mode.
In this mode, the oscillator frequency is divided by 32. The CPU and peripherals are clocked at this lower frequency.
Slow-wait mode is activated when entering Wait mode while the device is already in Slow mode.
Figure 25.
Slow mode clock transition f
OSC
/32 f
OSC f
CPU f
OSC
SMS
NORMAL RUN MODE
REQUEST
Wait mode places the MCU in a low power consumption mode by stopping the CPU.
This power saving mode is selected by calling the ‘WFI’ instruction.
All peripherals remain active. During Wait mode, the I bit of the CC register is cleared, to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in Wait mode until an interrupt or reset occurs, whereupon the program counter branches to the starting address of the interrupt or reset service routine.
The MCU will remain in Wait mode until a reset or an interrupt occurs, causing it to wake up.
Refer to
for a description of the Wait mode flowchart.
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ST7LITE49M
Figure 26.
Wait mode flowchart
WFI INSTRUCTION
OSCILLATOR
PERIPHERALS
CPU
I BIT
ON
ON
OFF
0
Power saving modes
N
N
RESET
Y
INTERRUPT
Y
OSCILLATOR
PERIPHERALS
CPU
I BIT
ON
OFF
ON
0
256 CPU CLOCK CYCLE
DELAY
OSCILLATOR
PERIPHERALS
CPU
I BIT
ON
ON
ON
X
1)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
1.
Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.
9.4 Active-halt and Halt modes
Active-halt and Halt modes are the two lowest power consumption modes of the MCU. They are both entered by executing the ‘HALT’ instruction. The decision to enter either in Activehalt or Halt mode is given by the LTCSR/ATCSR register status as shown in the following table:
Table 20.
Enabling/disabling Active-halt and Halt modes
LTCSR TBIE bit
ATCSR OVFIE bit
ATCSRCK1 bit ATCSRCK0 bit
0
0
0
1 x x
0
1 x
1 x x
1 x
0
0 x
1 x
1
Meaning
Active-halt mode disabled
Active-halt mode enabled
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Power saving modes ST7LITE49M
Active-halt mode is the lowest power consumption mode of the MCU with a real-time clock available. It is entered by executing the ‘HALT’ instruction when Active-halt mode is enabled.
The MCU can exit Active-halt mode on reception of a Lite timer/ AT timer interrupt or a reset.
● When exiting Active-halt mode by means of a reset, a 256 CPU cycle delay occurs.
After the start up delay, the CPU resumes operation by fetching the reset vector which
● When exiting Active-halt mode by means of an interrupt, the CPU immediately resumes operation by servicing the interrupt vector which woke it up (see
).
When entering Active-halt mode, the I bit in the CC register is cleared to enable interrupts.
Therefore, if an interrupt is pending, the MCU wakes up immediately.
In Active-halt mode, only the main oscillator and the selected timer counter (LT/AT) are running to keep a wakeup time base. All other peripherals are not clocked except those which get their clock supply from another clock generator (such as external or auxiliary oscillator).
Caution: As soon as Active-halt is enabled, executing a HALT instruction while the watchdog is active does not generate a reset if the WDGHALT bit is reset.
This means that the device cannot spend more than a defined delay in this power saving mode.
Figure 27.
Active-halt timing overview
[Active-halt Enabled]
RUN
ACTIVE
HALT
HALT
INSTRUCTION
256 CPU
CYCLE DELAY
1)
RESET
OR
INTERRUPT
RUN
FETCH
VECTOR
1.
This delay occurs only if the MCU exits Active-halt mode by means of a RESET.
60/188 Doc ID 13562 Rev 3
ST7LITE49M
Figure 28.
Active-halt mode flowchart
HALT INSTRUCTION
(Active-halt enabled)
OSCILLATOR
PERIPHERALS 2)
CPU
I BIT
ON
OFF
OFF
0
Power saving modes
N
RESET
Y
N
INTERRUPT 3)
Y OSCILLATOR
PERIPHERALS 2)
CPU
I BIT
ON
OFF
ON
X
4)
256 CPU CLOCK CYCLE
DELAY
OSCILLATOR
PERIPHERALS
CPU
I BITS
ON
ON
ON
X
4)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
1.
This delay occurs only if the MCU exits Active-halt mode by means of a RESET.
2.
Peripherals clocked with an external clock source can still be active.
3.
Only the Lite timer RTC and AT timer interrupts can exit the MCU from Active-halt mode.
4.
Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.
The Halt mode is the lowest power consumption mode of the MCU. It is entered by executing the HALT instruction when Active-halt mode is disabled.
The MCU can exit Halt mode on reception of either a specific interrupt (see
) or a reset. When exiting Halt mode by means of a reset or an interrupt, the main oscillator is immediately turned on and the 256 CPU cycle delay is used to stabilize it. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see
).
When entering Halt mode, the I bit in the CC register is forced to 0 to enable interrupts.
Therefore, if an interrupt is pending, the MCU wakes immediately.
In Halt mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator).
The compatibility of watchdog operation with Halt mode is configured by the “WDGHALT” option bit of the option byte. The HALT instruction when executed while the watchdog
system is enabled, can generate a watchdog reset (see Section 14.1: Option bytes
for more details).
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Power saving modes
Figure 29.
Halt timing overview
ST7LITE49M
RUN HALT
HALT
INSTRUCTION
[ Active-halt disabled ]
256 CPU CYCLE
DELAY
RESET
OR
INTERRUPT
RUN
FETCH
VECTOR
1.
A reset pulse of at least 42 µs must be applied when exiting from Halt mode.
Figure 30.
Halt mode flowchart
HALT INSTRUCTION
(Active-halt disabled)
ENABLE
0
WDGHALT 1)
1
WATCHDOG
RESET
CPU
I BIT
WATCHDOG
OSCILLATOR
PERIPHERALS
DISABLE
2)
OFF
OFF
OFF
0
N
RESET
Y
N
INTERRUPT 3)
Y OSCILLATOR
PERIPHERALS
CPU
I BIT
ON
OFF
ON
X 4)
256 CPU CLOCK CYCLE
DELAY 5)
OSCILLATOR
PERIPHERALS
CPU
I BITS
ON
ON
ON
X 4)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
1.
WDGHALT is an option bit. See option byte section for more details.
2.
Peripheral clocked with an external clock source can still be active.
3.
Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to
Table 18: ST7LITE49M interrupt mapping for more details.
4.
Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.
5.
The CPU clock must be switched to 1 MHz (RC/8) or AWU RC before entering Halt mode.
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ST7LITE49M Power saving modes
Halt mode recommendations
●
●
●
●
●
Make sure that an external event is available to wake up the microcontroller from Halt mode.
When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition.
For the same reason, reinitialize the level sensitiveness of each external interrupt as a precautionary measure.
The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction due to a Program Counter failure, it is advised to clear all occurrences of the data value
0x8E from memory. For example, avoid defining a constant in ROM with the value
0x8E.
As the HALT instruction clears the I bit in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction.
This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wakeup event (reset or external interrupt).
9.5 Auto-wakeup from Halt mode
Auto-wakeup from Halt (AWUFH) mode is similar to Halt mode with the addition of a specific internal RC oscillator for wakeup (Auto-wakeup from Halt oscillator) which replaces the main clock which was active before entering Halt mode. Compared to Active-halt mode, AWUFH has lower power consumption (the main clock is not kept running), but there is no accurate real-time clock available.
It is entered by executing the HALT instruction when the AWUEN bit in the AWUCSR register has been set.
Figure 31.
AWUFH mode block diagram
AWU RC oscillator f
AWU_RC to 8-bit timer input capture
/64 divider
AWUFH interrupt
AWUFH prescaler/1 .. 255
(ei0 source)
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Power saving modes ST7LITE49M
●
●
●
As soon as Halt mode is entered, and if the AWUEN bit has been set in the AWUCSR register, the AWU RC oscillator provides a clock signal (f
AWU_RC
). Its frequency is divided by a fixed divider and a programmable prescaler controlled by the AWUPR register. The output of this prescaler provides the delay time. When the delay has elapsed, the following actions are performed: the AWUF flag is set by hardware, an interrupt wakes up the MCU from Halt mode, the main oscillator is immediately turned on and the 256 CPU cycle delay is used to stabilize it.
After this start-up delay, the CPU resumes operation by servicing the AWUFH interrupt. The
AWU flag and its associated interrupt are cleared by software reading the AWUCSR register.
To compensate for any frequency dispersion of the AWU RC oscillator, it can be calibrated by measuring the clock frequency f
AWU_RC and then calculating the right prescaler value.
Measurement mode is enabled by setting the AWUM bit in the AWUCSR register in Run mode. This connects f
AWU_RC
to the input capture of the 8-bit Lite timer, allowing the f
AWU_RC
to be measured using the main oscillator clock as a reference timebase.
Similarities with Halt mode
The following AWUFH mode behavior is the same as normal Halt mode:
● The MCU can exit AWUFH mode by means of any interrupt with exit from Halt
capability or a reset (see Section 9.4: Active-halt and Halt modes
).
● When entering AWUFH mode, the I bit in the CC register is forced to 0 to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
●
●
In AWUFH mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. None of the peripherals are clocked except those which get their clock supply from another clock generator (such as an external or auxiliary oscillator like the AWU oscillator).
The compatibility of watchdog operation with AWUFH mode is configured by the
WDGHALT option bit in the option byte. Depending on this setting, the HALT instruction when executed while the watchdog system is enabled, can generate a watchdog reset.
Figure 32.
AWUF Halt timing diagram t
AWU
HALT MODE 256 t
CPU
RUN MODE RUN MODE f
CPU f
AWU_RC
AWUFH interrupt
Clear by software
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ST7LITE49M
Figure 33.
AWUFH mode flowchart
HALT INSTRUCTION
(Active-Halt disabled)
(AWUCSR.AWUEN=1)
ENABLE
0
WDGHALT 1)
1
WATCHDOG
RESET
WATCHDOG
DISABLE
AWU RC OSC ON
MAIN OSC OFF
PERIPHERALS 2)
OFF
CPU
I[1:0] BITS
OFF
10
N
INTERRUPT 3)
Y
N
RESET
Y
AWU RC OSC OFF
MAIN OSC ON
PERIPHERALS
CPU
I[1:0] BITS
OFF
ON
XX 4)
256 CPU CLOCK
CYCLE DELAY
AWU RC OSC OFF
MAIN OSC
PERIPHERALS
CPU
I[1:0] BITS
ON
ON
ON
XX 4)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Power saving modes
1.
WDGHALT is an option bit. See option byte section for more details.
2.
Peripheral clocked with an external clock source can still be active.
3.
Only an AWUFH interrupt and some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to
Table 18: ST7LITE49M interrupt mapping
for more details.
4.
Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped.
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Power saving modes ST7LITE49M
9.5.2
Note:
AWUFH control/status register (AWUCSR)
Reset value: 0000 0000 (00h)
7 0
0 0 0 0 0
AWU
F
AWUM AWUEN
Read/Write
Bits 7:3 = Reserved
Bit 2 = AWUF Auto-wakeup flag
This bit is set by hardware when the AWU module generates an interrupt and cleared by software on reading AWUCSR. Writing to this bit does not change its value.
0: No AWU interrupt occurred
1: AWU interrupt occurred
Bit 1 = AWUM Auto-wakeup measurement bit
This bit enables the AWU RC oscillator and connects its output to the Input Capture of the 8-bit Lite timer. This allows the timer to be used to measure the AWU RC oscillator dispersion and then compensate this dispersion by providing the right value in the
AWUPRE register.
0: Measurement disabled
1: Measurement enabled
Bit 0 = AWUEN Auto-wakeup from Halt enabled bit
This bit enables the Auto-wakeup from halt feature: once Halt mode is entered, the
AWUFH wakes up the microcontroller after a time delay dependent on the AWU prescaler value. It is set and cleared by software.
0: AWUFH (Auto-wakeup from Halt) mode disabled
1: AWUFH (Auto-wakeup from Halt) mode enabled
Whatever the clock source, this bit should be set to enable the AWUFH mode once the
HALT instruction has been executed.
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9.5.3
Power saving modes
AWUFH prescaler register (AWUPR)
Reset value: 1111 1111 (FFh)
7 0
AWUPR7 AWUPR6 AWUPR5 AWUPR4 AWUPR3 AWUPR2 AWUPR1 AWUPR0
Read/Write
Bits 7:0= AWUPR[7:0] Auto-wakeup prescaler
These 8 bits define the AWUPR dividing factor (see Table 21 ).
Table 21.
Configuring the dividing factor
AWUPR[7:0 ] Dividing
00h
01h
...
FEh
FFh
Forbidden
1
...
254
255
In AWU mode, the time during which the MCU stays in Halt mode, t
AWU
, is given by the
equation below. See also Figure 32 on page 64
.
Note: t
AWU
= 64 × AWUPR × f
AWURC
+ t
RCSTRT
The AWUPR prescaler register can be programmed to modify the time during which the
MCU stays in Halt mode before waking up automatically.
If 00h is written to AWUPR, the AWUPR remains unchanged.
Table 22.
AWU register mapping and reset values
Address
(Hex.)
Register label
7 6 5 4
0048h
0049h
3 2 1 0
AWUCSR
Reset value
AWUPR
Reset value
0 0 0 0 0 AWUF AWUM AWUEN
AWUPR7
1
AWUPR6
1
AWUPR5
1
AWUPR4
1
AWUPR3
1
AWUPR2
1
AWUPR1
1
AWUPR0
1
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I/O ports ST7LITE49M
10.1 Introduction
The I/O ports allow data transfer. An I/O port can contain up to 8 pins. Each pin can be programmed independently either as a digital input or digital output. In addition, specific pins may have several other functions. These functions can include external interrupt, alternate signal input/output for on-chip peripherals or analog input.
A data register (DR) and a data direction register (DDR) are always associated with each port. The Option register (OR), which allows input/output options, may or may not be implemented. The following description takes into account the OR register. Refer to the port configuration table for device specific information.
An I/O pin is programmed using the corresponding bits in the DDR, DR and OR registers: bit x corresponding to pin x of the port.
shows the generic I/O block diagram.
Clearing the DDRx bit selects input mode. In this mode, reading its DR bit returns the digital value from that I/O pin.
If an OR bit is available, different input modes can be configured by software: floating or pullup. Refer to I/O Port Implementation section for configuration.
Note: 1 Writing to the DR modifies the latch value but does not change the state of the input pin.
2 Do not use read/modify/write instructions (BSET/BRES) to modify the DR register.
External interrupt function
Depending on the device, setting the ORx bit while in input mode can configure an I/O as an input with interrupt. In this configuration, a signal edge or level input on the I/O generates an interrupt request via the corresponding interrupt vector (eix).
Falling or rising edge sensitivity is programmed independently for each interrupt vector. The
External Interrupt Control register (EICR) or the Miscellaneous register controls this sensitivity, depending on the device.
Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description and interrupt section). If several I/O interrupt pins on the same interrupt vector are selected simultaneously, they are logically combined. For this reason if one of the interrupt pins is tied low, it may mask the others.
External interrupts are hardware interrupts. Fetching the corresponding interrupt vector automatically clears the request latch. Changing the sensitivity of a particular external interrupt clears this pending interrupt. This can be used to clear unwanted pending interrupts.
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Spurious interrupts
When enabling/disabling an external interrupt by setting/resetting the related OR register bit, a spurious interrupt is generated if the pin level is low and its edge sensitivity includes falling/rising edge. This is due to the edge detector input which is switched to '1' when the external interrupt is disabled by the OR register.
To avoid this unwanted interrupt, a "safe" edge sensitivity (rising edge for enabling and falling edge for disabling) has to be selected before changing the OR register bit and configuring the appropriate sensitivity again.
Caution: In case a pin level change occurs during these operations (asynchronous signal input), as interrupts are generated according to the current sensitivity, it is advised to disable all interrupts before and to reenable them after the complete previous sequence in order to avoid an external interrupt occurring on the unwanted edge.
This corresponds to the following steps: a) Set the interrupt mask with the SIM instruction (in cases where a pin level change could occur) c) Enable the external interrupt through the OR register d) Select the desired sensitivity if different from rising edge e) Reset the interrupt mask with the RIM instruction (in cases where a pin level change could occur)
2. To disable an external interrupt: a) Set the interrupt mask with the SIM instruction SIM (in cases where a pin level change could occur) c) Disable the external interrupt through the OR register e) Reset the interrupt mask with the RIM instruction (in cases where a pin level change could occur)
Setting the DDRx bit selects output mode. Writing to the DR bits applies a digital value to the
I/O through the latch. Reading the DR bits returns the previously stored value.
If an OR bit is available, different output modes can be selected by software: push-pull or open-drain. Refer to I/O Port Implementation section for configuration.
Table 23.
DR value and output pin status
DR Push-pull
0
1
V
OL
V
OH
Open-drain
V
OL
Floating
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I/O ports ST7LITE49M
Many ST7s I/Os have one or more alternate functions. These may include output signals from, or input signals to, on-chip peripherals.
Table 2 describes which peripheral signals can
be input/output to which ports.
A signal coming from an on-chip peripheral can be output on an I/O. To do this, enable the on-chip peripheral as an output (enable bit in the peripheral’s control register). The peripheral configures the I/O as an output and takes priority over standard I/O programming.
The I/O’s state is readable by addressing the corresponding I/O data register.
Configuring an I/O as floating enables alternate function input. It is not recommended to configure an I/O as pull-up as this will increase current consumption. Before using an I/O as an alternate input, configure it without interrupt. Otherwise spurious interrupts can occur.
Configure an I/O as input floating for an on-chip peripheral signal which can be input and output.
Caution: I/Os which can be configured as both an analog and digital alternate function need special attention. The user must control the peripherals so that the signals do not arrive at the same time on the same pin. If an external clock is used, only the clock alternate function should be employed on that I/O pin and not the other alternate function.
Figure 34.
I/O port general block diagram
REGISTER
ACCESS
ALTERNATE
OUTPUT
From on-chip periphera l
1
0
ALTERNATE
ENABLE
BIT
DR
V
DD
P-BUFFER
(see table below)
PULL-UP
(see table below)
V
DD
DDR
PULL-UP
CONDITION
OR
OR SEL
If implemented
N-BUFFER
DDR SEL
DR SEL
1
0
CMOS
SCHMITT
TRIGGER
EXTERNAL
INTERRUPT
REQUEST (ei x
)
Combinational
Logic
SENSITIVITY
SELECTION
FROM
OTHER
BITS
Note : Refer to the Port Configuration table for device specific information.
DIODES
PAD
(see table below)
ANALOG
INPUT
ALTERNATE
INPUT
To on-chip peripheral
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ST7LITE49M I/O ports
Table 24.
I/O port mode options
(1)
Configuration mode Pull-up P-buffer to V
DD
Diodes to V
SS
Input
Output
Floating with/without Interrupt
Pull-up with Interrupt
Push-pull
Open-drain (logic level)
Off
On
Off
Off
On
Off
1.
Off means implemented not activated, On means implemented and activated.
Table 25.
I/O port configuration
Hardware configuration
DR REGISTER ACCESS
On On
PAD
DR
REGISTER
W
R
DATA BUS
FROM
OTHER
PINS
INTERRUPT
CONDITION
ALTERNATE INPUT
To on-chip peripheral
COMBINATIONAL
LOGIC
POLARITY
SELECTION
EXTERNAL INTERRUPT
SOURCE (ei x
)
ANALOG INPUT
PAD
DR REGISTER ACCESS
DR
REGISTER
R/W
DATA BUS
DR REGISTER ACCESS
DR
REGISTER
R/W
DATA BUS
PAD
ALTERNATE
ENABLE
BIT
ALTERNATE
OUTPUT
From on-chip periphera l
1.
When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status.
2.
When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content.
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I/O ports ST7LITE49M
10.2.4 Analog alternate function
Configure the I/O as floating input to use an ADC input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail, connected to the ADC input.
Analog Recommendations
Do not change the voltage level or loading on any I/O while conversion is in progress. Do not have clocking pins located close to a selected analog pin.
Caution: The analog input voltage level must be within the limits stated in the absolute maximum ratings.
10.3 I/O port implementation
The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific I/O port features such as ADC input or open-drain.
Switching these I/O ports from one state to another should be done in a sequence that
prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 35 .
Other transitions are potentially risky and should be avoided, since they may present unwanted side-effects such as spurious interrupt generation.
Figure 35.
Interrupt I/O port state transitions
01 00
INPUT floating/pull-up interrupt
INPUT floating
(reset state)
10
OUTPUT open-drain
XX = DDR, OR
11
OUTPUT push-pull
10.4 Unused I/O pins
Unused I/O pins must be connected to fixed voltage levels. Refer to
Section 13.9: I/O port pin characteristics .
10.5 Low power modes
s
Table 26.
Effect of low power modes on I/O ports
Mode Description
Wait
Halt
No effect on I/O ports. External interrupts cause the device to exit from Wait mode.
No effect on I/O ports. External interrupts cause the device to exit from Halt mode.
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ST7LITE49M I/O ports
10.6 Interrupts
The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and if the I bit in the CC register is cleared (RIM instruction).
Table 27.
Description of interrupt events
Interrupt event
External interrupt on selected external event
Event flag
-
Enable control bit
DDRx
ORx
Exit from
Wait
Yes
Exit from
Halt
Yes
See application notes AN1045 software implementation of I
2
C bus master, and AN1048 - software LCD driver
10.7 Device-specific I/O port configuration
The I/O port register configurations are summarized in
Section 10.7.1: Standard ports and
Table 28.
PA5:0, PB7:0, PC7:4 and PC2:0 pins
Mode floating input pull-up interrupt input open-drain output push-pull output
Table 29.
PA7:6 pins
Mode floating input interrupt input open-drain output push-pull output
M
Table 30.
PC3 pin
Mode floating input pull-up input
Doc ID 13562 Rev 3
DDR
0
0
1
1
OR
0
1
0
1
DDR
0
0
1
1
DDR
0
0
OR
0
1
0
1
OR
0
1
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Table 30.
PC3 pin (continued)
Mode open-drain output push-pull output
Table 31.
Port configuration
Port
Port A
Port B
Port C
Pin name
PA5:0
PA7:6
PB7:0
PC7:4,
PC2:0
PC3
OR = 0 floating floating floating
Input
OR = 1 pull-up interrupt interrupt pull-up interrupt floating floating pull-up interrupt pull-up
Table 32.
I/O port register mapping and reset values
Address
(Hex.)
Register label
7 6 5 4
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
PADR
Reset value
PADDR
Reset value
PAOR
Reset value
PBDR
Reset value
PBDDR
Reset value
PBOR
Reset value
PCDR
Reset value
PCDDR
Reset value
PCOR
Reset value
MSB
0
MSB
0
MSB
0
MSB
0
MSB
0
MSB
0
MSB
0
MSB
0
MSB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
0
0
0
0
0
0
0
0
1
DDR
1
1
OR
0
1
Output
OR = 0 OR = 1 open-drain push-pull true open-drain open-drain push-pull open-drain open-drain push-pull push-pull
2
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
LSB
0
LSB
0
LSB
0
LSB
0
LSB
0
LSB
0
LSB
0
LSB
0
LSB
0
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ST7LITE49M On-chip peripherals
11.1 Watchdog timer (WDG)
11.1.1 Introduction
The watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter’s contents before the T6 bit becomes cleared.
●
●
●
●
●
Programmable free-running downcounter (64 increments of 16000 CPU cycles)
Programmable reset
Reset (if watchdog activated) when the T6 bit reaches zero
Optional reset on HALT instruction (configurable by option byte)
Hardware Watchdog selectable by option byte
The counter value stored in the CR register (bits T[6:0]), is decremented every 16000 machine cycles, and the length of the timeout period can be programmed by the user in 64 increments.
If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the RESET pin for typically 30 µs.
Figure 36.
Watchdog block diagram
RESET f
CPU
WDGA T6
WATCHDOG CONTROL REGISTER (CR)
T5 T4 T3 T2
7-BIT DOWNCOUNTER
T1 T0
CLOCK DIVIDER
÷
16000
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On-chip peripherals ST7LITE49M
●
●
●
The application program must write in the CR register at regular intervals during normal operation to prevent an MCU reset. This downcounter is free-running: it counts down even if the watchdog is disabled. The value to be stored in the CR register must be between FFh
and C0h (see Table 33: Watchdog timing ):
The WDGA bit is set (watchdog enabled)
The T6 bit is set to prevent generating an immediate reset
The T[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset.
Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by a reset.
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared).
If the watchdog is activated, the HALT instruction will generate a reset.
Table 33.
Watchdog timing
(1)(2)
WDG counter code f
CPU
= 8 MHz min
[ms] max
[ms]
C0h
FFh
1
127
2
128
1.
The timing variation shown in
Table 33 is due to the unknown status of the prescaler when writing to the
CR register.
2.
The number of CPU clock cycles applied during the reset phase (256 or 4096) must be taken into account in addition to these timings.
If Hardware Watchdog is selected by option byte, the watchdog is always active and the
WDGA bit in the CR is not used.
Refer to the option byte description in
.
Using Halt mode with the WDG (WDGHALT option)
If Halt mode with Watchdog is enabled by option byte (No watchdog reset on HALT instruction), it is recommended before executing the HALT instruction to refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.
Same behavior in Active-halt mode.
11.1.5 Interrupts
None.
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ST7LITE49M On-chip peripherals
Note:
Control register (WDGCR)
Reset value: 0111 1111 (7Fh)
7
WDGA T6 T5 T4
Read/Write
T3 T2 T1
0
T0
Bit 7 = WDGA Activation bit
This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
This bit is not used if the hardware watchdog option is enabled by option byte.
Bits 6:0 = T[6:0] 7-bit timer (MSB to LSB)
These bits contain the decremented value. A reset is produced when it rolls over from
40h to 3Fh (T6 becomes cleared).
Table 34.
Watchdog timer register mapping and reset values
Address
(Hex.)
Register label
7 6 5 4 3 2
0033h
WDGCR
Reset value
WDGA
0
T6
1
T5
1
T4
1
T3
1
T2
1
1
T1
1
0
T0
1
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On-chip peripherals ST7LITE49M
11.2 Dual 12-bit autoreload timer
11.2.1 Introduction
●
●
●
The 12-bit autoreload timer can be used for general-purpose timing functions. It is based on one or two free-running 12-bit upcounters with an input capture register and four PWM output channels. There are 7 external pins:
Four PWM outputs
ATIC/LTIC pins for the input capture function
BREAK pin for forcing a break condition on the PWM outputs
●
●
●
●
●
●
●
●
●
Single timer or dual timer mode with two 12-bit upcounters (CNTR1/CNTR2) and two
12-bit autoreload registers (ATR1/ATR2)
Maskable overflow interrupts
PWM mode
– Generation of four independent PWMx signals
– Dead time generation for Half bridge driving mode with programmable dead time
– Frequency 2 kHz - 4 MHz (@ 8 MHz f
CPU
)
– Programmable duty-cycles
– Polarity control
– Programmable output modes
Output Compare mode
Input Capture mode
– 12-bit input capture register (ATICR)
– Triggered by rising and falling edges
– Maskable IC interrupt
– Long range input capture
Internal/external break control
Flexible clock control
One-pulse mode on PWM2/3
Force update
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ST7LITE49M On-chip peripherals
Figure 37.
Single timer mode (ENCNTR2=0)
ATIC
Edge Detection Circuit
12-bit Input Capture
Output Compare
CMP
Interrupt
PWM0 Duty Cycle Generator
PWM1 Duty Cycle Generator
12-Bit Autoreload register 1
PWM2 Duty Cycle Generator
12-Bit Upcounter 1
OVF1 interrupt
PWM3 Duty Cycle Generator
Dead Time
Generator
OE0
OE1
DTE bit
OE2
OE3
PWM0
PWM1
PWM2
PWM3
BPEN bit
Clock
Control
OFF f
CPU
1 ms from
Lite timer
Figure 38.
Dual timer mode (ENCNTR2=1)
ATIC Edge Detection Circuit
12-Bit Autoreload register 1
12-Bit Upcounter 1
12-Bit Upcounter 2
12-bit Input Capture
Output Compare
CMP
Interrupt
PWM0 Duty Cycle Generator
PWM1 Duty Cycle Generator
OVF1 interrupt
OVF2 interrupt
PWM2 Duty Cycle Generator
PWM3 Duty Cycle Generator
Dead Time
Generator
OE0
OE1
DTE bit
One-pulse mode
OE2
OE3
12-Bit Autoreload register 2
Clock
Control
OFF f
CPU
1 ms from
Lite timer
Output Compare
CMP Interrupt
OP_EN bit
BPEN bit
PWM0
PWM1
PWM2
PWM3
LTIC
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On-chip peripherals ST7LITE49M
PWM mode
This mode allows up to four pulse width modulated signals to be generated on the PWMx output pins.
● PWM frequency
The four PWM signals can have the same frequency (f
PWM
) or can have two different frequencies. This is selected by the ENCNTR2 bit which enables Single timer or Dual
timer mode (see Figure 37 and Figure 38
). The frequency is controlled by the counter period and the ATR register value. In Dual timer mode, PWM2 and PWM3 can be generated with a different frequency controlled by CNTR2 and ATR2.
● f
PWM
= f
COUNTER
⁄ (
4096 – ATR
)
Following the above formula, if f
COUNTER
equals 4 MHz
, the maximum value of f
PWM
2 MHz (ATR register value = 4094), and the minimum value is 1 kHz (ATR register
is value = 0).
The maximum value of ATR is 4094 because it must be lower than the DC4R value which must be 4095 in this case.
To update the DCRx registers at 32 MHz, the following precautions must be taken:
– If the PWM frequency is < 1 MHz and the TRANx bit is set asynchronously, it should be set twice after a write to the DCRx registers.
– If the PWM frequency is > 1 MHz, the TRANx bit should be set along with
FORCEx bit with the same instruction (use a load instruction and not 2 bset instructions).
Duty cycle
The duty cycle is selected by programming the DCRx registers. These are preload registers. The DCRx values are transferred in Active duty cycle registers after an overflow event if the corresponding transfer bit (TRANx bit) is set.
The TRAN1 bit controls the PWMx outputs driven by counter 1 and the TRAN2 bit controls the PWMx outputs driven by counter 2.
PWM generation and output compare are done by comparing these active DCRx values with the counter.
The maximum available resolution for the PWMx duty cycle is:
Resolution = 1 ⁄ ( 4096 – ATR ) where ATR is equal to 0. With this maximum resolution, 0% and 100% duty cycle can be obtained by changing the polarity.
At reset, the counter starts counting from 0.
When a upcounter overflow occurs (OVF event), the preloaded Duty cycle values are transferred to the active Duty Cycle registers and the PWMx signals are set to a high level. When the upcounter matches the active DCRx value the PWMx signals are set to a low level. To obtain a signal on a PWMx pin, the contents of the corresponding active
DCRx register must be greater than the contents of the ATR register.
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ST7LITE49M On-chip peripherals
●
The maximum value of ATR is 4094 because it must be lower than the DCR value which must be 4095 in this case.
Polarity inversion
The polarity bits can be used to invert any of the four output signals. The inversion is synchronized with the counter overflow if the corresponding transfer bit in the ATCSR2
register is set (reset value). See Figure 39 .
Figure 39.
PWM polarity inversion inverter
PWMx
PWMx
PIN
PWMxCSR register
OPx
TRANx
ATCSR2 register counter overflow
DFF
The data flip flop (DFF) applies the polarity inversion when triggered by the counter overflow input.
● Output control
The PWMx output signals can be enabled or disabled using the OEx bits in the
PWMCR register.
Figure 40.
PWM function
4095
DUTY CYCLE
REGISTER
(DCRx)
AUTO-RELOAD
REGISTER
(ATR)
000
WITH OE=1
AND OPx=0
WITH OE=1
AND OPx=1 t
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On-chip peripherals
Figure 41.
PWM signal from 0% to 100% duty cycle f
COUNTER
COUNTER
FFDh FFEh
ATR= FFDh
FFFh FFDh FFEh
DCRx=000h
DCRx=FFDh
DCRx=FFEh
ST7LITE49M
FFFh FFDh FFEh
DCRx=000h t
Dead time generation
A dead time can be inserted between PWM0 and PWM1 using the DTGR register. This is required for half-bridge driving where PWM signals must not be overlapped. The nonoverlapping PWM0/PWM1 signals are generated through a programmable dead time by setting the DTE bit.
Dead time = DT 6:0 ] × Tcounter1
DTGR[7:0] is buffered inside so as to avoid deforming the current PWM cycle. The DTGR effect will take place only after an overflow.
Note: 1 Dead time is generated only when DTE=1 and DT[6:0]
≠
0
.
If DTE is set and DT[6:0]=0,
PWM output signals will be at their reset state.
2 Half Bridge driving is possible only if polarities of PWM0 and PWM1 are not inverted, i.e. if
OP0 and OP1 are not set. If polarity is inverted, overlapping PWM0/PWM1 signals will be generated.
3 Dead time generation does not work at 1ms timebase.
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ST7LITE49M
Figure 42.
Dead time generation
T counter1
On-chip peripherals
CK_CNTR1
CNTR1 DCR0 DCR0+1 counter = DCR0
OVF ATR1
PWM 0 counter = DCR1
PWM 1
T dt
PWM 0
T dt
PWM 1
T dt
= DT[6:0] x T counter1
●
●
In the above example, when the DTE bit is set:
PWM goes low at DCR0 match and goes high at ATR1+Tdt
PWM1 goes high at DCR0+Tdt and goes low at ATR match.
With this programmable delay (Tdt), the PWM0 and PWM1 signals which are generated are not overlapped.
Break function
The break function can be used to perform an emergency shutdown of the application being driven by the PWM signals.
The break function is activated by the external BREAK pin. This can be selected by using the BRSEL bit in BREAKCR register. In order to use the break function it must be previously enabled by software setting the BPEN bit in the BREAKCR register.
The Break active level can be programmed by the BREDGE bit in the BREAKCR register.
When an active level is detected on the BREAK pin, the BA bit is set and the break function is activated. In this case, the PWM signals are forced to BREAK value if respective OEx bit is set in PWMCR register.
Software can set the BA bit to activate the break function without using the BREAK pin. The
BREN1 and BREN2 bits in the BREAKEN register are used to enable the break activation on the 2 counters respectively. In Dual Timer mode, the break for PWM2 and PWM3 is enabled by the BREN2 bit. In Single timer mode, the BREN1 bit enables the break for all
PWM channels.
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On-chip peripherals ST7LITE49M
●
●
●
●
When a break function is activated (BA bit =1 and BREN1/BREN2 =1):
● The break pattern (PWM[3:0] bits in the BREAKCR) is forced directly on the PWMx output pins if respective OEx is set. (after the inverter).
The 12-bit PWM counter CNTR1 is put to its reset value, i.e. 00h (if BREN1 = 1).
The 12-bit PWM counter CNTR2 is put to its reset value,i.e. 00h (if BREN2 = 1).
ATR1, ATR2, preload and active DCRx are put to their reset values.
Counters stop counting.
When the break function is deactivated after applying the break (BA bit goes from 1 to 0 by software), Timer takes the control of PWM ports.
Figure 43.
ST7LITE49M block diagram of break function
BRSEL BREDGE BREAKCR register
BREAK pin
Level
Selection
BA BPEN
BREAKCR register
PWM3 PWM2 PWM1 PWM0
OEx
BREAKEN register
BREN2 BREN1
PWM0
PWM1
PWM2
PWM3
(Inverters)
PWM0/1 Break Enable
PWM2/3 Break Enable
PWM0
PWM1
PWM2
PWM3
ENCNTR2 bit
Output compare mode
To use this function, load a 12-bit value in the Preload DCRxH and DCRxL registers.
When the 12-bit upcounter CNTR1 reaches the value stored in the Active DCRxH and
DCRxL registers, the CMPFx bit in the PWMxCSR register is set and an interrupt request is generated if the CMPIE bit is set.
In Single Timer mode the output compare function is performed only on CNTR1. The difference between both the modes is that, in Single timer mode, CNTR1 can be compared with any of the four DCR registers, and in Dual timer mode, CNTR1 is compared with DCR0 or DCR1 and CNTR2 is compared with DCR2 or DCR3.
Note: 1 The output compare function is only available for DCRx values other than 0 (reset value).
2 Duty cycle registers are buffered internally. The CPU writes in Preload duty cycle registers and these values are transferred in Active duty cycle registers after an overflow event if the corresponding transfer bit (TRANx bit) is set. Output compare is done by comparing these active DCRx values with the counters.
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ST7LITE49M
Figure 44.
Block diagram of output compare mode (single timer)
DCRx
PRELOAD DUTY CYCLE REG0/1/2/3
(ATCSR2) TRAN1
(ATCSR) OVF
On-chip peripherals
ACTIVE DUTY CYCLE REGx
CNTR1
COUNTER 1
OUTPUT COMPARE CIRCUIT
CMP
INTERRUPT REQUEST
CMPFx (PWMxCSR)
CMPIE (ATCSR)
Input capture mode
The 12-bit ATICR register is used to latch the value of the 12-bit free running upcounter
CNTR1 after a rising or falling edge is detected on the ATIC pin. When an Input Capture occurs, the ICF bit is set and the ATICR register contains the value of the free running upcounter. An IC interrupt is generated if the ICIE bit is set. The ICF bit is reset by reading the ATICRH/ATICRL register when the ICF bit is set. The ATICR is a read only register and always contains the free running upcounter value which corresponds to the most recent input capture. Any further input capture is inhibited while the ICF bit is set.
Figure 45.
Block diagram of input capture mode
ATIC
ATICR
12-BIT INPUT CAPTURE REGISTER
IC INTERRUPT
REQUEST
ATCSR
ICF ICIE CK1 CK0 f
LTIMER
(1 ms timebase
@ 8MHz) f
CPU
OFF
12-BIT UPCOUNTER1
CNTR1
ATR1
12-BIT AUTORELOAD REGISTER
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On-chip peripherals ST7LITE49M
Figure 46.
Input capture timing diagram f
COUNTER
COUNTER1
01h
ATIC PIN
02h 03h 04h 05h 06h
INTERRUPT
07h
ICF FLAG xxh 04h
08h 09h
ATICR READ
0Ah
09h
INTERRUPT t
Long range input capture
●
●
Pulses that last more than 8 µs can be measured with an accuracy of 4 µs if f
OSC
equals 8
MHz in the following conditions:
● The 12-bit AT4 timer is clocked by the Lite timer (RTC pulse: CK[1:0] = 01 in the ATCSR register)
● The ICS bit in the ATCSR2 register is set so that the LTIC pin is used to trigger the AT4 timer capture.
The signal to be captured is connected to LTIC pin
Input Capture registers LTICR, ATICRH and ATICRL are read
This configuration allows to cascade the Lite timer and the 12-bit AT4 timer to get a 20-bit
input capture value. Refer to Figure 47 .
Figure 47.
Long range input capture block diagram
LTIC
ATIC
LTICR
8-bit Input Capture register 8 LSB bits
ICS f
LTIMER f cpu
OFF
1
0 f
OSC/32 8-bit Timebase Counter1
LITE TIMER
12-bit ARTIMER
ATR1
CNTR1
12-bit AutoReload register
12-bit Upcounter1
ATICR
12-bit Input Capture register 12 MSB bits
20 cascaded bits
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ST7LITE49M On-chip peripherals
Since the input capture flags (ICF) for both timers (AT4 timer and LT timer) are set when signal transition occurs, software must mask one interrupt by clearing the corresponding
ICIE bit before setting the ICS bit.
If the ICS bit changes (from 0 to 1 or from 1 to 0), a spurious transition might occur on the
Input Capture signal because of different values on LTIC and ATIC. To avoid this situation, it is recommended to do as follows:
1.
First, reset both ICIE bits.
2. Then set the ICS bit.
3. Reset both ICF bits.
4. And then set the ICIE bit of desired interrupt.
Computing a pulse length in long input capture mode is not straightforward since both timers are used. The following steps are required:
1.
At the first input capture on the rising edge of the pulse, we assume that values in the registers are the following:
– LTICR = LT1
– ATICRH = ATH1
– ATICRL = ATL1
– Hence ATICR1 [11:0] = ATH1 & ATL1. Refer to
.
2. At the second input capture on the falling edge of the pulse, we assume that the values in the registers are as follows:
– LTICR = LT2
– ATICRH = ATH2
– ATICRL = ATL2
– Hence ATICR2 [11:0] = ATH2 & ATL2.
Now pulse width P between first capture and second capture is given by:
P
+
= decimal
( (
× ( F9
×
–
N )
LT1
+ N
+
+
LT2 + 1 )
ATICR2
×
–
0.004ms
ATICR1 – 1 ) × 1ms where N is the number of overflows of 12-bit CNTR1.
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On-chip peripherals ST7LITE49M
Figure 48.
Long range input capture timing diagram f
OSC/32
TB Counter1
F9h 00h LT1
_ _ _
ATH1 & ATL1 CNTR1
LTIC
LTICR
00h
F9h 00h
_ _ _ _ _ _ _ _ _
LT2
_ _ _ _ _ _
LT1
_ _ _
ATH2 & ATL2
LT2
ATICRH
0h ATH1 ATH2
ATICRL
00h ATL1 ATL2
ATICR = ATICRH[3:0] & ATICRL[7:0]
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ST7LITE49M On-chip peripherals
One-pulse mode
One-pulse mode can be used to control PWM2/3 signal with an external LTIC pin. This mode is available only in Dual Timer mode i.e. only for CNTR2, when the OP_EN bit in
PWM3CSR register is set.
One-pulse mode is activated by the external LTIC input. The active edge of the LTIC pin is selected by the OPEDGE bit in the PWM3CSR register.
After getting the active edge of the LTIC pin, CNTR2 is reset (000h) and PWM3 is set to high. CNTR2 starts counting from 000h, when it reaches the active DCR3 value then PWM3 goes low. Till this time, any further transitions on the LTIC signal will have no effect. If there are LTIC transitions after CNTR2 reaches DCR3 value, CNTR2 is reset again and PWM3 goes high.
If there is no LTIC active edge, CNTR2 counts until it reaches the ATR2 value, then it is reset again and PWM3 is set to high. The counter again starts counting from 000h, when it reaches the active DCR3 value PWM3 goes low, the counter counts until it reaches ATR2, it resets and PWM3 is set to high and so on.
The same operation applies for PWM2, but in this case the comparison is done on DCR2.
OP_EN and OPEDGE bits take effect on the fly and are not synchronized with Counter 2 overflow. The output bit OP2/3 can be used to inverse the polarity of PWM2/3 in one-pulse mode. The update of these bits (OP2/3) is synchronized with the counter 2 overflow, they will be updated if the TRAN2 bit is set.
The time taken from activation of LTIC input and CNTR2 reset is between 1 and 2 t
CPU cycles, that is, 125 ns to 250 ns (with 8-MHz f
CPU
).
Lite timer Input Capture interrupt should be disabled while 12-bit ARtimer is in One-pulse mode. This is to avoid spurious interrupts.
The priority of the various conditions for PWM3 is the following: Break > one-pulse mode with active LTIC edge > Forced overflow by s/w > one-pulse mode without active LTIC edge
> normal PWM operation.
It is possible to update DCR2/3 and OP2/3 at the counter 2 reset, the update is synchronized with the counter reset. This is managed by the overflow interrupt which is generated if counter is reset either due to ATR match or active pulse at LTIC pin. DCR2/3 and OP2/3 update in one-pulse mode is performed dynamically using a software force update. DCR3 update in this mode is not synchronized with any event. That may lead to a longer next PWM3 cycle duration than expected just after the change.
In One-pulse mode ATR2 value must be greater than DCR2/3 value for PWM2/3. (opposite to normal PWM mode).
If there is an active edge on the LTIC pin after the counter has reset due to an ATR2 match, then the timer again gets reset and appears as modified Duty cycle depending on whether the new DCR value is less than or more than the previous value.
The TRAN2 bit should be set along with the FORCE2 bit with the same instruction after a write to the DCR register.
ATR2 value should be changed after an overflow in one-pulse mode to avoid any irregular
PWM cycle.
When exiting from one-pulse mode, the OP_EN bit in the PWM3CSR register should be reset first and then the ENCNTR2 bit (if counter 2 must be stopped).
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On-chip peripherals
Note:
ST7LITE49M
How to enter One-pulse mode
The steps required to enter One-pulse mode are the following:
1.
Load ATR2H/ATR2L with required value.
2. Load DCR3H/DCR3L for PWM3. ATR2 value must be greater than DCR3.
3. Set OP3 in PWM3CSR if polarity change is required.
4. Select CNTR2 by setting ENCNTR2 bit in ATCSR2.
5. Set TRAN2 bit in ATCSR2 to enable transfer.
6. "Wait for Overflow" by checking the OVF2 flag in ATCSR2.
7. Select counter clock using CK<1:0> bits in ATCSR.
8. Set OP_EN bit in PWM3CSR to enable one-pulse mode.
9. Enable PWM3 by OE3 bit of PWMCR.
The "Wait for Overflow" in step 6 can be replaced by a forced update.
Follow the same procedure for PWM2 with the bits corresponding to PWM2.
When break is applied in One-pulse mode, CNTR2, DCR2/3 & ATR2 registers are reset. So, these registers have to be initialized again when break is removed.
Figure 49.
Block diagram of One-pulse mode
LTIC pin
Edge
Selection
OPEDGE OP_EN
PWM3CSR register
12-bit Upcounter 2
12-bit AutoReload register 2
12-bit Active DCR2/3
OP2/3
PWM
Generation
PWM2/3
Figure 50.
One-pulse mode and PWM timing diagram f counter2
CNTR2
LTIC
PWM2/3
000 DCR2/3 000 DCR2/3 ATR2 f counter2
CNTR2
LTIC
PWM2/3
OVF ATR2 DCR2/3 OVF ATR2 DCR2/3 OVF ATR2
Note 1: When OP_EN=0, LTIC edges are not taken into account as the timer runs in PWM mode.
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ST7LITE49M
Figure 51.
Dynamic DCR2/3 update in One-pulse mode f counter2
CNTR2
LTIC
FORCE2
TRAN2
DCR2/3
PWM2/3
000 FFF 000 (DCR3) old
(DCR2/3) old
(DCR3) new
(DCR2/3) new extra PWM3 period due to DCR3 update dynamically in one-pulse mode.
On-chip peripherals
ATR2 000
Force update
In order not to wait for the counter x
overflow to load the value into active DCRx registers, a programmable counter x
overflow is provided. For both counters, a separate bit is provided which when set, make the counters start with the overflow value, i.e. FFFh. After overflow, the counters start counting from their respective auto reload register values.
These bits are FORCE1 and FORCE2 in the ATCSR2 register. FORCE1 is used to force an overflow on Counter 1 and, FORCE2 is used for Counter 2. These bits are set by software and reset by hardware after the respective counter overflow event has occurred.
This feature can be used at any time. All related features such as PWM generation, output compare, input capture, One-pulse (refer to
Figure 51: Dynamic DCR2/3 update in Onepulse mode
) etc. can be used this way.
Figure 52.
Force overflow timing diagram f
CNTRx
FORCEx
CNTRx E03 E04 FFF ARRx
FORCE2 FORCE1
ATCSR2 register
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On-chip peripherals ST7LITE49M
11.2.4 Low power modes
Table 35.
Effect of low power modes on autoreload timer
Mode Description
Wait
Halt
No effect on AT timer
AT timer halted.
11.2.5 Interrupts
Note:
Table 36.
Description of interrupt events
Interrupt event
Event flag
Enable control bit
Overflow Event
AT4 IC Event
Overflow Event2
OVF1
ICF
OVF2
OVIE1
ICIE
OVIE2
Exit from
Wait
Yes
Yes
Yes
Exit from
Halt
No
No
No
Exit from
Active-halt
Yes
No
No
The AT4 IC is connected to an interrupt vector. The OVF event is mapped on a separate vector (see Interrupts chapter).
They generate an interrupt if the enable bit is set in the ATCSR register and the interrupt mask in the CC register is reset (RIM instruction).
Timer control status register (ATCSR)
Reset value: 0x00 0000 (x0h)
7
0 ICF ICIE CK1 CK0
Read / Write
OVF1 OVFIE1
0
CMPIE
Bit 7 = Reserved
Bit 6 = ICF Input capture flag
This Bit is set by hardware and cleared by software by reading the ATICR register (a read access to ATICRH or ATICRL clears this flag). Writing to this bit does not change the bit value.
0: No input capture
1: An input capture has occurred
Bit 5 = ICIE IC interrupt enable bit
This bit is set and cleared by software.
0: Input capture interrupt disabled
1: Input capture interrupt enabled
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ST7LITE49M On-chip peripherals
Bits 4:3 = CK[1:0] Counter clock selection bits
These bits are set and cleared by software and cleared by hardware after a reset. they select the clock frequency of the counter.
Table 37.
Counter clock selection
Counter clock selection CK1 CK0
OFF selection forbidden f
LTIMER
(1 ms timebase @ 8 MHz) f
CPU
0
1
0
1
1
0
0
1
Bit 2 = OVF1 Overflow flag
This bit is set by hardware and cleared by software by reading the ATCSR register. It indicates the transition of the counter1 CNTR1 from FFFh to ATR1 value.
0: No counter overflow occurred
1: Counter overflow occurred
Bit 1 = OVFIE1 Overflow interrupt enable bit
This bit is read/write by software and cleared by hardware after a reset.
0: Overflow Interrupt Disabled.
1: Overflow Interrupt Enabled.
Bit 0 = CMPIE Compare interrupt enable bit
This bit is read/write by software and cleared by hardware after a reset. it can be used to mask the interrupt generated when any of the cmpfx bit is set.
0: Output compare interrupt disabled.
1: Output compare interrupt enabled.
Counter register 1 high (CNTR1H)
Reset value: 0000 0000 (00h)
15
0 0 0 0
CNTR1_
11
Read only
8
CNTR1_
10
CNTR1_9 CNTR1_8
Counter register 1 low (CNTR1L)
Reset value: 0000 0000 (00h)
7 0
CNTR1_7 CNTR1_6 CNTR1_5 CNTR1_4 CNTR1_3 CNTR1_2 CNTR1_1 CNTR1_0
Read only
Bits 15:12 = Reserved
Doc ID 13562 Rev 3 93/188
On-chip peripherals ST7LITE49M
Bits 11:0 = CNTR1[11:0] Counter value
This 12-bit register is read by software and cleared by hardware after a reset. The counter CNTR1 increments continuously as soon as a counter clock is selected. To obtain the 12-bit value, software should read the counter value in two consecutive read operations. As there is no latch, it is recommended to read LSB first. In this case,
CNTR1H can be incremented between the two read operations and to have an accurate result when f timer
=f
CPU
, special care must be taken when CNTR1L values close to FFh are read.
When a counter overflow occurs, the counter restarts from the value specified in the
ATR1 register.
Autoreload register (ATR1H)
Reset value: 0000 0000 (00h)
15
0 0 0 0 ATR11
Read/write
ATR10 ATR9
8
ATR8
Autoreload register (ATR1L)
Reset value: 0000 0000 (00h)
7
ATR7 ATR6 ATR5 ATR4 ATR3
Read/write
ATR2 ATR1
0
ATR0
Bits 11:0 = ATR1[11:0] Autoreload register 1:
This is a 12-bit register which is written by software. The ATR1 register value is automatically loaded into the upcounter CNTR1 when an overflow occurs. The register value is used to set the PWM frequency.
PWM output control register (PWMCR)
Reset value: 0000 0000 (00h)
7
0 OE3 0 OE1 0
0
OE0 OE2
Read/write
0
Bits 7:0 = OE[3:0] PWMx output enable bits
These bits are set and cleared by software and cleared by hardware after a reset.
0: PWM mode disabled. PWMx output alternate function disabled (I/O pin free for general purpose I/O)
1: PWM mode enabled
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ST7LITE49M On-chip peripherals
PWMX control status register (PWMxCSR)
Reset value: 0000 0000 (00h)
7
0 0 0 0 OP_EN OPEDGE
Read/write
OPx
0
CMPFx
Bits 7:4= Reserved, must be kept cleared.
Bit 3 = OP_EN One-pulse mode enable bit
This bit is read/write by software and cleared by hardware after a reset. This bit enables the One-pulse feature for PWM2 and PWM3 (only available for PWM3CSR)
0: One-pulse mode disable for PWM2/3.
1: One-pulse mode enable for PWM2/3.
Bit 2 = OPEDGE One-pulse edge selection bit
This bit is read/write by software and cleared by hardware after a reset. This bit selects the polarity of the LTIC signal for One-pulse feature. This bit will be effective only if
OP_EN bit is set (only available for PWM3CSR)
0: Falling edge of LTIC is selected.
1: Rising edge of LTIC is selected.
Bit 1 = OPx PWMx output polarity bit
This bit is read/write by software and cleared by hardware after a reset. This bit selects the polarity of the PWM signal.
0: The PWM signal is not inverted.
1: The PWM signal is inverted.
Bit 0 = CMPFx PWMx compare flag
This bit is set by hardware and cleared by software by reading the PWMxCSR register.
It indicates that the upcounter value matches the Active DCRx register value.
0: Upcounter value does not match DCRx value.
1: Upcounter value matches DCRx value.
Break control register (BREAKCR)
Reset value: 0000 0000 (00h)
7
0 BREDGE BA PWM2 PWM1
0
PWM0 BPEN PWM3
Read/write
Bit 7 = Reserved
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On-chip peripherals ST7LITE49M
Bit 6 = BREDGE Break input edge selection bit
This bit is read/write by software and cleared by hardware after reset. It selects the active level of Break signal.
0: Low level of Break selected as active level
1: High level of Break selected as active level
Bit 5 = BA Break active bit
This bit is read/write by software, cleared by hardware after reset and set by hardware when the active level defined by the BR1EDGE bit is applied on the BREAK pin. It activates/deactivates the Break function.
0: Break not active
1: Break active
Bit 4 = BPEN Break pin enable bit
This bit is read/write by software and cleared by hardware after reset.
0: Break pin disabled
1: Break pin enabled
Bits 3:0 = PWM[3:0] Break pattern bits
These bits are read/write by software and cleared by hardware after a reset. They are used to force the four PWMx output signals into a stable state when the Break function is active and corresponding OEx bit is set.
PWMx duty cycle register High (DCRxH)
Reset value: 0000 0000 (00h)
15
0 0 0 DCR10 DCR9
8
DCR8 0 DCR11
Read/write
Bits 15:12 = Reserved.
PWMx duty cycle register Low (DCRxL)
Reset value: 0000 0000 (00h)
7
DCR7 DCR6 DCR5 DCR4 DCR3
Read/write
DCR2 DCR1
0
DCR0
Bits 11:0 = DCRx[11:0] PWMx duty cycle value: this 12-bit value is written by software. It
defines the duty cycle of the corresponding PWM output signal (see Figure 40 ).
In PWM mode (OEx=1 in the PWMCR register) the DCR[11:0] bits define the duty cycle of the PWMx output signal (see
). In output compare mode, they define the value to be compared with the 12-bit upcounter value.
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ST7LITE49M On-chip peripherals
Input capture register high (ATICRH)
Reset value: 0000 0000 (00h)
15
0 0 0 0 ICR11
Read only
ICR10 ICR9
8
ICR8
Bits 15:12 = Reserved.
Input capture register low (ATICRL)
Reset value: 0000 0000 (00h)
7
ICR7 ICR6 ICR5 ICR4 ICR3
Read only
ICR2 ICR1
0
ICR0
Bits 11:0 = ICR[11:0] Input capture data .
This is a 12-bit register which is readable by software and cleared by hardware after a reset. The ATICR register contains captured the value of the 12-bit CNTR1 register when a rising or falling edge occurs on the ATIC or LTIC pin (depending on ICS).
Capture will only be performed when the ICF flag is cleared.
Break enable register (BREAKEN)
Reset value: 0000 0011 (03h)
7
0 0 0 0
Read/write
0 0 BREN2
0
BREN1
Bits 7:2 = Reserved, must be kept cleared.
Bit 1 = BREN2 Break enable for counter 2 bit
This bit is read/write by software. It enables the break functionality for Counter2 if BA bit is set in BREAKCR. It controls PWM2/3 if ENCNTR2 bit is set.
0: No Break applied for CNTR2
1: Break applied for CNTR2
Bit 0 = BREN1 Break enable for counter 1 bit
This bit is read/write by software. It enables the break functionality for Counter1. If BA bit is set, it controls PWM0/1 by default, and controls PWM2/3 also if ENCNTR2 bit is reset.
0: No Break applied for CNTR1
1: Break applied for CNTR1
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On-chip peripherals
Note:
Note:
Note:
ST7LITE49M
Timer control register 2 (ATCSR2)
Reset value: 0000 0011 (03h)
7
FORCE2 FORCE1 ICS OVFIE2 OVF2
Read/write
ENCNTR2 TRAN2
0
TRAN1
Bit 7 = FORCE2 Force counter 2 overflow bit
This bit is read/set by software. When set, it loads FFFh in the CNTR2 register. It is reset by hardware one CPU clock cycle after counter 2 overflow has occurred.
0 : No effect on CNTR2
1 : Loads FFFh in CNTR2
This bit must not be reset by software
Bit 6 = FORCE1 Force counter 1 overflow bit
This bit is read/set by software. When set, it loads FFFh in CNTR1 register. It is reset by hardware one CPU clock cycle after counter 1 overflow has occurred.
0 : No effect on CNTR1
1 : Loads FFFh in CNTR1
This bit must not be reset by software
Bit 5 = ICS Input capture shorted bit
This bit is read/write by software. It allows the ATtimer CNTR1 to use the LTIC pin for long Input Capture.
0 : ATIC for CNTR1 input capture
1 : LTIC for CNTR1 input capture
Bit 4 = OVFIE2 Overflow interrupt 2 enable bit
This bit is read/write by software and controls the overflow interrupt of counter2.
0: Overflow interrupt disabled.
1: Overflow interrupt enabled.
Bit 3 = OVF2 Overflow flag
This bit is set by hardware and cleared by software by reading the ATCSR2 register. It indicates the transition of the counter2 from FFFh to ATR2 value.
0: No counter overflow occurred
1: Counter overflow occurred
Bit 2 = ENCNTR2 Enable counter2 for PWM2/3
This bit is read/write by software and switches the PWM2/3 operation to the CNTR2 counter. If this bit is set, PWM2/3 will be generated using CNTR2.
0: PWM2/3 is generated using CNTR1.
1: PWM2/3 is generated using CNTR2.
Counter 2 gets frozen when the ENCNTR2 bit is reset. When ENCNTR2 is set again, the counter will restart from the last value.
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ST7LITE49M On-chip peripherals
Bit 1= TRAN2 Transfer enable2 bit
This bit is read/write by software, cleared by hardware after each completed transfer and set by hardware after reset. It controls the transfers on CNTR2.
It allows the value of the Preload DCRx registers to be transferred to the Active DCRx registers after the next overflow event.
The OPx bits are transferred to the shadow OPx bits in the same way.
Note: 1 DCR2/3 transfer will be controlled using this bit if ENCNTR2 bit is set.
2 This bit must not be reset by software
Bit 0 = TRAN1 Transfer enable 1 bit
This bit is read/write by software, cleared by hardware after each completed transfer and set by hardware after reset. It controls the transfers on CNTR1. It allows the value of the Preload DCRx registers to be transferred to the Active DCRx registers after the next overflow event.
The OPx bits are transferred to the shadow OPx bits in the same way.
Note: 1 DCR0,1 transfers are always controlled using this bit.
2 DCR2/3 transfer will be controlled using this bit if ENCNTR2 is reset.
3 This bit must not be reset by software
Autoreload register 2 (ATR2H)
Reset value: 0000 0000 (00h)
15
0 0 0 0 ATR11
Read/write
ATR10 ATR9
8
ATR8
Autoreload register (ATR2L)
Reset value: 0000 0000 (00h)
7
ATR7 ATR6 ATR5 ATR4 ATR3
Read/write
ATR2 ATR1
0
ATR0
Bits 11:0 = ATR2[11:0] Autoreload register 2
This is a 12-bit register which is written by software. The ATR2 register value is automatically loaded into the upcounter CNTR2 when an overflow of CNTR2 occurs. The register value is used to set the PWM2/PWM3 frequency when ENCNTR2 is set.
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On-chip peripherals ST7LITE49M
Dead time generator register (DTGR)
Reset value: 0000 0000 (00h)
7
DTE DT6 DT5 DT4 DT3
Read/write
DT2 DT1
0
DT0
Note:
Bit 7 = DTE Dead time enable bit
This bit is read/write by software. It enables a dead time generation on PWM0/PWM1.
0: No Dead time insertion.
1: Dead time insertion enabled.
Bits 6:0 = DT[6:0] Dead time value
These bits are read/write by software. They define the dead time inserted between
PWM0/PWM1. Dead time is calculated as follows:
Dead Time = DT[6:0] x Tcounter1
If DTE is set and DT[6:0]=0, PWM output signals will be at their reset state.
Table 38.
Register mapping and reset values
Add.
(Hex)
Register label
7 6 5 4 3 2 1 0
0011
0012
0013
0014
0015
0016
0017
0018
0019
001A
001B
ATR1H
Reset value
ATR1L
Reset value
PWMCR
Reset value
PWM0CSR
Reset value
PWM1CSR
Reset value
PWM2CSR
Reset value
PWM3CSR
Reset value
DCR0H
Reset value
ATCSR
Reset value
CNTR1H
Reset value
CNTR1L
Reset value
0
0
CNTR1_7
0
CNTR1_8
0
CNTR1_
7
0
CNTR1_6
0
CNTR1_3
0
0
ATR7
0
0
0
ATR6
0
OE3
0
0
ATR5
0
0
0
ATR4
0
OE2
0
ATR11
0
ATR3
0
0
0
0
0
ICF
0
0
0
0
0
ICIE
0
0
0
0
0
CK1
0
0
0
0
0
CK0
0
CNTR1_1
1
0
OVF1
0
OVFIE1
0
CMPIE
0
CNTR1_1
0
0
CNTR1_9
0
CNTR1_
8
0
0
0
0
CNTR1_2
0
ATR10
0
ATR2
0
OE1
0
0
0
0
CNTR1_1
0
CNTR1_
0
0
ATR9
0
ATR1
0
0
OP0
0
OP1
0
OP2
0
ATR8
0
ATR0
0
OE0
0
CMPF0
0
CMPF1
0
CMPF2
0
0
0
0
0
0
0
0
0
OP_EN
0
DCR11
0
OPEDGE
0
DCR10
0
OP3
0
DCR9
0
CMPF3
0
DCR8
0
100/188 Doc ID 13562 Rev 3
ST7LITE49M On-chip peripherals
Table 38.
Register mapping and reset values (continued)
Add.
(Hex)
Register label
7 6 5 4
DCR7
0
DCR6
0
DCR5
0
DCR4
0
001C
001D
001E
001F
0020
0021
0022
0023
0024
0025
DCR0L
Reset value
DCR1H
Reset value
DCR1L
Reset value
DCR2H
Reset value
DCR2L
Reset value
DCR3H
Reset value
DCR3L
Reset value
ATICRH
Reset value
ATICRL
Reset value
ATCSR2
Reset value
0026
0027
0028
0029
002A
BREAKCR
Reset value
ATR2H
Reset value
ATR2L
Reset value
DTGR
Reset value
BREAKEN
Reset value
0
DCR7
0
0
DCR7
0
0
DCR7
0
0
ICR7
0
FORCE2
0
0
ICR6
0
FORCE1
0
BREDGE
0
0
ATR7
0
DTE
0
0
0
DCR6
0
0
DCR6
0
0
DCR6
0
0
0
ATR6
0
DT6
0
0
0
DCR5
0
0
DCR5
0
0
DCR5
0
0
ICR5
0
ICS
0
BA
0
0
ATR5
0
DT5
0
0
0
DCR4
0
0
DCR4
0
0
DCR4
0
0
ICR4
0
OVFIE2
0
BPEN
0
0
ATR4
0
DT4
0
0
3
PWM3
0
ATR11
0
ATR3
0
DT3
0
DCR3
0
DCR11
0
DCR3
0
ICR11
0
ICR3
0
OVF2
0
DCR3
0
DCR11
0
DCR3
0
DCR11
0
0
2 1 0
0
PWM1
0
ATR9
0
ATR1
0
DT1
0
BREN2
1
DCR1
0
DCR9
0
DCR1
0
ICR9
0
ICR1
0
TRAN2
1
DCR1
0
DCR9
0
DCR1
0
DCR9
0
DCR2
0
DCR10
0
DCR2
0
DCR10
0
DCR2
0
DCR10
0
DCR2
0
ICR10
0
ICR2
0
ENCNTR2
0
PWM2
0
ATR10
0
ATR2
0
DT2
0
PWM0
0
ATR8
0
ATR0
0
DT0
0
BREN1
1
DCR0
0
DCR8
0
DCR0
0
ICR8
0
ICR0
0
TRAN1
1
DCR0
0
DCR8
0
DCR0
0
DCR8
0
Doc ID 13562 Rev 3 101/188
On-chip peripherals ST7LITE49M
11.3 Lite timer 2 (LT2)
11.3.1 Introduction
The Lite timer can be used for general-purpose timing functions. It is based on two freerunning 8-bit upcounters and an 8-bit input capture register.
●
●
Real-time clock
– One 8-bit upcounter 1 ms or 2 ms timebase period (@ 8 MHz f
OSC
)
– One 8-bit upcounter with autoreload and programmable timebase period from 4 µs to 1.024 ms in 4 µs increments (@ 8 MHz f
OSC
)
– 2 maskable timebase interrupts
Input capture
– 8-bit input capture register (LTICR)
Maskable interrupt with wakeup from Halt mode capability ●
Figure 53.
Lite timer 2 block diagram f
OSC
/32
LTCNTR
8-bit TIMEBASE
COUNTER 2
LTCSR2
0 0 0 0 0 0 TB2IE TB2F
LTTB2
Interrupt request
8
LTARR
8-bit AUTORELOAD
REGISTER f
LTIMER
To 12-bit AT TImer
LTIC
8-bit TIMEBASE
COUNTER 1
/2 f
LTIMER
1
0 Timebase
1 or 2 ms
(@ 8 MHz f
OSC
)
8
LTICR
8-bit
INPUT CAPTURE
REGISTER
LTCSR1
ICIE ICF TB TB1IE TB1F
LTTB1 INTERRUPT REQUEST
LTIC INTERRUPT REQUEST
102/188 Doc ID 13562 Rev 3
ST7LITE49M On-chip peripherals
Timebase counter 1
The 8-bit value of counter 1 cannot be read or written by software. After an MCU reset, it starts incrementing from 0 at a frequency of f
OSC
/32. An overflow event occurs when the counter rolls over from F9h to 00h. If f
OSC
= 8 MHz, then the time period between two counter overflow events is 1 ms. This period can be doubled by setting the TB bit in the
LTCSR1 register.
When Counter 1 overflows, the TB1F bit is set by hardware and an interrupt request is generated if the TB1IE bit is set. The TB1F bit is cleared by software reading the LTCSR1 register.
Input capture
The 8-bit Input Capture register is used to latch the free-running upcounter (Counter 1) 1 after a rising or falling edge is detected on the LTIC pin. When an Input Capture occurs, the
ICF bit is set and the LTICR register contains the counter 1 value. An interrupt is generated if the ICIE bit is set. The ICF bit is cleared by reading the LTICR register.
The LTICR is a read-only register and always contains the data from the last Input Capture.
Input Capture is inhibited if the ICF bit is set.
Timebase counter 2
Counter 2 is an 8-bit autoreload upcounter. It can be read by accessing the LTCNTR register. After an MCU reset, it increments at a frequency of f
OSC
/32 starting from the value stored in the LTARR register. A counter overflow event occurs when the counter rolls over from FFh to the LTARR reload value. Software can write a new value at any time in the
LTARR register, this value will be automatically loaded in the counter when the next overflow occurs.
When Counter 2 overflows, the TB2F bit in the LTCSR2 register is set by hardware and an interrupt request is generated if the TB2IE bit is set. The TB2F bit is cleared by software reading the LTCSR2 register.
Figure 54.
Input capture timing diagram
4µs
(@ 8 MHz f
OSC
) f
CPU f
OSC
/32
8-bit COUNTER 1 01h 02h 03h 04h 05h 06h 07h
CLEARED
BY S/W
READING
LTIC REGISTER
LTIC PIN
ICF FLAG
LTICR REGISTER xxh 04h 07h t
Doc ID 13562 Rev 3 103/188
On-chip peripherals ST7LITE49M
11.3.4 Low power modes
Table 39.
Effect of low power modes on Lite timer 2
Mode Description
Slow
Wait
No effect on Lite timer
(this peripheral is driven directly by f
OSC
/32)
No effect on Lite timer
Active-halt
Halt
No effect on Lite timer
Lite timer stops counting
11.3.5 Interrupts
Table 40.
Description of interrupt events
Interrupt event
Timebase 1 Event
Timebase 2 Event
IC Event
Event flag
TB1F
TB2F
ICF
Enable control
Bit
TB1IE
TB2IE
ICIE
Exit from
Wait
Yes
Exit from
Active-halt
Yes
No
No
Exit from
Halt
No
The TBxF and ICF interrupt events are connected to separate interrupt vectors (see
).
They generate an interrupt if the enable bit is set in the LTCSR1 or LTCSR2 register and the interrupt mask in the CC register is reset (RIM instruction).
Lite timer control/status register 2 (LTCSR2)
Reset value: 0000 0000 (00h)
7
0 0 0 0 0
Read / Write
Bits 7:2 = Reserved, must be kept cleared.
Bit 1 = TB2IE Timebase 2 Interrupt enable bit
This bit is set and cleared by software.
0: Timebase (TB2) interrupt disabled
1: Timebase (TB2) interrupt enabled
0 TB2IE
0
TB2F
104/188 Doc ID 13562 Rev 3
ST7LITE49M On-chip peripherals
Bit 0 = TB2F Timebase 2 Interrupt flag
This bit is set by hardware and cleared by software reading the LTCSR register. Writing to this bit has no effect.
0: No Counter 2 overflow
1: A Counter 2 overflow has occurred
Lite timer autoreload register (LTARR)
Reset value: 0000 0000 (00h)
7
AR7 AR6 AR5 AR4 AR3
Read / Write
AR2 AR1
0
AR0
Bits 7:0 = AR[7:0] Counter 2 reload value
These bits register is read/write by software. The LTARR value is automatically loaded into
Counter 2 (LTCNTR) when an overflow occurs.
Lite timer counter 2 (LTCNTR)
Reset value: 0000 0000 (00h)
7
CNT7 CNT6 CNT5 CNT4 CNT3
Read only
CNT2 CNT1
0
CNT0
Bits 7:0 = CNT[7:0] Counter 2 Reload value
This register is read by software. The LTARR value is automatically loaded into Counter
2 (LTCNTR) when an overflow occurs.
Lite timer control/status register (LTCSR1)
Reset value: 0x00 0000 (x0h)
7
ICIE ICF TB TB1IE TB1F
Read / Write
Bit 7 = ICIE Interrupt enable bit
This bit is set and cleared by software.
0: Input Capture (IC) interrupt disabled
1: Input Capture (IC) interrupt enabled
0
Doc ID 13562 Rev 3 105/188
On-chip peripherals ST7LITE49M
Note:
Bit 6 = ICF Input capture flag
This bit is set by hardware and cleared by software by reading the LTICR register.
Writing to this bit does not change the bit value.
0: No Input Capture
1: An Input Capture has occurred
After an MCU reset, software must initialize the ICF bit by reading the LTICR register
Bit 5 = TB Timebase period selection bit
This bit is set and cleared by software.
0: Timebase period = t
OSC
* 8000 (1 ms @ 8 MHz)
1: Timebase period = t
OSC
* 16000 (2 ms @ 8 MHz)
Bit 4 = TB1IE Timebase Interrupt enable bit
This bit is set and cleared by software.
0: Timebase (TB1) interrupt disabled
1: Timebase (TB1) interrupt enabled
Bit 3 = TB1F Timebase Interrupt flag
This bit is set by hardware and cleared by software reading the LTCSR register. Writing to this bit has no effect.
0: No counter overflow
1: A counter overflow has occurred
Bits 2:0 = Reserved, must be kept cleared.
Lite timer input capture register (LTICR)
Reset value: 0000 0000 (00h)
7
ICR7 ICR6 ICR5 ICR4 ICR3
Read only
ICR2 ICR1
0
ICR0
Bits 7:0 = ICR[7:0] Input capture value
These bits are read by software and cleared by hardware after a reset. If the ICF bit in the
LTCSR is cleared, the value of the 8-bit up-counter will be captured when a rising or falling edge occurs on the LTIC pin.
Table 41.
Lite timer register mapping and reset values
Address
(Hex.)
Register label
7 6 5 4
0C
0D
0E
LTCSR2
Reset value
LTARR
Reset value
LTCNTR
Reset value
0
AR7
0
CNT7
0
0
AR6
0
CNT6
0
0
AR5
0
CNT5
0
0
AR4
0
CNT4
0
3
0
AR3
0
CNT3
0
2
0
AR2
0
CNT2
0
1
TB2IE
0
AR1
0
CNT1
0
0
TB2F
0
AR0
0
CNT0
0
106/188 Doc ID 13562 Rev 3
ST7LITE49M
Table 41.
Lite timer register mapping and reset values (continued)
Address
(Hex.)
Register label
7 6 5 4 3
0F
10
LTCSR1
Reset value
LTICR
Reset value
ICIE
0
ICR7
0
ICF x
ICR6
0
TB
0
ICR5
0
TB1IE
0
ICR4
0
TB1F
0
ICR3
0
2
0
ICR2
0
On-chip peripherals
1
0
ICR1
0
0
0
ICR0
0
Doc ID 13562 Rev 3 107/188
On-chip peripherals ST7LITE49M
11.4 I
2
C bus interface (I
2
C)
11.4.1 Introduction
The I
2
C Bus Interface serves as an interface between the microcontroller and the serial I
2
C bus. It provides both multimaster and slave functions, and controls all I
2
C bus-specific sequencing, protocol, arbitration and timing. It supports fast I
2
C mode (400 kHz).
●
●
●
●
●
●
Parallel-bus/I
2
C protocol converter
Multi-master capability
7-bit/10-bit addressing
Transmitter/receiver flag
End-of-byte transmission flag
Transfer problem detection
I
2
C master features:
●
●
●
●
●
●
●
Clock generation
I
2
C bus busy flag
Arbitration lost flag
End of byte transmission flag
Transmitter/receiver Flag
Start bit detection flag
Start and stop generation
●
●
●
●
●
●
●
I
2
C slave features:
Stop bit detection
I
2
C bus busy flag
Detection of misplaced start or stop condition
Programmable I
2
C address detection
Transfer problem detection
End-of-byte transmission flag
Transmitter/Receiver flag
In addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa, using either an interrupt or polled handshake. The interrupts are enabled or disabled by software. The interface is connected to the I
2
C bus by a data pin
(SDAI) and by a clock pin (SCLI). It can be connected both with a standard I
2
C bus and a
Fast I
2
C bus. This selection is made by software.
108/188 Doc ID 13562 Rev 3
ST7LITE49M On-chip peripherals
Mode selection
●
●
The interface can operate in the four following modes:
Slave transmitter/receiver
Master transmitter/receiver
By default, it operates in slave mode.
The interface automatically switches from slave to master after it generates a START condition and from master to slave in case of arbitration loss or a STOP generation, allowing then Multi-Master capability.
Communication flow
In Master mode, it initiates a data transfer and generates the clock signal. A serial data transfer always begins with a start condition and ends with a stop condition. Both start and stop conditions are generated in master mode by software.
In Slave mode, the interface is capable of recognizing its own address (7 or 10-bit), and the general call address. The general call address detection may be enabled or disabled by software.
Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the start condition contain the address (one in 7-bit mode, two in 10-bit mode). The address is always transmitted in Master mode.
A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. Refer to
Figure 55.
I
2
C bus protocol
SDA
MSB ACK
SCL
1 2 8 9
START
CONDITION
STOP
CONDITION
Acknowledge may be enabled and disabled by software.
The I
2
C interface address and/or general call address can be selected by software.
The speed of the I
2
C interface may be selected between Standard (up to 100 kHz) and Fast
I
2
C (up to 400 kHz).
SDA/SCL line control
Transmitter mode: the interface holds the clock line low before transmission to wait for the microcontroller to write the byte in the data register.
Receiver mode: the interface holds the clock line low after reception to wait for the microcontroller to read the byte in the data register.
The SCL frequency (F scl
) is controlled by a programmable clock divider which depends on the I
2
C bus mode.
Doc ID 13562 Rev 3 109/188
On-chip peripherals ST7LITE49M
When the I
2
C cell is enabled, the SDA and SCL ports must be configured as floating inputs.
In this case, the value of the external pull-up resistor used depends on the application.
When the I
2
C cell is disabled, the SDA and SCL ports revert to being standard I/O port pins.
Figure 56.
I
2
C interface block diagram
DATA REGISTER (DR)
SDA or SDAI DATA CONTROL
DATA SHIFT REGISTER
COMPARATOR
OWN ADDRESS REGISTER 1 (OAR1)
OWN ADDRESS REGISTER 2 (OAR2)
SCL or SCLI
CLOCK CONTROL
CLOCK CONTROL REGISTER (CCR)
CONTROL REGISTER (CR)
STATUS REGISTER 1 (SR1)
STATUS REGISTER 2 (SR2)
CONTROL LOGIC
INTERRUPT
110/188 Doc ID 13562 Rev 3
ST7LITE49M On-chip peripherals
Refer to the CR, SR1 and SR2 registers in Section 11.4.7
. for the bit definitions.
By default the I
2
C interface operates in Slave mode (M/SL bit is cleared) except when it initiates a transmit or receive sequence.
First the interface frequency must be configured using the FRi bits in the OAR2 register.
Slave mode
Note:
As soon as a start condition is detected, the address is received from the SDA line and sent to the shift register; then it is compared with the address of the interface or the general call address (if selected by software).
●
●
In 10-bit addressing mode, the comparison includes the header sequence (11110xx0) and the two most significant bits of the address.
● Header matched the ACK bit is set.
(10-bit mode only): the interface generates an acknowledge pulse if
Address not matched
Address matched
: the interface ignores it and waits for another Start condition.
: the interface generates in sequence:
– Acknowledge pulse if the ACK bit is set.
– EVF and ADSL bits are set with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 register, holding the SCL line low (see
transfer sequencing EV1).
Next, in 7-bit mode read the DR register to determine from the least significant bit (data direction bit) if the slave must enter Receiver or Transmitter mode.
In 10-bit mode, after receiving the address sequence the slave is always in receive mode. It will enter transmit mode on receiving a repeated Start condition followed by the header sequence with matching address bits and the least significant bit set (11110xx1).
Slave receiver
●
●
Following the address reception and after SR1 register has been read, the slave receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence:
Acknowledge pulse if the ACK bit is set
EVF and BTF bits are set with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 register followed by a read of the DR register, holding the SCL line low
(see Figure 57 Transfer sequencing EV2).
Slave transmitter
Following the address reception and after SR1 register has been read, the slave sends bytes from the DR register to the SDA line via the internal shift register.
The slave waits for a read of the SR1 register followed by a write in the DR register, holding the SCL line low
Transfer sequencing EV3).
When the acknowledge pulse is received the EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set.
Doc ID 13562 Rev 3 111/188
On-chip peripherals
Note:
ST7LITE49M
Closing slave communication
After the last data byte is transferred a stop condition is generated by the master. The interface detects this condition and sets:
EVF and STOPF bits with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR2 register (see
Transfer sequencing
EV4).
Error cases
●
●
BERR : Detection of a Stop or a Start condition during a byte transfer. In this case, the
EVF and the BERR bits are set with an interrupt if the ITE bit is set.
If it is a Stop then the interface discards the data, released the lines and waits for another Start condition.
If it is a Start then the interface discards the data and waits for the next slave address on the bus.
AF : Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set with an interrupt if the ITE bit is set.
The AF bit is cleared by reading the I2CSR2 register. However, if read before the completion of the transmission, the AF flag will be set again, thus possibly generating a new interrupt. Software must ensure either that the SCL line is back at 0 before reading the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse of a transmitted byte.
In both cases, SCL line is not held low; however, the SDA line can remain low if the last bits transmitted are all 0. It is then necessary to release both lines by software. The SCL line is not held low while AF=1 but by other flags (SB or BTF) that are set at the same time.
How to release the SDA / SCL lines
Set and subsequently clear the STOP bit while BTF is set. The SDA/SCL lines are released after the transfer of the current byte.
SMBus compatibility
ST7 I
2
C is compatible with SMBus V1.1 protocol. It supports all SMBus addressing modes,
SMBus bus protocols and CRC-8 packet error checking. Refer to AN1713: SMBus Slave
Driver For ST7 I
2
C Peripheral.
112/188 Doc ID 13562 Rev 3
ST7LITE49M On-chip peripherals
Master mode
To switch from default Slave mode to Master mode a Start condition generation is needed.
Note:
Note:
Start condition
Setting the START bit while the BUSY bit is cleared causes the interface to switch to Master mode (M/SL bit set) and generates a Start condition.
Once the Start condition is sent, the EVF and SB bits are set by hardware with an interrupt if the ITE bit is set.
The master then waits for a read of the SR1 register followed by a write in the DR register with the Slave address, holding the SCL line low (see
EV5).
Slave address transmission
1.
The slave address is then sent to the SDA line via the internal shift register.
– In 7-bit addressing mode, one address byte is sent.
– In 10-bit addressing mode, sending the first byte including the header sequence causes the following event. The EVF bit is set by hardware with interrupt generation if the ITE bit is set.
2. The master then waits for a read of the SR1 register followed by a write in the DR register, holding the SCL line low (see
transfer sequencing EV9).
3. Then the second address byte is sent by the interface.
4. After completion of this transfer (and acknowledge from the slave if the ACK bit is set), the EVF bit is set by hardware with interrupt generation if the ITE bit is set.
5. The master waits for a read of the SR1 register followed by a write in the CR register
(for example set PE bit), holding the SCL line low
transfer sequencing
EV6).
6. Next the master must enter receiver or transmitter mode.
In 10-bit addressing mode, to switch the master to receiver mode, software must generate a repeated Start condition and resend the header sequence with the least significant bit set
(11110xx1).
Master receiver
●
●
Following the address transmission and after SR1 and CR registers have been accessed, the master receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence:
Acknowledge pulse if the ACK bit is set
EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 register followed by a read of the DR register, holding the SCL line low
(see Figure 57 transfer sequencing EV7).
To close the communication: before reading the last byte from the DR register, set the STOP bit to generate the Stop condition. The interface goes automatically back to slave mode
(M/SL bit cleared).
In order to generate the non-acknowledge pulse after the last received data byte, the ACK bit must be cleared just before reading the second last data byte.
Doc ID 13562 Rev 3 113/188
On-chip peripherals
Note:
ST7LITE49M
Master transmitter
Following the address transmission and after SR1 register has been read, the master sends bytes from the DR register to the SDA line via the internal shift register.
The master waits for a read of the SR1 register followed by a write in the DR register, holding the SCL line low
(see Figure 57 Transfer sequencing EV8).
When the acknowledge bit is received, the interface sets EVF and BTF bits with an interrupt if the ITE bit is set.
To close the communication: after writing the last byte to the DR register, set the STOP bit to generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit cleared).
Error cases
●
●
●
BERR : Detection of a Stop or a Start condition during a byte transfer. In this case, the
EVF and BERR bits are set by hardware with an interrupt if ITE is set.
Note that BERR will not be set if an error is detected during the first pulse of each 9-bit transaction:
Single Master mode
If a Start or Stop is issued during the first pulse of a 9-bit transaction, the BERR flag will not be set and transfer will continue however the BUSY flag will be reset. To work around this, slave devices should issue a NACK when they receive a misplaced Start or
Stop. The reception of a NACK or BUSY by the master in the middle of communication gives the possibility to reinitiate transmission.
Multimaster mode
Normally the BERR bit would be set whenever unauthorized transmission takes place while transfer is already in progress. However, an issue will arise if an external master generates an unauthorized Start or Stop while the I
2
C master is on the first pulse of a
9-bit transaction. It is possible to work around this by polling the BUSY bit during I
2
C master mode transmission. The resetting of the BUSY bit can then be handled in a similar manner as the BERR flag being set.
AF : Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set by hardware with an interrupt if the ITE bit is set. To resume, set the Start or Stop bit.
The AF bit is cleared by reading the I2CSR2 register. However, if read before the completion of the transmission, the AF flag will be set again, thus possibly generating a new interrupt. Software must ensure either that the SCL line is back at 0 before reading the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse of a transmitted byte.
ARLO: Detection of an arbitration lost condition.
In this case the ARLO bit is set by hardware (with an interrupt if the ITE bit is set and the interface goes automatically back to slave mode (the M/SL bit is cleared).
In all these cases, the SCL line is not held low; however, the SDA line can remain low if the last bits transmitted are all 0. It is then necessary to release both lines by software. The SCL line is not held low while AF=1 but by other flags (SB or BTF) that are set at the same time.
114/188 Doc ID 13562 Rev 3
ST7LITE49M On-chip peripherals
Figure 57.
Transfer sequencing
7-bit slave receiver
S Address A
EV1
Data1 A
EV2
Data2 A
EV2
.....
DataN A
EV2
P
EV4
7-bit slave transmitter
S Address A
EV1 EV3
Data1 A
EV3
Data2 A
EV3
....
.
Data
N
NA
EV3-
1
P
EV4
7-bit master receiver
S Address A
EV5 EV6
Data1 A
EV7
Data2 A
EV7
....
.
DataN NA
EV7
P
7-bit master transmitter
S
EV5
Address A
EV6 EV8
Data1 A
EV8
Data2 A
EV8
....
.
Data
N
A
EV8
P
10-bit slave receiver
S Header A Address A
EV1
Data1 A
EV2
.....
DataN A P
EV2 EV4
10-bit slave transmitter
S r
Header A
EV1 EV3
Data1 A
EV3
...
Data
N
A
EV3-
1
P
EV4
10-bit master transmitter
S Header A Address A
EV5 EV9 EV6 EV8
Data1 A
EV8
....
DataN A
EV8
P
10-bit master receiver
S r
EV5
Header A
EV6
Data1 A
EV7
.....
DataN A
EV7
P
1.
S=Start, S r if ITE=1).
= Repeated Start, P=Stop, A=Acknowledge, NA=Non-acknowledge, EVx=Event (with interrupt
2.
EV1: EVF=1, ADSL=1, cleared by reading SR1 register.
3.
EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
4.
EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
5.
EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading SR1 register. BTF is cleared by releasing the lines
(STOP=1, STOP=0) or by writing DR register (DR=FFh). If lines are released by STOP=1, STOP=0, the
Doc ID 13562 Rev 3 115/188
On-chip peripherals ST7LITE49M subsequent EV4 is not seen.
6.
EV4: EVF=1, STOPF=1, cleared by reading SR2 register.
7.
EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register.
8.
EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1).
9.
EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
10.
EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
11.
EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register.
11.4.5 Low power modes
Table 42.
Effect of low power modes on the I
2
C interface
Mode Description
Wait
Halt
No effect on I
2
C interface.
I
2
C interrupts cause the device to exit from Wait mode.
I
2
C registers are frozen.
In Halt mode, the I
2
C interface is inactive and does not acknowledge data on the bus. The
I
2
C interface resumes operation when the MCU is woken up by an interrupt with “exit from
Halt mode” capability.
11.4.6 Interrupts
Figure 58.
Event flags and interrupt generation
ADD10
BTF
ADSL
SB
AF
STOPF
ARLO
BERR
*
ITE
*
EVF can also be set by EV6 or an error from the SR2 register.
INTERRUPT
EVF
Table 43.
Description of interrupt events
Interrupt event
(1)
Event flag
Enable control bit
Exit from
Wait
Exit from
Halt
10-bit address sent event (Master mode)
End of byte transfer event
Address matched event (Slave mode)
Start bit generation event (Master mode)
ADD10
BTF
ADSL
SB
Yes
Yes
Yes
Yes
ITE
Acknowledge failure event
Stop detection event (Slave mode)
AF
STOPF
Yes
Yes
No
No
Arbitration lost event (Multimaster configuration) ARLO Yes No
Bus error event BERR Yes No
1.
The I
2
C interrupt events are connected to the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding Enable Control Bit is set and the I-bit in the CC register is reset (RIM instruction).
No
No
No
No
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ST7LITE49M On-chip peripherals
Note:
Note:
I
2
C control register (I2CCR)
Reset value: 0000 0000 (00h)
7
0 0 PE ENGC START
Read / Write
ACK STOP
0
ITE
Bits 7:6 = Reserved. Forced to 0 by hardware.
Bit 5 = PE Peripheral Enable bit
This bit is set and cleared by software.
0: Peripheral disabled
1: Master/Slave capability
When PE=0, all the bits of the CR register and the SR register except the Stop bit are reset.
All outputs are released while PE=0
When PE=1, the corresponding I/O pins are selected by hardware as alternate functions.
To enable the I
2
C interface, write the CR register TWICE with PE=1 as the first write only activates the interface (only PE is set).
Bit 4 = ENGC Enable general call bit
This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0). The 00h General Call address is acknowledged (01h ignored).
0: General Call disabled
1: General Call enabled
In accordance with the I
2
C standard, when GCAL addressing is enabled, an I
2
C slave can only receive data. It will not transmit data to the master.
Bit 3 = START Generation of a Start condition bit . This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0) or when the Start condition is sent (with interrupt generation if ITE=1).
● In master mode:
0: No start generation
●
1: Repeated start generation
In slave mode:
0: No start generation
1: Start generation when the bus is free
Bit 2 = ACK Acknowledge enable bit
This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0).
0: No acknowledge returned
1: Acknowledge returned after an address byte or a data byte is received
Doc ID 13562 Rev 3 117/188
On-chip peripherals ST7LITE49M
Bit 1 = STOP Generation of a Stop condition bit
This bit is set and cleared by software. It is also cleared by hardware in master mode.
Note: This bit is not cleared when the interface is disabled (PE=0).
● In master mode:
0: No stop generation
●
1: Stop generation after the current byte transfer or after the current Start condition is sent. The STOP bit is cleared by hardware when the Stop condition is sent.
In slave mode:
0: No stop generation
1: Release the SCL and SDA lines after the current byte transfer (BTF=1). In this mode the STOP bit has to be cleared by software.
Bit 0 = ITE Interrupt enable bit
This bit is set and cleared by software and cleared by hardware when the interface is disabled (PE=0).
0: Interrupts disabled
1: Interrupts enabled
Refer to
for the relationship between the events and the interrupt.
SCL is held low when the ADD10, SB, BTF or ADSL flags or an EV6 event (See
) is detected.
118/188 Doc ID 13562 Rev 3
ST7LITE49M On-chip peripherals
I
2
C status register 1 (I2CSR1)
Reset value: 0000 0000 (00h)
7
EVF ADD10 TRA BUSY BTF
Read Only
ADSL M/SL
0
SB
Bit 7 = EVF Event flag
This bit is set by hardware as soon as an event occurs. It is cleared by software reading
SR2 register in case of error event or as described in Figure 57
. It is also cleared by hardware when the interface is disabled (PE=0).
0: No event
1: One of the following events has occurred:
– BTF=1 (byte received or transmitted)
– ADSL=1 (Address matched in Slave mode while ACK=1)
– SB=1 (Start condition generated in Master mode)
– AF=1 (No acknowledge received after byte transmission)
– STOPF=1 (Stop condition detected in Slave mode)
– ARLO=1 (Arbitration lost in Master mode)
– BERR=1 (Bus error, misplaced Start or Stop condition detected)
– ADD10=1 (Master has sent header byte)
– Address byte successfully transmitted in Master mode.
Bit 6 = ADD10 10-bit addressing in Master mode
This bit is set by hardware when the master has sent the first byte in 10-bit address mode. It is cleared by software reading SR2 register followed by a write in the DR register of the second address byte. It is also cleared by hardware when the peripheral is disabled (PE=0).
0: No ADD10 event occurred.
1: Master has sent first address byte (header)
Bit 5 = TRA Transmitter/Receiver bit
When BTF is set, TRA=1 if a data byte has been transmitted. It is cleared automatically when BTF is cleared. It is also cleared by hardware after detection of Stop condition
(STOPF=1), loss of bus arbitration (ARLO=1) or when the interface is disabled (PE=0).
0: Data byte received (if BTF=1)
1: Data byte transmitted
Bit 4 = BUSY Bus busy bit
This bit is set by hardware on detection of a Start condition and cleared by hardware on detection of a Stop condition. It indicates a communication in progress on the bus. The
BUSY flag of the I2CSR1 register is cleared if a Bus Error occurs.
0: No communication on the bus
1: Communication ongoing on the bus
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On-chip peripherals ST7LITE49M
Bit 3 = BTF Byte transfer finished bit
This bit is set by hardware as soon as a byte is correctly received or transmitted with interrupt generation if ITE=1. It is cleared by software reading SR1 register followed by a read or write of DR register. It is also cleared by hardware when the interface is disabled (PE=0).
– Following a byte transmission, this bit is set after reception of the acknowledge clock pulse. In case an address byte is sent, this bit is set only after the EV6 event
(See
Figure 57 ). BTF is cleared by reading SR1 register followed by writing the
next byte in DR register.
– Following a byte reception, this bit is set after transmission of the acknowledge clock pulse if ACK=1. BTF is cleared by reading SR1 register followed by reading the byte from DR register.
The SCL line is held low while BTF=1.
0: byte transfer not done
1: byte transfer succeeded
Bit 2 = ADSL Address matched bit (slave mode).
This bit is set by hardware as soon as the received slave address matched with the
OAR register content or a general call is recognized. An interrupt is generated if ITE=1.
It is cleared by software reading SR1 register or by hardware when the interface is disabled (PE=0).
The SCL line is held low while ADSL=1.
0: Address mismatched or not received
1: Received address matched
Bit 1 = M/SL Master/Slave bit
This bit is set by hardware as soon as the interface is in Master mode (writing
START=1). It is cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration (ARLO=1). It is also cleared when the interface is disabled (PE=0).
0: Slave mode
1: Master mode
Bit 0 = SB Start bit (master mode).
This bit is set by hardware as soon as the Start condition is generated (following a write
START=1). An interrupt is generated if ITE=1. It is cleared by software reading SR1 register followed by writing the address byte in DR register. It is also cleared by hardware when the interface is disabled (PE=0).
0: No Start condition
1: Start condition generated
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ST7LITE49M
Note:
On-chip peripherals
I
2
C status register 2 (I2CSR2)
Reset value: 0000 0000 (00h)
7
0 0 0 AF STOPF
Read Only
ARLO BERR
0
GCAL
Bits 7:5 = Reserved. Forced to 0 by hardware.
Bit 4 = AF Acknowledge failure bit
This bit is set by hardware when no acknowledge is returned. An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0).
The SCL line is not held low while AF=1 but by other flags (SB or BTF) that are set at the same time.
0: No acknowledge failure
1: Acknowledge failure
Bit 3 = STOPF Stop detection bit (slave mode)
This bit is set by hardware when a Stop condition is detected on the bus after an acknowledge (if ACK=1). An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0).
The SCL line is not held low while STOPF=1.
0: No Stop condition detected
1: Stop condition detected
Bit 2 = ARLO Arbitration lost bit
This bit is set by hardware when the interface loses the arbitration of the bus to another master. An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0).
After an ARLO event the interface switches back automatically to Slave mode
(M/SL=0).
The SCL line is not held low while ARLO=1.
0: No arbitration lost detected
1: Arbitration lost detected
In a Multimaster environment, when the interface is configured in master receive mode it does not perform arbitration during the reception of the Acknowledge Bit. Mishandling of the
ARLO bit from the I2CSR2 register may occur when a second master simultaneously requests the same data from the same slave and the I
2
C master does not acknowledge the data. The ARLO bit is then left at 0 instead of being set.
Bit 1 = BERR Bus error bit
This bit is set by hardware when the interface detects a misplaced Start or Stop condition. An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0).
The SCL line is not held low while BERR=1.
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
Doc ID 13562 Rev 3 121/188
On-chip peripherals
Note:
ST7LITE49M
If a bus error occurs, a Stop or a repeated Start condition should be generated by the
Master to re-synchronize communication, get the transmission acknowledged and the bus released for further communication
Bit 0 = GCAL General Call bit (slave mode).
This bit is set by hardware when a general call address is detected on the bus while
ENGC=1. It is cleared by hardware detecting a Stop condition (STOPF=1) or when the interface is disabled (PE=0).
0: No general call address detected on bus
1: general call address detected on bus
Note:
I
2
C clock control register (I2CCCR)
Reset value: 0000 0000 (00h)
7
FM/SM CC6 CC5 CC4 CC3 CC2 CC1
0
CC0
Read / Write
Bit 7 = FM/SM Fast/Standard I
2
C mode bit
This bit is set and cleared by software. It is not cleared when the interface is disabled
(PE=0).
0: Standard I
2
C mode
1: Fast I
2
C mode
Bits 6:0 = CC[6:0] 7-bit clock divider bits
These bits select the speed of the bus (F
SCL
) depending on the I cleared when the interface is disabled (PE=0).
2
C mode. They are not
Refer to the Electrical Characteristics section for the table of values.
The programmed F
SCL
assumes no load on SCL and SDA lines.
I
2
C data register (I2CDR)
Reset value: 0000 0000 (00h)
7
D7 D6 D5 D2 D1
0
D0 D4 D3
Read / Write
Bits 7:0 = D[7:0] 8-bit data register
These bits contain the byte to be received or transmitted on the bus.
– Transmitter mode: byte transmission start automatically when the software writes in the DR register.
– Receiver mode: the first data byte is received automatically in the DR register using the least significant bit of the address. Then, the following data bytes are received one by one after reading the DR register.
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ST7LITE49M
Note:
On-chip peripherals
I
2
C own address register (I2COAR1)
Reset value: 0000 0000 (00h)
7
ADD7 ADD6 ADD5 ADD4 ADD3
Read / Write
ADD2 ADD1
0
ADD0
● In 7-bit addressing mode
Bits 7:1 = ADD[7:1] Interface address . These bits define the I
2
C bus address of the interface. They are not cleared when the interface is disabled (PE=0).
Bit 0 = ADD0 Address direction bit.
This bit is don’t care, the interface acknowledges either 0 or 1. It is not cleared when the interface is disabled (PE=0).
Address 01h is always ignored.
● In 10-bit addressing mode
Bits 7:0 = ADD[7:0] Interface address . These are the least significant bits of the I
2
C bus address of the interface. They are not cleared when the interface is disabled
(PE=0).
I
2
C own address register (I2COAR2)
Reset value: 0100 0000 (40h)
7
FR1 FR0 0 0
Read / Write
0 ADD9 ADD8
0
0
Bits 7:6 = FR[1:0] Frequency bits
These bits are set by software only when the interface is disabled (PE=0). To configure the interface to I
2
C specified delays select the value corresponding to the microcontroller frequency f
CPU
.
Table 44.
Configuration of I
2
C delay times f
CPU
< 6 MHz
6 to 8 MHz
FR1
0
0
FR0
0
1
Bits 5:3 = Reserved
Bits 2:1 = ADD[9:8] Interface address
These are the most significant bits of the I
2
C bus address of the interface (10-bit mode only). They are not cleared when the interface is disabled (PE=0).
Bit 0 = Reserved.
Doc ID 13562 Rev 3 123/188
On-chip peripherals
Table 45.
I
2
C register mapping and reset values
Address
(Hex.)
Register label
7 6 5
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
I2CCR
Reset value
I2CSR1
Reset value
I2CSR2
Reset value
I2CCCR
Reset value
I2COAR1
Reset value
I2COAR2
Reset value
I2CDR
Reset value
0
EVF
0
0
FM/SM
0
ADD7
0
FR1
0
MSB
0
0
ADD10
0
0
CC6
0
ADD6
0
FR0
1
0
PE
0
TRA
0
0
CC5
0
ADD5
0
0
0
4
ENGC
0
BUSY
0
AF
0
CC4
0
ADD4
0
0
0
3
START
0
BTF
0
STOPF
0
CC3
0
ADD3
0
0
0
2
ACK
0
ADSL
0
ARLO
0
CC2
0
ADD2
0
ADD9
0
0
1
STOP
0
M/SL
0
BERR
0
CC1
0
ADD1
0
ADD8
0
0
ST7LITE49M
0
0
LSB
0
ITE
0
SB
0
GCAL
0
CC0
0
ADD0
0
124/188 Doc ID 13562 Rev 3
ST7LITE49M On-chip peripherals
11.5 10-bit A/D converter (ADC)
11.5.1 Introduction
The on-chip analog to digital converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has up to 10 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 10 different sources.
The result of the conversion is stored in a 10-bit data register. The A/D converter is controlled through a control/status register.
●
●
●
●
●
●
10-bit conversion
Up to 10 channels with multiplexed input
Linear successive approximation
Data register (DR) which contains the results
Conversion complete status flag
On/off bit (to reduce consumption)
The block diagram is shown in
Analog power supply
V
DDA
and V
SSA
are the high and low level reference voltage pins. In some devices (refer to device pin out description) they are internally connected to the V
DD
and V
SS
pins.
Conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines.
Doc ID 13562 Rev 3 125/188
On-chip peripherals
Figure 59.
ADC block diagram f
CPU
DIV 2
AIN0
AIN1
AINx
0
1
DIV 4
ST7LITE49M
1
0
SLOW bit f
ADC
EOC SPEED ADON 0 CH3 CH2 CH1 CH0 ADCCSR
4
HOLD CONTROL
R
ADC
ANALOG
MUX
ANALOG TO DIGITAL
CONVERTER
C
ADC
ADCDRH D9 D8 D7 D6 D5 D4 D3 D2
ADCDRL
0 0 0 0 SLOW 0 D1 D0
Digital A/D conversion result
The conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not.
If the input voltage (V
AIN
) is greater than V
DDA
(high-level voltage reference) then the conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without overflow indication).
If the input voltage (V
AIN
) is lower than V
SSA
(low-level voltage reference) then the conversion result in the ADCDRH and ADCDRL registers is 00 00h.
The A/D converter is linear and the digital result of the conversion is stored in the ADCDRH and ADCDRL registers. The accuracy of the conversion is described in the Electrical
Characteristics section.
R
AIN
is the maximum recommended impedance for an analog input signal. If the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time.
126/188 Doc ID 13562 Rev 3
ST7LITE49M On-chip peripherals
Configuring the A/D conversion
The analog input ports must be configured as input, no pull-up, no interrupt (see Section 10:
I/O ports ). Using these pins as analog inputs does not affect the ability of the port to be read
as a logic input.
To assign the analog channel to convert, select the CH[2:0] bits in the ADCCSR register.
Set the ADON bit to enable the A/D converter and to start the conversion. From this time on, the ADC performs a continuous conversion of the selected channel.
●
●
When a conversion is complete:
The EOC bit is set by hardware.
The result is in the ADCDR registers.
A read to the ADCDRH or a write to any bit of the ADCCSR register resets the EOC bit.
To read the 10 bits, perform the following steps:
1.
Poll the EOC bit
3. Read ADCDRH. This clears EOC automatically.
To read only 8 bits, perform the following steps:
1.
Poll EOC bit
2. Read ADCDRH. This clears EOC automatically.
Changing the conversion channel
The application can change channels during conversion. When software modifies the
CH[3:0] bits in the ADCCSR register, the current conversion is stopped, the EOC bit is cleared, and the A/D converter starts converting the newly selected channel.
11.5.4 Low power modes
The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced power consumption when no conversion is needed and between single shot conversions.
Table 46.
Effect of low power modes on the A/D converter
Mode Description
Wait
Halt
No effect on A/D converter
A/D Converter disabled.
After wakeup from Halt mode, the A/D Converter requires a stabilization time t
STAB
(see Electrical Characteristics) before accurate conversions can be performed.
11.5.5 Interrupts
None.
Doc ID 13562 Rev 3 127/188
On-chip peripherals ST7LITE49M
Control/status register (ADCCSR)
Reset value: 0000 0000 (00h)
7
EOC
Read only
SPEED ADON 0 CH3
Read/write
CH2 CH1
0
CH0
Bit 7 = EOC End of conversion bit
This bit is set by hardware. It is cleared by hardware when software reads the ADCDRH register or writes to any bit of the ADCCSR register.
0: Conversion is not complete
1: Conversion complete
Bit 6 = SPEED ADC clock selection bit
This bit is set and cleared by software. It is used together with the SLOW bit to configure the ADC clock speed. Refer to the table in the SLOW bit description
(ADCDRL register).
Bit 5 = ADON A/D converter ON bit
This bit is set and cleared by software.
0: A/D converter is switched off
1: A/D converter is switched on
Bit 4 = Reserved , must be kept cleared.
Bits 3:0 = CH[3:0] Channel selection
These bits select the analog input to convert. They are set and cleared by software.
Table 47.
Channel selection using CH[3:0]
Channel pin
(1)
CH3 CH2 CH1
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
0
0
0
0
0
0
0
0
1
1
1.
The number of channels is device dependent. Refer to the device pinout description.
0
1
1
0
0
0
1
1
0
0
1
0
0
0
0
1
1
1
0
0
CH0
1
0
1
0
1
0
0
1
0
1
128/188 Doc ID 13562 Rev 3
ST7LITE49M On-chip peripherals
Data register high (ADCDRH)
Reset value: xxxx xxxx (xxh)
7
D9 D8 D7 D6
Read only
D5
Bits 7:0 = D[9:2] MSB of analog converted value
ADC control/data register low (ADCDRL)
Reset value: 0000 00xx (0xh)
D4 D3
0
D2
7
0 0 0 0 SLOW
Read/write
D1
0
D0
Bits 7:4 = Reserved. Forced by hardware to 0.
Bit 3 = SLOW Slow mode bit
This bit is set and cleared by software. It is used together with the SPEED bit in the
ADCCSR register to configure the ADC clock speed as shown on the table below.
Table 48.
Configuring the ADC clock speed f
ADC
(1) f
CPU
/2 f
CPU f
CPU
/4
1.
The maximum allowed value of f
ADC is 4 MHz (see
)
Bit 2 = Reserved. Forced by hardware to 0.
Bits 1:0 = D[1:0] LSB of analog converted value
SLOW
0
0
1
SPEED
0
1 x
Table 49.
ADC register mapping and reset values
Address
(Hex.)
Register label
7 6 5 4
0036h
0037h
0038h
ADCCSR
Reset value
ADCDRH
Reset value
ADCDRL
Reset value
EOC
0
D9 x
0
0
SPEED
0
ADON
0
D8 x
0
0
D7 x
0
0
0
0
D6 x
0
3
0
CH3
0
D5 x
SLOW
0
2
CH2
0
D4 x
0
1
CH1
0
D3 x
D1 x
0
CH0
0
D2 x
D0 x
Doc ID 13562 Rev 3 129/188
Instruction set ST7LITE49M
12.1 ST7 addressing modes
The ST7 core features 17 different addressing modes which can be classified in seven main groups:
Table 50.
Description of addressing modes
Addressing mode
Inherent
Immediate
Direct
Indexed
Indirect
Relative
Bit operation
Example nop ld A,#$55 ld A,$55 ld A,($55,X) ld A,([$55],X) jrne loop bset byte,#5
The ST7 instruction set is designed to minimize the number of bytes required per instruction: To do so, most of the addressing modes may be subdivided in two submodes called long and short:
● Long addressing mode is more powerful because it can use the full 64 Kbyte address space, however it uses more bytes and more CPU cycles.
● Short addressing mode is less powerful because it can generally only access page zero (0000h - 00FFh range), but the instruction size is more compact, and faster. All memory to memory instructions use short addressing modes only (CLR, CPL, NEG,
BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
The ST7 Assembler optimizes the use of long and short addressing modes.
Table 51.
ST7 addressing mode overview
Inherent
Immediate
Short
Long
No Offset
Short
Long
Short
Long
Short
Mode
Direct
Direct
Direct
Direct
Direct
Indirect
Indirect
Indirect
Indexed
Indexed
Syntax nop ld A,#$55 ld A,$10 ld A,$1000 ld A,(X) ld A,($10,X)
Destination/ source
00..FF
0000..FFFF
00..FF
Indexed ld A,($1000,X) 0000..FFFF
ld A,[$10] ld A,[$10.w]
Indexed ld A,([$10],X)
00..1FE
00..FF
0000..FFFF
00..1FE
Pointer address
00..FF
00..FF
00..FF
Pointer size byte word byte
Length
(bytes)
+ 0
+ 1
+ 1
+ 2
+ 0 (with X register)
+ 1 (with Y register)
+ 1
+ 2
+ 2
+ 2
+ 2
130/188 Doc ID 13562 Rev 3
ST7LITE49M Instruction set
Table 51.
ST7 addressing mode overview (continued)
Mode Syntax
Destination/ source
Long Indirect Indexed ld
A,([$10.w],X)
0000..FFFF
Relative
Relative
Bit
Bit
Bit
Bit
Direct
Indirect
Direct
Indirect
Direct
Indirect
Relative
Relative jrne loop jrne [$10] bset $10,#7 bset [$10],#7 btjt
$10,#7,skip btjt
[$10],#7,skip
PC-
128/PC+127
(1)
PC-
128/PC+127
(1)
00..FF
00..FF
00..FF
00..FF
Pointer address
00..FF
00..FF
00..FF
00..FF
Pointer size word byte byte byte
1.
At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx.
Length
(bytes)
+ 2
+ 1
+ 2
+ 1
+ 2
+ 2
+ 3
All Inherent instructions consist of a single byte. The opcode fully specifies all the required information for the CPU to process the operation.
Table 52.
Instructions supporting inherent addressing mode
Instruction Function
RCF
RSP
LD
CLR
PUSH/POP
INC/DEC
TNZ
CPL, NEG
NOP
TRAP
WFI
HALT
RET
IRET
SIM
RIM
SCF
No operation
S/W interrupt
Wait for interrupt (low power mode)
Halt oscillator (lowest power mode)
Subroutine return
Interrupt subroutine return
Set interrupt mask
Reset interrupt mask
Set carry flag
Reset carry flag
Reset stack pointer
Load
Clear
Push/Pop to/from the stack
Increment/decrement
Test negative or zero
1 or 2 complement
Doc ID 13562 Rev 3 131/188
Instruction set ST7LITE49M
Table 52.
Instructions supporting inherent addressing mode (continued)
Instruction Function
MUL
SLL, SRL, SRA, RLC, RRC
SWAP
Byte multiplication
Shift and rotate operations
Swap nibbles
Immediate instructions have 2 bytes, the first byte contains the opcode, the second byte contains the operand value.
Imm
Table 53.
Instructions supporting inherent immediate addressing mode
Immediate instruction Function
LD
CP
BCP
AND, OR, XOR
ADC, ADD, SUB, SBC
Load
Compare
Bit compare
Logical operations
Arithmetic operations
In Direct instructions, the operands are referenced by their memory address.
The direct addressing mode consists of two submodes:
Direct (short) addressing mode
The address is a byte, thus requires only 1 byte after the opcode, but only allows 00 - FF addressing space.
Direct (long) addressing mode
The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode.
12.1.4 Indexed modes (no offset, short, long)
In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset.
The indirect addressing mode consists of three submodes:
Indexed mode (no offset)
There is no offset (no extra byte after the opcode), and allows 00 - FF addressing space.
Indexed mode (short)
The offset is a byte, thus requires only 1 byte after the opcode and allows 00 - 1FE addressing space.
132/188 Doc ID 13562 Rev 3
ST7LITE49M Instruction set
Indexed mode (long)
The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode.
12.1.5 Indirect modes (short, long)
The required data byte to do the operation is found by its memory address, located in memory (pointer).
The pointer address follows the opcode. The indirect addressing mode consists of two submodes:
Indirect mode (short)
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode.
Indirect mode (long)
The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode.
12.1.6 Indirect indexed modes (short, long)
This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (X or Y) with a pointer value located in memory. The pointer address follows the opcode.
The indirect indexed addressing mode consists of two submodes:
Indirect indexed mode (short)
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing space, and requires 1 byte after the opcode.
Indirect indexed mode (long)
The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode.
Table 54.
Instructions supporting direct, indexed, indirect and indirect indexed addressing modes
Instructions Function
Long and short instructions
LD
CP
AND, OR, XOR
ADC, ADD, SUB, SBC
BCP
Load
Compare
Logical operations
Arithmetic addition/subtraction operations
Bit compare
Doc ID 13562 Rev 3 133/188
Instruction set ST7LITE49M
Table 54.
Instructions supporting direct, indexed, indirect and indirect indexed addressing modes (continued)
Instructions Function
Short instructions only
CLR
INC, DEC
TNZ
CPL, NEG
BSET, BRES
BTJT, BTJF
SLL, SRL, SRA, RLC, RRC
SWAP
CALL, JP
Clear
Increment/decrement
Test negative or zero
1 or 2 complement
Bit operations
Bit test and jump operations
Shift and rotate operations
Swap nibbles
Call or jump subroutine
12.1.7 Relative modes (direct, indirect)
This addressing mode is used to modify the PC register value by adding an 8-bit signed offset to it.
Table 55.
Instructions supporting relative modes
Available Relative Direct/Indirect instructions
JRxx
CALLR
The relative addressing mode consists of two submodes:
Function
Conditional jump
Call relative
Relative mode (direct)
The offset follows the opcode.
Relative mode (indirect)
The offset is defined in memory, of which the address follows the opcode.
134/188 Doc ID 13562 Rev 3
ST7LITE49M Instruction set
The ST7 family devices use an instruction set consisting of 63 instructions. The instructions may be subdivided into 13 main groups as illustrated in the following table:
Table 56.
ST7 instruction set
Instructions
Load and Transfer
Stack operation
Increment/decrement
Compare and tests
Logical operations
Bit operation
Conditional bit test and branch
Arithmetic operations
Shift and rotate
Unconditional jump or call
Conditional branch
LD CLR
PUSH POP RSP
INC
CP
DEC
TNZ BCP
AND OR
BSET BRES
XOR CPL NEG
BTJT BTJF
ADC ADD SUB SBC MUL
SLL
JRA
JRxx
SRL SRA RLC RRC SWAP SLA
JRT JRF JP CALL CALLR NOP RET
Interruption management TRAP WFI HALT IRET
Condition Code Flag modification SIM RIM SCF RCF
Using a prebyte
The instructions are described with 1 to 4 bytes.
In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes modify the meaning of the instruction they precede.
The whole instruction becomes by:
PC-2 End of previous instruction
PC-1 Prebyte
PC Opcode
PC+1 Additional word (0 to 2) according to the number of bytes required to compute the effective address
These prebytes enable instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are:
PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent addressing mode by a Y one.
PIX 92 Replace an instruction using direct, direct bit or direct relative addressing mode to an instruction using the corresponding indirect addressing mode.
It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode.
PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one.
Doc ID 13562 Rev 3 135/188
Instruction set ST7LITE49M
In order to provide enhanced robustness to the device against unexpected behavior, a system of illegal opcode detection is implemented: a reset is generated if the code to be executed does not correspond to any opcode or prebyte value. This, combined with the
Watchdog, allows the detection and recovery from an unexpected fault or interference.
A valid prebyte associated with a valid opcode forming an unauthorized combination does not generate a reset.
I
Table 57.
Illegal opcode detection
Mnemo Description Function/Example
JRA
JRT
JRF
JRIH
JRIL
JRH
JRNH
JRM
JRNM
JRMI
CPL
DEC
HALT
IRET
INC
JP
ADC
ADD
AND
BCP
BRES
BSET
BTJF
BTJT
CALL
Add with Carry
Addition
Logical And
Bit compare A, Memory
Bit reset
Bit Set
Jump if bit is false (0)
Jump if bit is true (1)
Call subroutine
CALLR Call subroutine relative
CLR Clear
CP Arithmetic compare
One Complement
Decrement
Halt
Interrupt routine return
Increment
Absolute jump
Jump relative always
Jump relative
Never jump
Jump if ext. interrupt = 1
Jump if ext. interrupt = 0
Jump if H = 1
Jump if H = 0
Jump if I = 1
Jump if I = 0
Jump if N = 1 (minus)
A = A + M + C
A = A + M
A = A . M tst (A . M) bres Byte, #3 bset Byte, #3 btjf Byte, #3, Jmp1 btjt Byte, #3, Jmp1 tst(Reg - M)
A = FFH-A dec Y
Pop CC, A, X, PC inc X jp [TBL.w] jrf *
H = 1 ?
H = 0 ?
I = 1 ?
I = 0 ?
N = 1 ?
Dst
M
M
M
M
A
A
A
A reg, M reg reg, M reg, M reg, M
Src
M
M
M
M
M
H
H
H
H
I
0
I
N
N
N
N
N
N
N
0
N
N
N
Z
Z
Z
Z
Z
Z
Z
1
Z
Z
Z
C
C
C
C
1
C
C
C
136/188 Doc ID 13562 Rev 3
ST7LITE49M
RRC
RSP
SBC
SCF
SIM
SLA
PUSH
RCF
RET
RIM
RLC
SLL
SRL
SRA
SUB
SWAP
TNZ
TRAP
Table 57.
Illegal opcode detection (continued)
Mnemo Description Function/Example
JRUGT
JRULE
LD
MUL
NEG
NOP
OR
POP
JRPL Jump if N = 0 (plus)
JREQ Jump if Z = 1 (equal)
JRNE Jump if Z = 0 (not equal)
JRC
JRNC
JRULT
JRUGE
Jump if C = 1
Jump if C = 0
Jump if C = 1
Jump if C = 0
Jump if (C + Z = 0)
Jump if (C + Z = 1)
Load
Multiply
Negate (2's compl)
No Operation
OR operation
Pop from the stack
N = 0 ?
Z = 1 ?
Z = 0 ?
C = 1 ?
C = 0 ?
Unsigned <
Jmp if unsigned >=
Unsigned >
Unsigned <= dst <= src
X,A = X * A neg $10
A = A + M pop reg pop CC push Y
C = 0
Push onto the stack
Reset carry flag
Subroutine Return
Enable Interrupts
Rotate left true C
Rotate right true C
Reset stack pointer
Subtract with carry
Set carry flag
Disable interrupts
Shift left arithmetic
Shift left logic
Shift right logic
Shift right arithmetic
Subtraction
SWAP nibbles
Test for neg & zero
S/W trap
Dst reg, M M, reg
A, X, Y X, Y, A reg, M
A reg
CC
M
I = 0
C <= Dst <= C
C => Dst => C
S = Max allowed
A = A - M - C reg, M reg, M
A
C = 1
I = 1
C <= Dst <= 0
C <= Dst <= 0
0 => Dst => C
Dst7 => Dst => C reg, M reg, M
A = A - M A
Dst[7..4]<=>Dst[3..0] reg, M tnz lbl1
S/W interrupt reg, M reg, M
Src
M
M
M reg, CC
M
M
Instruction set
H I N Z C
0
N Z
N Z
0
C
N Z
H I N Z C
0
0
N
N
Z
Z
C
C
1
N Z C
1
Z
Z
Z
Z
Z
Z
Z
N
N
N
0
N
N
N
C
C
C
C
C
1
Doc ID 13562 Rev 3 137/188
Instruction set
Table 57.
Illegal opcode detection (continued)
Mnemo Description Function/Example
WFI
XOR
Wait for interrupt
Exclusive OR A = A XOR M
Dst
A
Src
M
ST7LITE49M
H I
0
N Z C
N Z
138/188 Doc ID 13562 Rev 3
ST7LITE49M Electrical characteristics
Unless otherwise specified, all voltages are referred to V
SS
.
13.1.1 Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T
A
= 25 °C and T
A
= T
A max (given by the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3
Σ
).
Unless otherwise specified, typical data are based on T
4.5 V ≤ V
DD
A
= 25 °C, V
DD
≤ 5.5 V voltage range) and V
DD
= 3.3 V (for the 3.0 V ≤ V
DD
= 5 V (for the
≤ 3.6 V voltage range).
They are given only as design guidelines and are not tested.
Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.
The loading conditions used for pin parameter measurement are shown in Figure 60 .
Figure 60.
Pin loading conditions
ST7 PIN
C
L
13.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in
.
Doc ID 13562 Rev 3 139/188
Electrical characteristics
Figure 61.
Pin input voltage
ST7LITE49M
ST7 PIN
V
IN
13.2 Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Table 58.
Voltage characteristics
Symbol Ratings Maximum value Unit
V
V
V
DD
- V
V
IN
SS
ESD(HBM)
ESD(CDM)
Supply voltage
Input voltage on any pin
(1)(2)
Electrostatic discharge voltage (Human body model)
Electrostatic discharge voltage (Charge device model)
7.0
V
SS
-0.3 to V
DD
+0.3
V
1.
Directly connecting the RESET and I/O pins to V
DD
or V
SS could damage the device if an unintentional internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7 k
Ω
for RESET, 10 k
Ω
for I/Os). Unused I/O pins must be tied in the same way to V
DD
or V
SS
according to their reset configuration.
2.
I
INJ(PIN)
must never be exceeded. This is implicitly insured if V cannot be respected, the injection current must be limited externally to the I
INJ(PIN) injection is induced by V
IN
>V
DD
IN
maximum is respected. If V
while a negative injection is induced by V pads, there is no positive injection current, and the corresponding V
IN
IN
<V
SS
IN
maximum
value. A positive
. For true open-drain
maximum must always be respected
140/188 Doc ID 13562 Rev 3
ST7LITE49M Electrical characteristics
Table 59.
Current characteristics
Symbol
I
VDD
I
VSS
I
IO
Ratings
Total current into V
DD
power lines (source)
(1)
Total current out of V
SS
ground lines (sink)
(1)
Output current sunk by any standard I/O and control pin
Output current sunk by any high sink I/O pin
Maximum value
75
150
20
40
I
INJ(PIN)
(2)(3)
Σ I
INJ(PIN)
(2)
Output current source by any I/Os and control pin
Injected current on RESET pin
Injected current on OSC1/CLKIN and OSC2 pins
Injected current on any other pin
(4)
Total injected current (sum of all I/O and control pins)
(4)
- 25
± 5
± 5
± 5
± 20
Unit mA
1.
All power (V
DD
) and ground (V
SS
) lines must always be connected to the external supply.
2.
I
INJ(PIN)
must never be exceeded. This is implicitly insured if V cannot be respected, the injection current must be limited externally to the I
INJ(PIN) injection is induced by V
IN
>V
DD
IN
maximum is respected. If V
while a negative injection is induced by V pads, there is no positive injection current, and the corresponding V
IN
IN
<V
SS
IN
maximum
value. A positive
. For true open-drain
maximum must always be respected
3.
Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken:
- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage is lower than the specified limits)
- Pure digital pins must have a negative injection less than 1.6 mA. In addition, it is recommended to inject the current as far as possible from the analog input pins.
4.
When several inputs are submitted to a current injection, the maximum
Σ
I
INJ(PIN)
is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with
Σ
I
INJ(PIN)
maximum current injection on four I/O port pins of the device.
Table 60.
Thermal characteristics
Symbol Ratings Value Unit
T
STG
T
J
Storage temperature range -65 to +150 °C
Maximum junction temperature (see
Table 98: Thermal characteristics on page 184 )
Doc ID 13562 Rev 3 141/188
Electrical characteristics ST7LITE49M
13.3.1 General operating conditions
T
A
= -40 to +125 °C unless otherwise specified.
Table 61.
General operating conditions
Symbol Parameter Conditions Min Max Unit
V
DD f
CPU
Supply voltage
CPU clock frequency f
CPU
= 4 MHz max.
f
CPU
= 8 MHz max.
3.3 V ≤ V
DD
≤ 5.5 V
2.4 V ≤ V
DD
< 3.3 V
2.4
3.3
up to 8 up to 4
5.5
5.5
V
MHz
Figure 62.
f
CPU
maximum operating frequency versus V
DD supply voltage f
CPU
[MHz]
8
FUNCTIONALITY
GUARANTEED
IN THIS AREA
(UNLESS OTHERWISE
STATED IN THE
TABLES OF
PARAMETRIC DATA)
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
4
2
0
2.0
2.4
2.7
3.3
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE [V]
T
A
= -40 to 125 °C unless otherwise specified.
,
Table 62.
Operating characteristics with LVD
Symbol Parameter Conditions Min Typ Max Unit
V
IT+ (LVD)
Reset release threshold
(V
DD
rise)
High threshold
Med. threshold
Low threshold
3.9
3.2
2.5
4.2
3.5
2.7
4.5
3.8
3.0
V
V
IT(LVD)
Reset generation threshold
(V
DD
fall)
High threshold
Med. threshold
Low threshold
3.7
3.0
2.4
4.0
3.3
2.6
4.3
3.6
2.9
I
V
V hys tPOR
DD(LVD)
LVD voltage threshold hysteresis V
IT+ (LVD)
-V
IT(LVD)
V
DD
rise time rate
(1)(2)
LVD/AVD current consumption V
DD
= 5 V
2
150
80 140
1.
Not tested in production. The V
DD
rise time rate condition is needed to ensure a correct device power-on and LVD reset release. When the V
DD reset of the MCU.
slope is outside these values, the LVD may not release properly the mV
μ s/V
μ A
142/188 Doc ID 13562 Rev 3
ST7LITE49M Electrical characteristics
2.
Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the application, it is recommended to pull V
DD
circuit example in Figure 96 on page 169 .
down to 0 V to ensure optimum restart conditions. Refer to
13.3.3 Auxiliary voltage detector (AVD) thresholds
T
A
= -40 to 125 °C unless otherwise specified
,
Table 63.
Operating characteristics with AVD
(1)
Symbol Parameter Conditions
V
V
IT+ (AVD)
IT(AVD)
1=>0 AVDF flag toggle threshold (V
DD
rise)
0=>1 AVDF flag toggle threshold (V
DD
fall)
High threshold
Med. threshold
Low threshold
High threshold
Med. threshold
Low threshold
V hys
AVD voltage threshold hysteresis
V
IT+ (AVD)
1.
Refer to Section : Monitoring the VDD main supply .
2.
Not tested in production, guaranteed by characterization.
-V
IT(AVD)
Min
(2)
Typ
(2)
Max
(2)
Unit
4.0
3.4
2.6
3.9
3.3
2.5
4.4
3.7
2.9
4.3
3.6
2.8
4.8
4.1
3.2
4.7
4.0
3.1
V
150 mV
13.3.4 Voltage drop between AVD flag setting and LVD reset generation
Table 64. Voltage drop
Parameter Min
(1)
AVD med. threshold - AVD low threshold
AVD high threshold - AVD low threshold
AVD high threshold - AVD med. threshold
AVD low threshold - LVD low threshold
AVD med threshold - LVD low threshold
AVD med threshold - LVD med. threshold
AVD high threshold - LVD low threshold
AVD high threshold - LVD med. threshold
1.
Not tested in production, guaranteed by characterization.
800
1400
600
100
950
250
1600
900
Typ
(1)
850
1450
650
200
1050
300
1700
1000
Max
(1)
950
1550
750
250
1150
400
1800
1050
Unit mV
Doc ID 13562 Rev 3 143/188
Electrical characteristics ST7LITE49M
To improve clock stability and frequency accuracy, it is recommended to place a decoupling capacitor, typically 100 nF, between the V
DD
and V device
SS
pins as close as possible to the ST7
Internal RC oscillator calibrated at 5.0 V
The ST7 internal clock can be supplied by an internal RC oscillator (selectable by option byte).
Table 65.
Internal RC oscillator characteristics (5.0 V calibration)
Symbol Parameter Conditions Min Typ Max Unit f
RC
Internal RC oscillator frequency
RCCR = FF (reset value),
T
A
= 25 °C, V
DD
= 5 V
RCCR=RCCR0
T
A
= 25 °C, V
(1)
,
DD
= 5 V
7.84
5.5
8 8.16
MHz f
G(RC)
ACC
RC
RC trimming granularity
Accuracy of Internal
RC oscillator with
RCCR=RCCR0
1)
T
A
= 25 °C, V
DD
= 5 V
T
A
= 25 °C, V
DD
= 4.5 to 5.5 V
(2)
T
A
= 0 to +85 °C,
V
DD
= 4.5 to 5.5 V
(2)
T
A
= 0 to +125 °C,
V
DD
= 4.5 to 5.5 V
(2)
T
A
= -40 to 0 °C,
V
DD
= 4.5 to 5.5 V
(2)
-2
-2.5
-3
-4
6
2
4
6 kHz
%
%
%
2.5
% t su(RC)
RC oscillator setup time
T
A
= 25 °C, V
DD
= 5 V
1.
See
Section 7.1.1: Internal RC oscillator
2.
Tested in production at 5.0 V only
3.
Not tested in production
Internal RC oscillator calibrated at 3.3 V
4
(3) μ s
The ST7 internal clock can be supplied by an internal RC oscillator (selectable by option byte).
Table 66.
Internal RC oscillator characteristics (3.3 V calibration)
Symbol Parameter Conditions Min f
RC
Internal RC oscillator frequency
RCCR = FF (reset value),
T
A
=25 °C,V
DD
=3.3 V
RCCR = RCCR1
(1)
,
T
A
= 25 °C, V
DD
= 3.3 V
7.84
Typ
4.3
8
Max Unit
8.16
MHz
144/188 Doc ID 13562 Rev 3
ST7LITE49M Electrical characteristics
Table 66.
Internal RC oscillator characteristics (3.3 V calibration)
Symbol Parameter Conditions Min
ACC
RC
Accuracy of internal
RC oscillator with
RCCR=RCCR1
1)
V
DD
T
A
= 25 °C,
= 3.0 to 3.6 V
(2)
T
A
= 0 to +85 °C,
V
DD
= 3.0 to 3.6 V
T
A
= 0 to +125 °C,
V
DD
= 3.0 to 3.6 V
T
A
V
DD
= -40 to 0 °C,
= 3.0 to 3.6 V
-2
-2.5
-3
-4 t su(RC)
RC oscillator setup time
1.
See
Section 7.1.1: Internal RC oscillator
2.
Tested in production at 3.3 V only
T
A
= 25 °C, V
DD
= 3.3 V
Typ
4
Max Unit
2
4
6
2.5
%
%
%
%
μ s
Figure 63.
Frequency vs voltage at four different ambient temperatures (RC at 5 V)
8 .200
8 .160
8 .120
8 .080
8 .040
8 .000
7 .960
7 .920
7 .880
7 .840
7 .800
2
.4
2.
8
3.
2
3.
6
4
.0
4.
4
VDD (V)
4.
8
5.
2
5
.6
RC 5V@- 40 °C
RC 5V@25 °C
RC 5V@85 °C
RC 5V@12 5 °C
Figure 64.
Frequency vs voltage at four different ambient temperatures (RC at 3.3 V)
8 .240
8 .200
8 .160
8 .120
8 .080
8 .040
8 .000
7 .960
7 .920
7 .880
7 .840
2. 4 2.8
3 .2
3.6
4.0
VDD (V)
4 .4
4.8
5.2
5.6
R C3.3V@ -40 °C
R C3.3V@ 25 °C
R C3.3V@ 85 °C
R C3.3V@ 125 °C
Doc ID 13562 Rev 3 145/188
Electrical characteristics ST7LITE49M
Figure 65.
Accuracy in % vs voltage at 4 different ambient temperatures (RC at 5 V)
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
-1.4
-1.6
-1.8
-2.0
-2.2
2.2
2.0
1.8
1.6
1.4
1.2
1.0
R C5V% @-40 °C
R C5V% @25 °C
R C5V% @85 °C
R C5V% @12 5 °C
VDD (V)
Figure 66.
Accuracy in % vs voltage at 4 different ambient temperatures
(RC at 3.3 V)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
-1.4
3.0
2.8
2.6
2.4
2.2
2.0
1.8
RC 3.3V%@ -4 0 °C
RC 3.3C% @2 5 °C
RC 3.3V%@ 85 °C
RC 3.3V%@ 125 °C
VDD (V)
146/188 Doc ID 13562 Rev 3
ST7LITE49M Electrical characteristics
13.4 Supply current characteristics
The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total device consumption, the two current values must be added (except for Halt mode for which the clock is stopped).
T
A
= -40 to +125 °C unless otherwise specified.
Table 67.
Supply current characteristics
Symbol Parameter Conditions Typ Max Unit
4.5
(2)
I
DD
Supply current in Run mode
Supply current in Wait mode
(1)
(3)
Supply current in Slow mode
(4)
Supply current in Slow-wait mode
(5)
Supply current in AWUFH mode
(6)(7) f f f
CPU
= 4 MHz f
CPU
= 8 MHz f
CPU
= 4 MHz f
CPU
= 8 MHz
CPU
CPU
/32 = 250 kHz
/32 = 250 kHz
2.5
5.0
1.1
2
550
450
50
9.5
2
(2)
3.5
900
750
90
(2) mA
μ A
Supply current in Active-halt mode 120 200
I
DD
Supply current in Halt mode
Supply current in Run mode
Supply current in Wait mode
Supply current in Slow mode
(8)
(1)
(3)
(4)
Supply current in Slow-wait mode
Supply current in AWUFH mode
(5)
(6)(7)
Supply current in Active-halt mode f
CPU f
CPU
T
A
= 85 °C
T
A
= 125 f
CPU f
CPU
°C
= 4 MHz
= 4 MHz
/32 = 250 kHz
/32 = 250 kHz
0.5
5
0.5
1.4
5
2.5
(2)
600 900
(2)
300 500
(2)
250 450
(2)
20 40
(2)
80
0.5
120
(2)
5
(2) mA
μ
Supply current in Halt mode
(8)
T
A
= 85 °C
T
A
= 125 °C 0.5
5
1.
CPU running with memory access, all I/O pins in input mode with a static value at V
DD reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
or V
SS
(no load), all peripherals in
2.
Data based on characterization, not tested in production.
3.
All I/O pins in input mode with a static value at V
DD driven by external square wave, LVD disabled.
or V
SS
(no load), all peripherals in reset state; clock input (CLKIN)
4.
Slow mode selected with f
CPU
based on f
OSC
divided by 32. All I/O pins in input mode with a static value at V
DD load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
or V
SS
(no
5.
Slow-wait mode selected with f
CPU
based on f
OSC
divided by 32. All I/O pins in input mode with a static value at V
DD
(no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
or V
SS
6.
All I/O pins in input mode with a static value at V
DD
or V
SS
(no load). Data tested in production at V
DD
max. and f
CPU
max.
7.
This consumption refers to the Halt period only and not the associated run period which is software dependent.
8.
All I/O pins in output mode with a static value at V
SS tested in production at V
DD
max and f
CPU
max.
(no load), LVD disabled. Data based on characterization results,
A
Doc ID 13562 Rev 3 147/188
Electrical characteristics
Figure 67.
Typical I
DD
in Run mode vs. f
CPU
3.0
2.0
1.0
0.0
6.0
5.0
4.0
2.
4
2MHz
4MHz
8MHz
2.8
3.
2
3.6
4
Vdd [V]
4.4
4.
8
5.2
5.
6
Figure 68.
Typical I
DD
in WFI vs. f
CPU
2.5
2
1.5
1
0.5
0
2.
4
2.
8
2MH z
4MH z
8MH z
3.2
3.6
4
Vdd [V]
4.4
4.8
5
.2
5
.6
Figure 69.
Typical I
DD
in slow mode vs. f
CPU
0 .7
0 .6
0 .5
0 .4
0 .3
0 .2
0 .1
0
2.4
2MHz
4MHz
8MHz
2.
8
3.
2
3.6
4
4.4
Vdd [V]
4
.8
5.2
5
.6
ST7LITE49M
148/188 Doc ID 13562 Rev 3
ST7LITE49M
Figure 70.
Typical I
DD
in Slow-wait mode vs. f
CPU
0.6
0.5
0.4
0.3
0.2
0.1
0
2.4
2.8
2 MHz
4 MHz
8 MHz
3.2
3.6
4
4.4
Vdd [V]
4.8
5.
2
5.6
Electrical characteristics
Figure 71.
Typical I
DD
vs. temperature at V
DD
= 5 V and f
CPU
= 8 MHz
RUN
WFI
SLOW
SLOW-WAIT
3
2
1
0
6
5
4
-40 °C 25°C
Temp[°C]
8 5°C 125°C
Doc ID 13562 Rev 3 149/188
Electrical characteristics ST7LITE49M
Table 68.
On-chip peripheral characteristics
Symbol Parameter Conditions Typ Unit
I
I
I
DD(AT)
DD(I2C)
DD(ADC)
12-bit auto-reload timer supply current
I
2
C supply current
(2)
ADC supply current when converting
(1)
(3) f f
CPU
=4 MHz V
DD
= 3.0 V f
CPU
=8 MHz V
DD
= 5.0 V
10
50 f
CPU
=4 MHz V
DD
= 3.0 V 600 f
CPU
=8 MHz V
DD
= 5.0 V 1000
ADC
=4 MHz
V
DD
= 3.0 V 400
V
DD
= 5.0 V 600
μ
μ
μ
1.
Data based on a differential I running in PWM mode at f cpu
DD
measurement between reset configuration (timer stopped) and a timer
= 8 MHz.
2.
Data based on a differential I
I
2
DD
measurement between reset configuration (I
2
C disabled) and a permanent
C master communication at 100 kHz (data sent equal to 55h). This measurement include the pad toggling consumption (4.7 kOhm external pull-up on clock and data lines).
3.
Data based on a differential I
DD
measurement between reset configuration and continuous A/D conversions with amplifier disabled.
A
A
A
13.5 Communication interface characteristics
13.5.1 I
2
C interface
Subject to general operating conditions for V
DD
, f
OSC
, and T
A
unless otherwise specified.
Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SDAI and SCLI). The ST7 I
2
C interface meets the electrical and timing requirements of the Standard I
2
C communication protocol.
T
A
= -40 °C to 125 °C, unless otherwise specified.
Table 69.
I
2
C interface characteristics
Symbol Parameter Conditions Min Max Unit f
SCL
(1)
I²C SCL frequency f
CPU
=4 MHz to 8 MHz,
V
DD
= 2.4 to 5.5 V
1.
The I
2
C interface will not function below the minimum clock speed of 4 MHz (see
400 kHz
gives the values to be written in the I2CCCR register to obtain the required I
2
C
SCL line frequency.
150/188 Doc ID 13562 Rev 3
ST7LITE49M Electrical characteristics
Table 70.
SCL frequency (multimaster I
2
C interface)
(1)(2)(3)
I2CCCR Value f
CPU
= 4 MHz f
CPU
= 8 MHz f
SCL
400
300
200
100
V
DD
= 3.3 V V
DD
= 5 V V
DD
= 3.3 V V
DD
= 5 V
R
P
=3.3 k Ω R
P
=4.7 k Ω R
P
=3.3 k Ω R
P
=4.7 k Ω R
P
=3.3 k Ω R
P
=4.7 k Ω R
P
=3.3 k Ω R
P
=4.7 k Ω
NA
NA
84h
11h
NA
NA
84h
11h
NA
NA
84h
11h
NA
NA
84h
11h
84h
86h
8Ah
25h
83h
86h
8Ah
24h
84h
86h
8Ah
25h
84h
86h
8Ah
24h
50 25h 25h 25h 25h 4Ch 4Ch 4Dh 4Ch
20 61h 61h 61h 62h FFh FFh FFh FFh
1.
R
P
= External pull-up resistance, f
SCL
= I
2
C speed
2.
For fast mode speeds, achieved speed can have
±
5% tolerance. For other speed ranges, achieved speed can have
±
2% tolerance.
3.
The above variations depend on the accuracy of the external components used.
13.6 Clock and timing characteristics
Subject to general operating conditions for V
DD
, f
OSC
, and T
A
.
Table 71.
General timings
Symbol Parameter
(1)
Conditions Min Typ
(2)
Max Unit t c(INST)
Instruction cycle time f
CPU
= 8 MHz
2
250
3
375
12
1500 t
CPU ns t v(IT)
Interrupt reaction time t v(IT)
= Δ t c(INST)
+ 10
(3) f
CPU
= 8 MHz
10
1.25
22
2.75
1.
Guaranteed by Design. Not tested in production.
2.
Data based on typical application software.
3.
Time measured between interrupt event and interrupt vector fetch.
Δ t c(INST) needed to finish the current instruction execution.
is the number of t
CPU
cycles t
CPU
μ s
Doc ID 13562 Rev 3 151/188
Electrical characteristics ST7LITE49M
Table 72.
External clock source characteristics
Symbol Parameter Conditions Min Typ Max
V
OSC1H or
V
CLKIN_H
V
OSC1L or
V
CLKIN_L t w(OSC1H) or t w(CLKINH) t w(OSC1L) or t w(CLKINL) t r(OSC1) or t r(CLKIN) t f(OSC1) or t f(CLKIN)
OSC1/CLKIN input pin high level voltage
OSC1/CLKIN input pin low level voltage
OSC1/CLKIN high or low time
(1)
OSC1/CLKIN rise or fall time
(1)
I
L
OSCx/CLKIN Input leakage current
V
SS
≤ V
IN
≤ V
DD
0.7xV
DD
V
SS
15
1.
Data based on design simulation and/or technology characteristics, not tested in production.
V
DD
0.3xV
DD
15
±1
Figure 72.
Typical application with an external clock source
Unit
V ns
μ A
V
OSC1H or V
CLKINH
90%
10%
V
OSC1L or V
CLKINL t r(OSC1 or CLKIN))
EXTERNAL
CLOCK SOURCE t f(OSC1 or
CLKIN) t w(OSC1H or
CLKINH)) t w(OSC1L or
CLKINL)
OSC2
OSC1/CLKIN
Not connected internally f
OSC
I
L
ST7xxx
Table 73.
AWU from Halt characteristics
Symbol Parameter
(1)
Conditions t f
AWU
RCSRT
AWU oscillator frequency
AWU oscillator startup time
1.
Guaranteed by Design. Not tested in production.
Min
16
Typ
32
Max
64
50
Unit kHz
µs
152/188 Doc ID 13562 Rev 3
ST7LITE49M Electrical characteristics
13.6.2 Crystal and ceramic resonator oscillators
The ST7 internal clock can be supplied with ten different crystal/ceramic resonator oscillators. All the information given in this paragraph are based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal/ceramic resonator manufacturer for more details (frequency, package, accuracy...).
Table 74.
Crystal/ceramic resonator oscillator characteristics
Symbol Parameter Conditions Min Typ Max Unit f
CrOSC
Supplier f
CrOSC
(MHz)
C
L1
C
L2
Crystal oscillator frequency
Recommended load capacitance versus equivalent serial resistance of the crystal or ceramic resonator (R
S
)
Table 75.
Typical ceramic resonators
(1)
Typical ceramic resonators
Reference Type
Oscillator modes
C1
(pF)
C2
(pF)
Rf
2 CSTCC2M00G56Z-R0 SMD LP or MP (47) (47) open
CSTCR4M00G55Z-R0 SMD MP or MS (39) (39) open
4
CSTLS4M00G56Z-B0 LEAD MP or MS (47) (47) open
CSTCE8M00G52Z-R0 SMD MS or HS (10) (10) open
8
CSTLS8M00G53Z-B0 LEAD MS or HS (15) (15) open
CSTCE16M0V51Z-R0 SMD HS (5) (5) open
16
CSTLS16M0X53Z-B0 LEAD HS (15) (15) 47k
1.
( ) means load capacitor built in resonator.
Resonator characteristics given by the ceramic resonator manufacturer.
SMD = [-R0: plastic tape package Ø = 180 mm), -B0: Bulk]
LEAD = [-B0: bulk]
For more information on these resonators, please consult www.murata.com
2 16 MHz see table below pF
Rd
(Ohm)
Supply voltage range
(V)
Temperature range
(°C)
0
0
0
0
0
0
0
2.4 to
5.5
3.3 to
5.5
-40 to 85
Doc ID 13562 Rev 3 153/188
Electrical characteristics
Figure 73.
Typical application with a crystal or ceramic resonator
WHEN RESONATOR WITH
INTEGRATED CAPACITORS
C
L1 OSC1 i
2
Resonator R f
C
L2
OSC2
R d
ST7LITE49M f
OSC
ST7LITE49M
154/188 Doc ID 13562 Rev 3
ST7LITE49M Electrical characteristics
T
A
= -40 °C to 125 °C, unless otherwise specified.
Table 76.
RAM and hardware registers characteristics
Symbol Parameter Conditions Min
V
RM
Data retention mode
(1)
Halt mode (or reset) 1.6
1.
Minimum V
DD
supply voltage without losing data stored in RAM (in Halt mode or under reset) or in hardware registers (only in Halt mode). Guaranteed by construction, not tested in production.
Table 77.
Flash program memory characteristics
Symbol Parameter Conditions
Typ Max Unit
V
Min Typ Max Unit
V
DD
Operating voltage for Flash write/erase
Refer to operating range of V
DD with T
A,
t prog t
RET
N
RW
I
DD
Programming time for 1~32 bytes
(1)
Programming time for 4 kbytes
Data retention
(2)
Write erase cycles
Supply current
(4)
T
A
=− 40 to +125 °C
T
A
= +25 °C
T
A
=
+55 °C
(3)
T
A
= +25 °C
Read / Write / Erase modes f
CPU
= 8 MHz,
V
DD
= 5.5 V
No Read/No Write mode
Power down mode /
Halt
1.
Up to 32 bytes can be programmed at a time.
2.
Data based on reliability test results and monitored in production.
3.
The data retention time increases when the T
A
decreases.
4.
Guaranteed by Design. Not tested in production.
Table 78.
Data EEPROM memory characteristics
Symbol Parameter Conditions
V
DD
Operating voltage for
EEPROM Write/Erase
Refer to operating range of
V
DD with T
t prog
N t ret
RW
Programming time for
1~32 bytes
Data retention
(1)
Write erase cycles
T
A
=− 40 to +125 °C
T
A
=+55 °C
(2)
T
A
=
+25 °C
1.
Data based on reliability test results and monitored in production.
2.
The data retention time increases when the T
A
decreases.
2.4
20
5
0.64
1.28
s years
10k cycles
0
5.5
10
100
0.1
Min Typ Max Unit
2.4
20
5
2.6
5.5
10
V ms mA
μ A
μ A
V ms years
300k cycles
Doc ID 13562 Rev 3 155/188
Electrical characteristics ST7LITE49M
13.8 EMC (electromagnetic compatibility) characteristics
Susceptibility tests are performed on a sample basis during product characterization.
13.8.1 Functional EMS (electromagnetic susceptibility)
Based on a simple running application on the product (toggling two LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the
LEDs).
● ESD : Electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard.
● FTB : A burst of fast transient voltage (positive and negative) is applied to V
DD
and V
SS through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.
● Software recommendations
The software flowchart must include the management of runaway conditions such as:
– Corrupted program counter
– Unexpected reset
– Critical data corruption (control registers...)
● Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
Table 79.
EMS test results
Symbol Parameter Conditions
Level/
Class
V
FESD
V
FFTB
Voltage limits to be applied on any I/O pin to induce a functional disturbance
Fast transient voltage burst limits to be applied through 100 pF on V
DD
and V
SS pins to induce a functional disturbance
V
DD
= 5 V, T
A
= +25 °C, f
OSC
= 8 MHz conforms to IEC 1000-4-2
V
DD
= 5 V, T
A
= +25 °C, f
OSC
= 8 MHz conforms to IEC 1000-4-4
2B
3B
156/188 Doc ID 13562 Rev 3
ST7LITE49M Electrical characteristics
13.8.2 EMI (electromagnetic interference)
Based on a simple application running on the product (toggling two LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/3 which specifies the board and the loading of each pin.
Table 80.
EMI emissions
Symbol Parameter
S
EMI
Peak level
Conditions
V
DD
= 5 V, T
A
= +25 °C, conforming to SAE
J 1752/3
Monitored frequency band
0.1 MHz to 30 MHz
30 MHz to 130 MHz
130 MHz to 1 GHz
SAE EMI Level
Max vs.
[f
OSC
/f
CPU
]
8/4MHz 16/8MHz
Unit
28
31
18
3
32
34
26
3.5
dB
-
μ V
13.8.3 Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models can be simulated: Human body model and Machine model. This test conforms to the
JESD22-A114A/A115A standard. For more details, refer to the application note AN1181.
Table 81.
ESD absolute maximum ratings
Symbol Ratings Conditions
Maximum value
(1)
Unit
V
ESD(HBM)
V
ESD(CDM)
Electrostatic discharge voltage (Human body model)
Electrostatic discharge voltage (Charge device model)
1.
Data based on characterization results, not tested in production.
Static latch-up (LU)
T
A
= +25 °C
T
A
= +25 °C
4000
500
●
●
Two complementary static tests are required on six parts to assess the latch-up performance.
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
V
Doc ID 13562 Rev 3 157/188
Electrical characteristics
Table 82.
Electrical sensitivities
Symbol Parameter
LU Static latch-up class
13.9 I/O port pin characteristics
Conditions
T
A
= +125 °C
ST7LITE49M
Class
A
Subject to general operating conditions for V
DD
, f
OSC
, and T
A
unless otherwise specified.
Table 83.
General characteristics
Symbol Parameter Conditions Min Typ Max Unit
V
V
V
I
I
IL
IH hys
L
S
Input low level voltage
Input high level voltage
Schmitt trigger voltage hysteresis
(1)
Input leakage current
Static current consumption induced by each floating input pin
(2)
V
SS
≤ V
IN
≤ V
DD
Floating input mode
V
SS
- 0.3
0.7V
DD
400
400
0.3V
V
DD
DD
+0.3
±1 mV
μ
V
A
R
PU
Weak pull-up equivalent resistor
(3)
V
IN
= V
SS
V
V
DD
DD
= 5 V
= 3 V
100 120
300
(1)
5
140 k Ω t t t
C
IO f(IO)out r(IO)out w(IT)in
I/O pin capacitance
Output high to low level fall time
(1)
Output low to high level rise time
(1)
External interrupt pulse time
(4)
C
L
= 50 pF
Between 10% and 90%
1
25
25 t
1.
Data based on validation/design results.
2.
Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor (see
).
Static peak current value taken at a fixed V
IN based on design simulation and technology characteristics, not tested in production. This value depends on V
DD temperature values.
value, and
3.
The R
PU
pull-up equivalent resistor is based on a resistive transistor.
4.
To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external interrupt source.
pF ns
CPU
158/188 Doc ID 13562 Rev 3
ST7LITE49M Electrical characteristics
Figure 74.
Two typical applications with unused I/O pin
V
DD
10 k Ω
ST7XXX
UNUSED I/O PORT
10 k Ω
UNUSED I/O PORT
ST7XXX
1.
During normal operation the ICCCLK pin must be pulled-up, internally or externally (external pull-up of
10 k
Ω
mandatory in noisy environment). This is to avoid entering ICC mode unexpectedly during a reset.
2.
I/O can be left unconnected if it is configured as output (0 or 1) by the software. This has the advantage of greater EMC robustness and lower cost.
Figure 75.
R pu
resistance versus voltage at four different temperatures
400
350
300
250
200
150
100
50
2.4
2.8
-40°
25°
85°
125°
3.2
3.6
4
VDD [V]
4.4
4.8
5.2
5.6
Figure 76.
I pu
current versus voltage at four different temperatures
80
70
60
50
40
30
20
10
0
2.4
2.8
-40°
25°
85°
125°
3.2
3.6
4
VDD [V]
4.4
4.8
5.2
5.6
Doc ID 13562 Rev 3 159/188
Electrical characteristics ST7LITE49M
13.9.2 Output driving current
Subject to general operating conditions for V
DD
, f
CPU
, and T
A
unless otherwise specified.
Table 84.
Output driving current characteristics
Symbol Parameter Conditions Min Max Unit
V
V
OL
(1)
OH
(2)
Output low level voltage for a standard I/O pin when 8 pins are sunk at same time
(see
(see
Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time
Output high level voltage for an I/O pin when 4 pins are sourced at same time
(see
I
IO
=+5 mA,
T
A
≤ 125 °C
I
IO
T
A
=+2 mA,
≤ 125 °C
I
IO
=+20 mA,
T
A
≤ 125 °C
I
IO
T
A
=+8 mA
≤ 125 °C
I
IO
T
A
=-5 mA,
≤ 125 °C
I
IO
T
A
=-2 mA
≤ 125 °C
V
V
DD
DD
-1.5
-0.8
1.0
0.4
1.3
0.75
V
V
V
V
OL
OH
(2)(3)
OL
(1)(3)
(1)(3)
V
OH
(2)(3)
Output low level voltage for a standard I/O pin when 8 pins are sunk at same time
)
Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time
Output high level voltage for an I/O pin when 4 pins are sourced at same time
)
Output low level voltage for a standard I/O pin when 8 pins are sunk at same time
(see
Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time (see
Output high level voltage for an I/O pin when 4 pins are sourced at same time
(see
I
I
I
I
T
T
T
T
T
I
I
T
IO
A
IO
A
IO
A
IO
A
IO
A
IO
A
=+2 mA
≤ 125 °C
=+8 mA
≤ 125 °C
=-2 mA
≤ 125 °C
=+2 mA
≤ 125 °C
=+8 mA
≤ 125 °C
=-2 mA
≤ 125 °C
V
V
DD
DD
-0.8
-0.9
0.5
0.5
0.6
0.6
1.
The I
IO
current sunk must always respect the absolute maximum rating specified in
(I/O ports and control pins) must not exceed I
VSS
.
and the sum of I
IO
2.
The I
IO
current sourced must always respect the absolute maximum rating specified in
and the sum of I
(I/O ports and control pins) must not exceed I
VDD
.
IO
3.
Not tested in production, based on characterization results.
160/188 Doc ID 13562 Rev 3
ST7LITE49M
Figure 77.
Typical V
OL
at V
DD
= 2.4 V (standard)
Electrical characteristics
1400
1200
1000
800
600
400
200
0
-40°C
25°C
85°C
125°C
0 2
Iload [mA]
Figure 78.
Typical V
OL
at V
DD
= 3 V (standard)
600
400
200
0
1400
1200
1000
800
-40°C
25°C
85°C
125°C
0 2
Iload [mA]
4
Figure 79.
Typical V
OL
at V
DD
= 5 V (standard)
1800
1600
1400
1200
1000
800
600
400
200
0
-40°C
25°C
85°C
125°C
0 2 4
Iload [mA]
6 8
4
6
10
Doc ID 13562 Rev 3 161/188
Electrical characteristics
Figure 80.
Typical V
OL
at V
DD
= 2.4 V (high sink)
1200
1000
800
600
400
200
0
-40°C
25°C
85°C
125°C
0 2 4 6 8
Iload [mA]
10
Figure 81.
Typical V
OL
at V
DD
= 3 V (high sink)
12 14 16
800
600
400
200
0
1600
1400
1200
1000
-40°C
25°C
85°C
125°C
0 2 4 6 8 10
Iload [mA]
12 14 16 18 20
Figure 82.
Typical V
OL
at V
DD
= 5 V (high sink)
400
300
200
100
0
900
800
700
600
500
-40°C
25°C
85°C
125°C
0 2 4 6 8 10
Iload [mA]
12 14 16 18 20
ST7LITE49M
162/188 Doc ID 13562 Rev 3
ST7LITE49M Electrical characteristics
Figure 83.
Typical V
OL
vs. V
DD
at I
IO
= 2 mA (standard)
340
290
240
190
140
490
440
390
-40°C
25°C
85°C
125°C
2.4 2.6 2.8
3 3.2 3.4 3.6 3.8
4 4.2 4.4 4.6 4.8
5 5.2 5.4 5.6
Vdd [V]
Figure 84.
Typical V
OL
vs. V
DD
at I
IO
= 4 mA (standard)
1540
1340
1140
940
740
-40°C
25°C
85°C
125°C
540
340
140
2.4 2.6 2.8
3 3.2 3.4 3.6 3.8
4 4.2 4.4 4.6 4.8
5 5.2 5.4 5.6
Vdd [V]
Figure 85.
Typical V
OL
vs V
DD at I
IO
= 2 mA (high sink)
120
110
100
90
80
70
60
50
40
-40°C
25°C
85°C
125°C
2.4 2.6 2.8
3 3.2 3.4 3.6 3.8
4 4.2 4.4 4.6 4.8
5 5.2 5.4 5.6
Vdd [V]
Doc ID 13562 Rev 3 163/188
Electrical characteristics
Figure 86.
Typical V
OL
vs V
DD at
IO
= 8 mA (high sink)
540
490
440
390
340
290
240
190
140
-40°C
25°C
85°C
125°C
2.4 2.6 2.8
3 3.2 3.4 3.6 3.8
4 4.2 4.4 4.6 4.8
5 5.2 5.4 5.6
Vdd [V]
Figure 87.
Typical V
OL
vs V
DD at I
IO
= 12 mA (high sink)
1040
940
840
740
640
540
440
340
240
140
-40°C
25°C
85°C
125°C
2.4 2.6 2.8
3 3.2 3.4 3.6 3.8
4 4.2 4.4 4.6 4.8
5 5.2 5.4 5.6
Vdd [V]
Figure 88.
Typical V
DD
-V
OH
vs. I
IO
at V
DD
= 2.4 V (high sink)
ST7LITE49M
800
700
600
500
400
300
200
100
0
-40°C
25°C
85°C
125°C
2 4
Iload[mA]
164/188 Doc ID 13562 Rev 3
ST7LITE49M Electrical characteristics
Figure 89.
Typical V
DD
-V
OH
vs. I
IO
at V
DD
= 3 V (high sink)
1800
1600
1400
1200
1000
800
600
400
200
0
-40°C
25°C
85°C
125°C
0 2
Iload[mA]
4 6
Figure 90.
Typical V
DD
-V
OH
vs. I
IO
at V
DD
= 5 V (high sink)
4500
4000
3500
3000
2500
2000
1500
1000
500
0
0
-40°C
25°C
85°C
125°C
2 4 6 8
Iload[mA]
10 12 14
Doc ID 13562 Rev 3 165/188
Electrical characteristics
Figure 91.
Typical V
DD
-V
OH
vs. I
IO
at V
DD
= 2.4 V (standard)
800
700
600
500
400
300
200
100
0
-40°C
25°C
85°C
125°C
0 2
Iload[mA]
Figure 92.
Typical V
DD
-V
OH
vs. I
IO
at V
DD
= 3 V (standard)
1800
1600
1400
1200
1000
800
600
400
200
0
-40°C
25°C
85°C
125°C
0 2
Iload[mA]
4 6
Figure 93.
Typical V
DD
-V
OH
vs. I
IO
at V
DD
= 5 V (standard)
4500
4000
3500
3000
2500
2000
1500
1000
500
0
-40°C
25°C
85°C
125°C
0 2 4 6 8
Iload[mA]
10 12 14
166/188 Doc ID 13562 Rev 3
ST7LITE49M
ST7LITE49M Electrical characteristics
Figure 94.
Typical V
DD
-V
OH
vs. V
DD
at I
IO
= 2 mA (high sink)
800
700
600
500
400
300
200
100
0
2.4
2.8
3.2
3.6
4
Vdd [V]
4.4
-40°C
25°C
85°C
125°C
4.8
5.2
5.6
Figure 95.
Typical V
DD
-V
OH
vs. V
DD at I
IO
= 4 mA (high sink)
1800
1600
1400
1200
1000
800
600
400
200
0
2.6
3 3.4
3.8
4.2
Vdd [V]
4.6
-40°C
25°C
85°C
125°C
5 5.4
Doc ID 13562 Rev 3 167/188
Electrical characteristics
13.10 Control pin characteristics
ST7LITE49M
T
A
= -40 to 125 °C, unless otherwise specified.
Table 85.
Asynchronous RESET pin characteristics
Symbol Parameter Conditions Min Typ Max Unit
V
IL
V
IH
V hys
V
OL
Input low level voltage
Input high level voltage
Schmitt trigger voltage hysteresis
(1)
Output low level voltage
(2)
V
SS
- 0.3
0.7V
DD
2
0.3V
V
DD
DD
+0.3
V
V
R
ON
Pull-up equivalent resistor
(3)
V
DD
= 5 V I
IO
= +2 mA
V
DD
= 5 V
V
IN
= V
SS
V
DD
= 3 V
Internal reset sources
30
200
50
90
(1)
90
(1)
70 mV k t w(RSTL)out t h(RSTL)in t g(RSTL)in
Generated reset pulse duration
External reset pulse hold time
Filtered glitch duration
(4)
20
200
1.
Data based on characterization results, not tested in production
2.
The I
IO
current sunk must always respect the absolute maximum rating specified in
and the sum of I
IO
(I/O ports and control pins) must not exceed I
VSS
.
3.
The R and V
ON
DD
pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin between V
ILmax
4.
To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
RESET pin with a duration below t h(RSTL)in
can be ignored.
Ω
μ s
μ s ns
168/188 Doc ID 13562 Rev 3
ST7LITE49M
Figure 96.
RESET pin protection when LVD is enabled
V
DD
EXTERNAL
RESET
Required Optional
(note 3)
0.01
μ F
1M Ω
R
ON
Filter
PULSE
GENERATOR
Electrical characteristics
ST7xxx
INTERNAL
RESET
WATCHDOG
ILLEGAL OPCODE
LVD RESET
1.
The reset network protects the device against parasitic resets. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the
ST7 generates an internal reset (LVD or watchdog). Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below the V
IL
max. level specified in
reset circuit is designed to allow the internal reset to be output in the RESET pin, the user must ensure that the current sunk on the RESET pin is less than the absolute maximum value specified for I
INJ(RESET)
in
Section Table 59. on page 141 .
2.
When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A 10nF pulldown capacitor is required to filter noise on the reset line.
3.
In case a capacitive power supply is used, it is recommended to connect a 1 M
Ω
pull-down resistor to the
RESET pin to discharge any residual voltage induced by the capacitive effect of the power supply (this will add 5µA to the power consumption of the MCU).
Tips when using the LVD
●
●
●
Check that all recommendations related to ICCCLK and reset circuit have been applied
(see caution in
Section 4.4: ICC interface on page 21
and notes above).
Check that the power supply is properly decoupled (100 nF + 10 µF close to the MCU).
Refer to AN1709 and AN2017. If this cannot be done, it is recommended to put a
100 nF + 1 M Ω pull-down on the RESET pin.
The capacitors connected on the RESET pin and also the power supply are key to avoid any start-up marginality. In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: replace 10 nF pull-down on the RESET pin with a 5 µF to
20 µF capacitor.”
Doc ID 13562 Rev 3 169/188
Electrical characteristics
Figure 97.
RESET pin protection when LVD is disabled
V
DD
ST7LITE49M
ST7XXX
USER
EXTERNAL
RESET
CIRCUIT
0.01
μ F
R
ON
Filter
PULSE
GENERATOR
INTERNAL
RESET
WATCHDOG
ILLEGAL OPCODE
Required
1.
The reset network protects the device against parasitic resets.
The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad.
Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog).
Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below the V
IL
max. level specified in Section 13.10.1 on page 168 . Otherwise the reset will not be
taken into account internally.
Because the reset circuit is designed to allow the internal reset to be output in the RESET pin, the user must ensure that the current sunk on the RESET pin is less than the absolute maximum value specified for
I
INJ(RESET)
in Section Table 59. on page 141 .
2.
Please refer to
for more details on illegal opcode reset conditions.
13.11 10-bit ADC characteristics
Subject to general operating condition for V
DD
, f
OSC
, and T
A
unless otherwise specified.
Table 86.
ADC characteristics
Symbol f
ADC
V
AIN
R
AIN
Parameter
ADC clock frequency
(2)
Conversion voltage range
External input resistor
Conditions
V
DD
= 5 V, f
ADC
= 4 MHz
V
DD
= 3.3 V, f
ADC
= 4 MHz
2.7 V
≤
V
DD
≤
5.5 V, f
ADC
= 2 MHz
2.4 V ≤ V
DD
≤ 2.7 V, f
ADC
= 1 MHz
Min Typ
(1)
V
SSA
Max
4
V
DDA
8
7
10
20
(3)
(3)
(3)
(3)
Unit
MHz k
V
Ω
C t
ADC
STAB
Internal sample and hold capacitor
Stabilization time after ADC enable
0
6
(4) pF
μ s t
ADC
Conversion time (Sample+Hold)
- Sample capacitor loading time
- Hold conversion time f
CPU
= 8 MHz, f
ADC
= 4 MHz 3.5
4
10
1/f
ADC
1.
Unless otherwise specified, typical data are based on T
A guidelines and are not tested.
= 25 °C and V
DD
-V
SS
= 5 V. They are given only as design
2.
The maximum ADC clock frequency allowed within V
DD
= 2.4 V to 2.7 V operating range is 1 MHz.
3.
Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than the maximum value). Data guaranteed by Design, not tested in production.
4.
The stabilization time of the A/D converter is masked by the first t
LOAD valid.
. The first conversion after the enable is then always
170/188 Doc ID 13562 Rev 3
ST7LITE49M
Figure 98.
Typical application with ADC
V
DD
V
T
0.6 V
R
AIN AINx
V
AIN
V
T
0.6 V
Electrical characteristics
10-Bit A/D
Conversion
I
L
±1
μ
A
C
ADC
ST7xxx
Table 87.
ADC accuracy with V
DD
= 3.3 to 5.5 V
Symbol
(1)
Parameter Conditions
|E
T
|
|E
O
|
|E
G
|
|E
D
|
Total unadjusted error
Offset error
Gain error
Differential linearity error f f
CPU
ADC
=8 MHz,
=4 MHz
(1)
|E
L
| Integral linearity error
1.
Data based on characterization results over the whole temperature range.
Table 88.
ADC accuracy with V
DD
= 2.7 to 3.3 V
Symbol
(1)
Parameter Conditions
|E
T
|
|E
O
|
|E
G
|
|E
D
|
|E
L
|
Total unadjusted error
Offset error
Gain error
Integral linearity error
Differential linearity error f f
CPU
ADC
= 4 MHz,
= 2 MHz
(1)
1.
Data based on characterization results over the whole temperature range.
Table 89.
ADC accuracy with V
DD
= 2.4 to 2.7 V
Symbol
(1)
Parameter Conditions
|E
T
|
|E
O
|
|E
G
|
|E
D
|
|E
L
|
Total unadjusted error
Offset error
Gain error
Integral linearity error
Differential linearity error f f
CPU
ADC
= 2 MHz,
=1 MHz
(1)
1.
Data based on characterization results at ambient temperature and above.
Typ
Typ
Typ
2.0
0.9
1.0
1.2
1.1
2.5
1.1
0.5
1.1
1.2
1.9
0.9
0.8
1.4
1.1
Max
5.0
2.5
1.5
3.5
4.5
Unit
LSB
Max
3.0
1.5
1.4
2.5
2.5
Unit
LSB
Max
3.5
1.5
1.5
2.5
2.5
Unit
LSB
Doc ID 13562 Rev 3 171/188
Electrical characteristics ST7LITE49M
Figure 99.
ADC accuracy characteristics
Digital Result
1023
1022
1021
1LSBIDEAL =
1024
(2)
E
T
(3)
2
1
4
3
7
6
5
E
O
E
L
1 LSB
IDEAL
E
D
(1)
E
G
0
V
SS
1 2 3 4 5 6 7 1021 1022 1023 1024
V
DD
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
EO=Offset Error: deviation between the first actual transition and the first ideal one.
EG=Gain Error: deviation between the last ideal transition and the last actual one.
ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one.
EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line.
V in
(LSB
IDEAL
)
172/188 Doc ID 13562 Rev 3
ST7LITE49M
14
Device configuration and ordering information
Device configuration and ordering information
This device is available for production in user programmable version (Flash).
ST7LITE49M XFlash devices are shipped to customers with a default program memory content (FFh).
The two option bytes allow the hardware configuration of the microcontroller to be selected.
The option bytes can be accessed only in programming mode (for example using a standard
ST7 programming tool).
Bits 7:6 = CKSEL[1:0] Start-up clock selection.
These bits are used to select the startup frequency. By default, the internal RC is selected.
Table 90.
Startup clock selection
Configuration
Internal RC as startup clock
AWU RC as a startup clock
External crystal/ceramic resonator
External clock
Bits 5:4 = Reserved, must always be 1.
CKSEL1
1
1
0
0
CKSEL0
0
1
0
1
Bits 3:2 = LVD[1:0] Low voltage detection selection.
These option bits enable the low voltage detection block (LVD) with a selected threshold as shown in
.
Table 91.
LVD threshold configuration
Configuration
LVD off (default value)
Highest voltage threshold
Medium voltage threshold
Lowest voltage threshold
Bit 1 = WDG SW Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
Bit 0 = WDG HALT Watchdog reset on Halt
VD1
0
0
1
1
VD0
1
0
1
0
Doc ID 13562 Rev 3 173/188
Device configuration and ordering information ST7LITE49M
This option bit determines if a reset is generated when entering Halt mode while the
Watchdog is active.
0: No reset generation when entering Halt mode
1: Reset generation when entering Halt mode
Note:
OPT 7 = AWUCK Auto-wakeup clock selection
0: 32-kHz oscillator (VLP) selected as AWU clock
1: AWU RC oscillator selected as AWU clock.
If this bit is reset, OSCRANGE[2:0] must be set to 100.
OPT6:4 = OSCRANGE[2:0] Oscillator range
When the internal RC oscillator is not selected (CKSEL1=1), these option bits (and
CKSEL0) select the range of the resonator oscillator current source or the external clock source.
Table 92.
Selection of the resonator oscillator range
OSCRANGE
(1)
2 1 0
Typ. frequency range with Resonator
LP
MP
MS
HS
1~2 MHz
2~4 MHz
4~8 MHz
8~16 MHz
VLP 32.768 kHz
External Clock on OSC1/CLKIN
Reserved
External clock on PB1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1.
When the internal RC oscillator is selected, the CLKSEL option bits must be kept at their default value in order to select the 256 clock cycle delay (see
OPT 3:2 = SEC[1:0] Sector 0 size definition
These option bits indicate the size of sector 0 according to
0
1
0
1
0
1
0
1
174/188 Doc ID 13562 Rev 3
ST7LITE49M Device configuration and ordering information
Table 93.
Configuration of sector size
Sector 0 Size SEC1
0.5k
1k
2k
4k
1
1
0
0
SEC0
0
1
0
1
Bit 1 = FMP_R Read-out protection
Read-out protection, when selected provides a protection against program memory content extraction and against write access to Flash memory. Erasing the option bytes when the FMP_R option is selected will cause the whole memory to be erased first, and the device can be reprogrammed. Refer to
Section 4.5 on page 23 and the ST7
Flash Programming Reference Manual for more details.
0: Read-out protection off
1: Read-out protection on
Bit 0 = FMP_W Flash write protection
This option indicates if the Flash program memory is write protected.
0: Write protection off
1: Write protection on
Warning: When the Flash write protection is selected, the program memory (and the option bit itself) can never be erased or programmed again.
Default value
Option byte 0 Option byte 1
7 0 7 0
AWU
CK
OSCRANGE[2:0]
SEC
1
SEC
0
FMP
R
FMP
W
CK
SEL1
CK
SEL0
Res Res LVD1 LVD0
WDG
SW
WDG
HALT
1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1
Doc ID 13562 Rev 3 175/188
Device configuration and ordering information
14.2 Device ordering information
Figure 100. Ordering information scheme
Example:
Family
ST7 Microcontroller family
Sub-family
FLI49M
No. of pins
K = 32
ST7 FLI49M
Memory size
1 = 4K
K
Package
B = DIP
T = LQFP
Temperature range
6 = -40 °C to 85 °C
Shipping
TR = Tape and reel packing (available on LQFP32 only)
Blank = Tube (SDIP32) or Tray (LQFP32)
ST7LITE49M
1 T 6 TR
For a list of available options and orderable part numbers or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
176/188
Development tools for the ST7 microcontrollers include a complete range of hardware systems and software tools from STMicroelectronics and third-party tool suppliers. The range of tools includes solutions to help you evaluate microcontroller peripherals, develop and debug your application, and program your microcontrollers.
Doc ID 13562 Rev 3
ST7LITE49M Device configuration and ordering information
ST offers complete, affordable starter kits . Starter kits are complete hardware/software tool packages that include features and samples to help you quickly start developing your application.
14.3.2 Development and debugging tools
Application development for ST7 is supported by fully optimizing C Compilers and the ST7
Assembler-Linker toolchain, which are all seamlessly integrated in the ST7 integrated development environments in order to facilitate the debugging and fine-tuning of your application. The Cosmic C Compiler is available in a free version that outputs up to
16 Kbytes of code.
The range of hardware tools includes a full-featured STice Emulator , the low-cost RLink and the ST7-STICK in-circuit debugger/programmer. These tools are supported by the ST7
Toolset from STMicroelectronics, which includes the STVD7 integrated development environment (IDE) with high-level language debugger, editor, project manager and integrated programming interface.
During the development cycle, the STice emulator, the ST7-STICK and the RLink provide in-circuit programming capability for programming the Flash microcontroller on your application board.
ST also provides a low-cost dedicated in-circuit programmer and ST7 Socket Boards, which provide all the sockets required for programming any of the devices in a specific ST7 sub-family with any tool with in-circuit programming capability for ST7.
For production programming of ST7 devices, ST’s third-party tool partners also provide a complete range of gang and automated programming solutions, which are ready to integrate into your production environment.
14.3.4 Order codes for development and programming tools
below lists the ordering codes for the ST7LITE49M development and programming tools. For additional ordering codes for spare parts and accessories, refer to the online product selector at www.st.com/mcu.
Table 94.
Development tool order codes for the ST7LITE49M family
MCU
Debugging and programming tool
Starter kit with demo board
ST socket boards
ST7FLI49MK1T6
ST7FLI49MK1B6
STice emulator
(1)
STX-RLINK
(2)(3)
ST7-STICK
(4)(5)
ST7FLITE-SK/RAIS
(2)(3)
SBX-DIP32CD and SBX-QP32BC
Socket boards
(4)
1.
Contact local ST sales office for sales types.
2.
USB connection to PC.
3.
Available from ST or from Raisonance, www.raisonance.com.
4.
Add suffix /EU, /UK or /US for the power supply for your region.
5.
Parallel port connection to PC.
Doc ID 13562 Rev 3 177/188
Device configuration and ordering information ST7LITE49M
14.4 ST7 application notes
AN1046
AN1047
AN1048
AN1078
AN1082
AN1083
AN1105
AN1129
AN1130
AN1148
AN1149
AN1180
AN 969
AN 970
AN 971
AN 972
AN 973
AN 974
AN 976
AN 979
AN 980
AN1017
AN1041
AN1042
AN1044
AN1045
Table 95.
ST7 application notes
Identification
AN1658
AN1720
AN1755
AN1756
AN1812
Description
Application examples
Serial numbering implementation managing the Read-Out Protection in Flash microcontrollers
A high resolution/precision thermometer using ST7 and NE555
Choosing a DALI implementation strategy with ST7DALI
A high precision, low cost, single supply ADC for positive and negative input voltages
Example drivers
SCI communication between ST7 and PC
SPI communication between ST7 and EEPROM
I²C communication between ST7 and M24Cxx EEPROM
ST7 software SPI master communication
SCI software communication with a PC using ST72251 16-bit timer
Real time clock with ST7 timer Output Compare
Driving a buzzer through ST7 timer PWM function
Driving an analog keyboard with the ST7 ADC
ST7 keypad decoding techniques, implementing wakeup on keystroke
Using the ST7 Universal Serial Bus microcontroller
Using ST7 PWM signal to generate analog output (sinusoïd)
ST7 routine for I²C Slave mode Management
Multiple interrupt sources management for ST7 MCUs
ST7 S/W implementation of I²C bus master
UART emulation software
Managing reception errors with the ST7 SCI peripherals
ST7 software LCD Driver
PWM duty cycle switch implementing true 0% & 100% duty cycle
Description of the ST72141 motor control peripherals registers
ST72141 BLDC motor control software and flowchart example
ST7 pCAN peripheral driver
PWM management for BLDC motor drives using the ST72141
An introduction to sensorless brushless DC motor drive applications with the ST72141
Using the ST7263 for designing a USB mouse
Handling Suspend mode on a USB mouse
Using the ST7263 kit to implement a USB game pad
178/188 Doc ID 13562 Rev 3
ST7LITE49M Device configuration and ordering information
AN1276
AN1321
AN1325
AN1445
AN1475
AN1504
AN1602
AN1633
AN1712
AN1713
AN1753
AN1947
Table 95.
ST7 application notes (continued)
Identification Description
BLDC motor start routine for the ST72141 microcontroller
Using the ST72141 motor control MCU in Sensor mode
Using the ST7 USB low-speed firmware V4.x
Emulated 16-bit slave SPI
Developing an ST7265X mass storage application
Starting a PWM signal directly at high level using the ST7 16-bit timer
16-bit timing operations using ST7262 or ST7263B ST7 USB MCUs
Device firmware upgrade (DFU) implementation in ST7 non-USB applications
Generating a high resolution sinewave using ST7 PWMART
SMBus slave driver for ST7 I
2
C peripherals
Software UART using 12-bit ART
ST7MC PMAC sine wave motor control software library
General purpose
AN1476
AN1526
AN1709
AN1752
AN 910
AN 990
AN1077
AN1086
AN1103
AN1150
AN1151
AN1278
AN1131
AN1322
AN1365
AN1604
AN2200
AN 982
Low cost power supply for home appliances
ST7FLITE0 quick reference note
EMC design for ST microcontrollers
ST72324 quick reference note
Product evaluation
Performance benchmarking
ST7 benefits vs industry standard
Overview of enhanced CAN controllers for ST7 and ST9 MCUs
U435 can-do solutions for car multiplexing
Improved B-EMF detection for low speed, low voltage with ST72141
Benchmark ST72 vs PC16
Performance comparison between ST72254 & PC16F876
LIN (Local Interconnect Network) solutions
Product migration
Migrating applications from ST72511/311/214/124 to ST72521/321/324
Migrating an application from ST7263 Rev.B to ST7263B
Guidelines for migrating ST72C254 applications to ST72F264
How to use ST7MDT1-TRAIN with ST72F264
Guidelines for migrating ST7LITE1x applications to ST7FLITE1xB
Product optimization
Using ST7 with ceramic resonator
Doc ID 13562 Rev 3 179/188
Device configuration and ordering information ST7LITE49M
AN 978
AN 983
AN 985
AN 986
AN 987
AN 988
AN1039
AN1071
AN1106
AN1179
AN1446
AN1477
AN1527
AN1575
AN1576
AN1577
AN1601
AN1603
AN1529
AN1530
AN1605
AN1636
AN1828
AN1946
AN1953
AN1971
AN1014
AN1015
AN1040
AN1070
AN1181
AN1324
AN1502
Table 95.
ST7 application notes (continued)
Identification Description
How to minimize the ST7 power consumption
Software techniques for improving microcontroller EMC performance
Monitoring the Vbus signal for USB self-powered devices
ST7 checksum self-checking capability
Electrostatic discharge sensitive measurement
Calibrating the RC oscillator of the ST7FLITE0 MCU using the mains
Emulated data EEPROM with ST7 HD Flash memory
Extending the current & voltage capability on the ST7265 V
DDF
supply
Accurate timebase for low-cost ST7 applications with internal RC oscillator
Using an active RC to wake up the ST7LITE0 from power saving mode
Understanding and minimizing ADC conversion errors
PIR (passive infrared) detector using the ST7FLITE05/09/SUPERLITE
Sensorless BLDC motor control and BEMF sampling methods with ST7MC
PFC for ST7MC starter kit
ST7LITE0 microcontrolled ballast
Programming and tools
ST7 Visual DeVELOP software key debugging features
Key features of the Cosmic ST7 C-compiler package
Executing code In ST7 RAM
Using the indirect addressing mode with ST7
ST7 serial test controller programming
Starting with ST7 assembly tool chain
ST7 math utility routines
Half duplex USB-to-serial bridge using the ST72611 USB microcontroller
Translating assembly code from HC05 to ST7
Programming ST7 Flash microcontrollers in remote ISP mode (In-situ programming)
Using the ST72521 emulator to debug an ST72324 target application
Emulated data EEPROM with XFlash memory
Developing a USB smartcard reader with ST7SCR
On-board programming methods for XFlash and HD Flash ST7 MCUs
In-application programming (IAP) drivers for ST7 HD Flash or XFlash MCUs
Device firmware upgrade (DFU) Implementation for ST7 USB applications
Software implementation for ST7DALI-EVAL
Using the ST7 USB device firmware upgrade development kit (DFU-DK)
180/188 Doc ID 13562 Rev 3
ST7LITE49M Device configuration and ordering information
Table 95.
ST7 application notes (continued)
Identification
AN1635
AN1754
AN1796
AN1900
AN1904
AN1905
Description
ST7 customer ROM code release information
Data logging program for testing ST7 applications via ICC
Field updates for Flash memory based ST7 applications using a PC comm port
Hardware implementation for ST7DALI-EVAL
ST7MC three-phase AC induction motor control software library
ST7MC three-phase BLDC motor control software library
System optimization
AN1711
AN1827
AN2009
AN2030
Software techniques for compensating ST7 ADC errors
Implementation of SIGMA-DELTA ADC with ST7FLITE05/09
PWM management for 3-phase BLDC motor drives using the ST7FMC
Back EMF detection during PWM on time by ST7MC
Doc ID 13562 Rev 3 181/188
Package mechanical data
15 Package mechanical data
ST7LITE49M
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark
Figure 101. 32-pin plastic dual in-line package, shrink 400-mil width, package outline
E eC
A2 A
A1
L b2 b e
C
E1 eA eB
D
182/188
Table 96.
32-pin plastic dual in-line package, shrink 400-mil width,
(mechanical data mm inches
(1)
Dim.
Min Typ Max Min Typ
3.76
5.08
0.1480
b1
C
D
E
A
A1
A2 b
E1 e eA eB eC
3.56
0.51
3.05
0.36
0.76
0.20
27.43
9.91
7.62
3.56
0.46
1.02
0.25
10.41
8.89
1.78
10.16
4.57
0.58
1.40
0.36
28.45
11.05
9.40
12.70
1.40
0.1402
0.0201
0.1201
0.0142
0.0299
0.0079
1.0799
0.3902
0.3000
0.1402
0.0181
0.0402
0.0098
0.4098
0.3500
0.0701
0.4000
Max
0.2000
0.1799
0.0228
0.0551
0.0142
1.1201
0.4350
0.3701
0.5000
0.0551
Doc ID 13562 Rev 3
ST7LITE49M Package mechanical data
Table 96.
32-pin plastic dual in-line package, shrink 400-mil width,
(mechanical data (continued) mm inches
(1)
Dim.
Min Typ Max Min Typ
0.1201
L 2.54
3.05
3.81
0.1000
Number of pins
N 32
1.
Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 102. 32-pin low profile quad flat package (7x7), package outline
D
D1
A
A2
E1 E e b
A1
Max
0.1500
L1
L c h
Table 97.
32-pin low profile quad flat package (7x7), package mechanical data mm inches
(1)
Dim.
Min Typ Max Min Typ Max b
C
D
D1
A
A1
A2
E
E1 e
θ
L
0.05
1.35
0.30
0.09
1.60
0.15
1.45
1.40
0.37
0.45
0.20
9.00
7.00
9.00
7.00
0.0020
0.0531
0.0118
0.0035
0°
0.45
0.80
3.5°
0.60
7°
0.75
0°
0.0177
0.0551
0.0146
0.3543
0.2756
0.3543
0.2756
0.0315
3.5°
0.0236
0.0630
0.0059
0.0571
0.0177
0.0079
7°
0.0295
Doc ID 13562 Rev 3 183/188
Package mechanical data ST7LITE49M
Table 97.
32-pin low profile quad flat package (7x7), package mechanical data mm inches
(1)
Dim.
Min Typ Max Min Typ Max
0.0394
L1
N
1.00
Number of pins
32
1.
Values in inches are converted from mm and rounded to 4 decimal digits.
Table 98.
Thermal characteristics
Symbol Ratings Value Unit
R thJA
Package thermal resistance
(junction to ambient)
LQFP32
SDIP32
55
58
°C/W
T
Jmax
Maximum junction temperature
(1)
Power dissipation
(2)
150 °C
P
Dmax
TBD mW
1.
The maximum chip-junction temperature is based on technology characteristics.
2.
The maximum power dissipation is obtained from the formula P where P
INT
is the chip internal power (I
DD ports used in the application.
xV
DD
) and P
D
= (T
J
-T
A
) / R thJA
.
The power dissipation of an application can be defined by the user with the formula: P
D
=P
INT
+P
PORT
PORT
is the port power dissipation depending on the
184/188 Doc ID 13562 Rev 3
ST7LITE49M Revision history
Table 99.
Document revision history
Date Revision
01-Jun-2007
13-July-2007
1
2
Changes
Initial release.
Document reformatted and status updated to Full Datasheet.
Table 5. EEPROM register mapping and reset values removed.
Section 7.2.3: Internal RC oscillator updated.
Section 7.5.4: AVD threshold selection register (AVDTHCR) : global description of
AVD[1:0] added.
Table 62: Operating characteristics with LVD :
I
DD(LVD)
typical and maximum values updated, and note removed;
V tPOR
minimum value updated. Table 64: Voltage drop
: minimum and
maximum values added. Table 65: Internal RC oscillator characteristics (5.0 V calibration)
,
Table 66: Internal RC oscillator characteristics (3.3 V calibration)
, and Table 67: Supply current characteristics
updated.
Figure 118 ,
Figure 122 , Figure 126 , and
Table 68: On-chip peripheral characteristics
values and
Note 2 updated. t prog and N
RW
updated in Table 77: Flash program memory characteristics
. N
RW updated in
Table 78: Data EEPROM memory characteristics
.
Class updated forV
FESD in
Table 80: EMI emissions updated. Table 80: EMI emissions updated.
R
PU and R
ON
updated in Table 83: General characteristics
and
Table 85: Asynchronous RESET pin characteristics , respectively.
Cont’d
Doc ID 13562 Rev 3 185/188
Revision history ST7LITE49M
Table 99.
Document revision history (continued)
Date Revision Changes
13-Nov-2009 3
CKIN replaced by CLKIN in
Section 2: Pin description on page 14
Reset configuration of each pin shown in bold in
In
: OSC1 replaced by OSC1/CLKIN
Modified reset configuration for ICCCLK pin (
Modified note 4 in Section 4.4: ICC interface on page 21
Modified
Figure 5: Typical ICC interface on page 22
Modified
Section 7.3: Reset sequence manager (RSM) on page 37
(removed “or 4096 CPU clock cycle”)
Modifed Section 7.5.2 on page 44
(Flash memory instead of
EEPROM)
Added
Table 12: AVD threshold selection bits on page 46
Added
Table 18: ST7LITE49M interrupt mapping on page 55 updated
In
Section 11.2.3: Functional description on page 80
: modified PWM mode section and One-pulse mode section
Modified
Figure 45: Block diagram of input capture mode
and
Figure 47: Long range input capture block diagram on page 86
Removed watchdog description in
Removed bits 2:0 in LTCSR1 register in Section 11.3.6: Register description on page 104
Modified
Section 11.5.1: Introduction on page 125
and
Section 11.5.2: Main features on page 125
Modified
Figure 59: ADC block diagram on page 126
Modified one I
DD
value (Run mode) in
Table 67: Supply current characteristics on page 147
Modified Section 13.6.2: Crystal and ceramic resonator oscillators on page 153
Section 13.8 on page 156 modified
Modified
Table 80: EMI emissions on page 157
(removed notes)
V
IL
modified in
13.9.1: General characteristics on page 158
Modified first paragraph in Tips when using the LVD on page 169
Modified C
ADC
in
13.11: 10-bit ADC characteristics on page 170
Modified
Section 14.2: Device ordering information on page 176
Values in inches rounded to 4 decimal digits instead of 3 decimal
digits in mechanical data tables in Section 15 on page 182
Modified
Section 15: Package mechanical data on page 182
Table 98: Thermal characteristics on page 184
updated
Modified development tools section (replaced ST7LITE4 emulator by
STice emulator)
186/188 Doc ID 13562 Rev 3
ST7LITE49M
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