L9942
7 Appendix
Appendix
7.2
7.3
The L9942 contains logic blocks designed to detect a motor stall caused by excessive mechanical load.During a motor stall condition the load current rises much faster than during normal operation. The L9942 measures this time and compares it to a programmed value.
This is done by summing the PWM on times for one full quadrant. For a full wave stepping this is just one value (step 0). For microstepping this includes 8 separate values added together, one for each step. This measurement is only done on phase A during the
quadrants where the current is increasing naturally (quadrants 1 and 3 of Figure 15
); e.g. stall detection is active during phase counter values 1 to 8 and 17 to 24 for DIR=0. During the quadrants where the current is decreasing fast decay recirculation interferes with accurate measurement of this time. If the sum of the PWM on time is less than a programmed threshold stored in D0-D7, stall is detected and indicated as a logic “1” in the stall (ST) bit found in register 6 bit 8 (
Figure 15
bottom). If bit 11 of register 6 is set to logical
“1” then the ST bit is mirrored to the PWM pin providing detection externally.The register values DT7-DT0 store the threshold value in 16us intervals. These bits can be found interstitially in register 3 (D0, D1), register4 (D2, D3, D4) and register5 (D5, D6, D7).
Care should be taken when deciding the threshold timing. Motor current slew rates are dependant on the driving voltage, the actual speed of the motor, the back EMF of the motor as well as the motor and the inductance. Be sure to set your threshold well away from what can be seen in normal operation at any temperature.
Step clock input
The Step clock input allows to run one device in micro-step mode, or several devices simultaneously with cost effective 8 bit µController. In case of the L9942, the SPI communication link provides only the settings for motor operation mode. Motor commutation as high duty process is outsourced to a parallel driven pin. Without this step clock input, the
SPI command would also have to clock the motor, leading to a high SPI speed. For full micro-step operation or simultaneous motor drive, an 8 bit µController could be rapidly overloaded.
Load current control and detection of overcurrent (shortages at outputs)
The L9942 controls load current in the two full bridges by using a pulls with modulation
(PWM) regulator. The mirrored output current of active HS switch is compared with a programmed reference current (e.g. in figure A2 HSA1 and HSB2). Bridge is switched off if current has exceeded the programmed limit value. A second comparator of the related LS switch uses the mirrored load current to detect an overcurrent to ground during ON state of
bridges (e.g. in Figure 16 LSA2 and LSB1). The event of shortage from output to supply
voltage VS is detectable, but short current between outputs is limited through PWM controller and so an overcurrent failure will not occur.
Load currents decrease more or less fast during OFF state of bridges depending on selected decay mode. Slow decay mode is released by activating the HS switches of the
Doc ID 11778 Rev 7 33/40
Appendix L9942 bridge and current comparator has as new reference the overcurrent limit. A shortage to ground can be detected, but not between the outputs.
Is it recommended to use the different fast decay modes too, especially in period if the load current has to reduce from step to step. The duration of fast decay can set by fixed time ore that it depends on the comparator signal utilizing the second current mirror at LS switch.
There can be monitored the undershoot of bridge current during OFF state.
Fast decay can be seen as switching the bridge in opposite direction, if it is compared to ON state before. The load current control at HS switch is not used, but the comparator is still active. The reference value is changed to overcurrent limit and a shortage to ground or now between the outputs too will result in a signal. The internal filter time of at least 4 us will inhibit the signal in many applications. Then you can use the mode “auto decay without any
delay time“ (On Section 5.1
mode 100). On page 12 you can find in the lower part of
Figure 3 the phase counter values, when fast decay as only part of mixed decay is used and
the shortages can be detected during a longer time. After this it is signalized in register 7 as
overcurrent in HS switch (e.g. in Figure 17 HSA1).
34/40 Doc ID 11778 Rev 7
L9942
Figure 15.
Stall detection
PWM activ detection
Load Current Rising During High Speed
Counter value is above threshold value.
Stall
Time
Threshold
16us *
Register 5 bit7 bit6 bit5
Register 4 Reg3 bit7 bit6 bit5 bit7 bit6
D7 D6 D5 D4 D3 D2 D1 D0
PWM activ detection PWM activ detection
Time
Stall
Threshold
PWM activ counter
Stall
Threshold
PWM activ counter
No
Stall Signal
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Activ sampling and threshold
0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1
Activ sampling and threshold
Current Driver A
Phase Counter 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Current Driver A
Adress of Current
Profile Entry
0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1
Current Driver B
8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7
Current Driver B
Adress of Current
Profile Entry
8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7
STEP Signal
Micro Stepping Mode: DIR=0
Micro Stepping Mode: DIR=1
PWM activ detection
Load Current Rising During Low Speed or Stall
Time
Counter value is below threshold value.
PWM activ detection PWM activ detection
Stall
Threshold
PWM activ counter
Stall
Threshold
PWM activ counter
Stall Signal Stall Signal
Appendix
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
5 4 3 2
Activ sampling and threshold
1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2
1
0 1 2 3 4 5 6 7 8 7 6
Activ sampling and threshold
Current Driver A
Phase Counter 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Current Driver A
Adress of Current
Profile Entry
0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2
1
Current Driver B
8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7
Current Driver B
Adress of Current
Profile Entry
8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7
STEP Signal
Micro Stepping Mode: DIR=0
Micro Stepping Mode: DIR=1
Doc ID 11778 Rev 7 35/40
Appendix
Figure 16.
Reference generation for PWM control (switch on)
UP/Down
Count by
1,2,4,8
PhaseCounter
0 0 0
1
0 1
Register 0
Decay Mode
DM2 DM1 DM0
Slew Rate
SR1 SR0
StepMode DIR
0 0 0
1
Counter value changes after an signal at STEP to next one depending on selected stepping mode described in figure 3
(e.g. during micro stepping to value 2) .
STEP
0 0 0
0 1 2 3 0 1 2 3 0 1
A2 A1
2 3
A0
MUX MUX MUX
Address Calculation
Phase A
A3=0
Adr A[3..0]
A3=1
Adr neg(A[3..0])
A3 A2 A1 A0
Phase B
A3=0
Adr neg(A[3..0])
A3=1
Adr A[3..0]
Current-Profile Table stored in register2, ...6
1
1
1
1
1
1
0
0
0
1
1
0
1
1
0
1
0
0
1
0
1
1
1
0
1
1
0
1 1
1
1
1 0
0 1
0
0
0 1
0 0
1 0
0 0
Profile 8
Profile 7
Profile 6
5
5
5
9
5
Profile 5
Profile 4
Profile 3
5
5
5
Profile 2
Profile 1
Profile 0
5
5
Phase Counter
PWM Control With HS Current Monitoring
Overcurrent Detection At LS Switch
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Current Driver A
Adress of Current
Profile Entry
Phase A
0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1
Current Driver B
Adress of Current
Profile Entry
Phase B
8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7
STEP Signal
5
DI
Register 1
0
DAC Scale
0 0 1
95 mA
DAC Phase B
1 1 1
100mA * 30/31 = 91.9mA
0 0
DAC Phase A
0 1 1 0
100mA * 6/31 = 18.4mA
5 bit DAC
Phase B
I
LIMIT B
5 bit DAC
Phase A
I
LIMIT A
I
REF
REF
200 uA
DAC
Full Scale
I
MAX
LS Current
Monitoring
(Overcurrentl)
-
+
2mA
2mA
OC
LSB1
-
+
-
HS Current
Monitoring
(Load control)
-
+
-
LIMIT
HSB2
2mA
-
+
I
QA2LIM
1000
2mA
-
+
-
LS1 on
QB1
HS2on
QB2
I
B
-
+
-
LIMIT
HSA1
2mA
-
+
I
QA1LIM
1000
HS Current
Monitoring
(Load control)
HS1 on
QA1
2mA
-
+
-
I
A -
+
-
-
+
2mA
2mA
OC
LSA2
-
+
-
-
-
+
LS2 on
QA2
LS Current
Monitoring
(Overcurrent)
L9942
36/40 Doc ID 11778 Rev 7
L9942 Appendix
Figure 17.
Reference generation for PWM control (decay)
UP/Down
Count by
1,2,4,8
1
Counter value changes after an signal at STEP to next one depending on selected stepping mode described in figure 1.2
(e.g. during micro stepping to value 2) .
PhaseCounter
0 0 0
1
0 1
Register 0
Decay Mode
DM2 DM1 DM0
Slew Rate
SR1 SR0
StepMode DIR
0 0 0
STEP
0 0 0
0 1 2 3 0 1
A2
MUX
2 3
A1
MUX
0 1 2 3
A0
MUX
Address Calculation
Phase A
A3=0
Adr A[3..0]
A3=1
Adr neg(A[3..0])
A3 A2 A1 A0
Phase B
A3=0
Adr neg(A[3..0])
A3=1
Adr A[3..0]
Current-Profile Table stored in register2, ...6
1
1
1
1
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
1
1
0
1
0
1 1
1 0
0 1
1 0
1
0
0
1
0 0
1 0
0 0
Profile 8
Profile 7
Profile 6
Profile 5
Profile 4
Profile 3
Profile 2
Profile 1
Profile 0
5
9
5
5
5
5
5
5
5
5
Phase Counter
Auto Decay
Slow Decay
Mixed Decay
Fast and Slow
Decay
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Current Driver A
Adress of Current
Profile Entry
Phase A
0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1
Current Driver B
Adress of Current
Profile Entry
Phase B
8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7
STEP Signal
5
DI
Register 1
0
DAC Scale
0 0 1
95 mA
DAC Phase B
1 1 1
95mA * 30/31 = 91.9mA
0 0
DAC Phase A
0 1 1 0
100mA * 6/31 = 18.4mA
5 bit DAC
Phase B
I
REF
REF
200 uA
DAC
Full Scale
I
MAX
HS Current
Monitoring
(Overcurrent)
I
LIMIT B
2mA
5 bit DAC
Phase A
OC
HSB1
2mA
-
-
+
+
-
I
LIMIT A
I
QB1
1000
-
+
HS1 on
QB1
Fast
Decay
-
-
+
2mA QB2 LS Current
Monitoring
(Load Control)
2mA
-
+
-
LIMIT
LSB2 -
+
-
LS2on
I
B
OC
HSA1
2mA
-
+
2mA
-
+
-
-
+
-
OC
HSB1
2mA
-
+
2mA
-
+
-
-
+
-
HS Current
Monitoring
(Overcurrent)
HS1 on
Slow
QA1
Decay
HS2 on
QA2
HS Current
Monitoring
I
A
(Overcurrent)
Doc ID 11778 Rev 7 37/40
