ST72344xx, ST2345xx Central processing unit
Figure 11.
CPU registers
7 0
RESET VALUE = XXh
7 0
RESET VALUE = XXh
7 0
15 PCH 8
RESET VALUE = XXh
7 PCL 0
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
1
RESET VALUE = 1
1 I1 H I0 N Z
1 1 X 1 X X
0
C
X
15 8 7 0
RESET VALUE = STACK HIGHER ADDRESS
ACCUMULATOR
X INDEX REGISTER
Y INDEX REGISTER
PROGRAM COUNTER
CONDITION CODE REGISTER
STACK POINTER
X = Undefined Value
Reset value: 111x1xxx
7
1 1 I1 H
Read/Write
I0 N Z
0
C
The 8-bit Condition Code register contains the interrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions.
These bits can be individually tested and/or controlled by specific instructions.
Arithmetic management bits
Bit 4 = H Half carry.
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.
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Central processing unit ST72344xx, ST2345xx
Bit 2 = N Negative.
This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It’s a copy of the result 7 th
bit.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(that is, the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instructions.
Bit 1 = Z Zero.
This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero.
0: The result of the last operation is different from zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test instructions.
Bit 0 = C Carry/borrow.
This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.
Interrupt management bits
Bits 5,3 = I1, I0 Interrupt
The combination of the I1 and I0 bits gives the current interrupt software priority.
Table 6.
Priority
Interrupt software priority
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable)
I1
0
1
1
0
I0
0
1
0
1
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions.
See the interrupt management chapter for more details.
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