Supply, reset and clock management
7.2
ST72344xx, ST2345xx
Phase locked loop
The PLL can be used to multiply a 1 MHz frequency from the RC oscillator or the external clock by 4 or 8 to obtain f
OSC of 4 or 8 MHz. The PLL is enabled and the multiplication factor of 4 or 8 is selected by 3 option bits. Refer to
Table 7 for the PLL configuration depending on
the required frequency and the application voltage. Refer to
Section 15.1
for the option byte description.
Table 7.
PLL configurations
Target ratio x4
(1) x4 x8
V
DD
2.7 V - 3.65 V
3.3 V - 5.5 V
PLL ratio x4 x8 x8
1.
For a target ratio of x4 between 3.3 V - 3.65 V, this is the recommended configuration.
DIV2
OFF
ON
OFF
Figure 14.
PLL output frequency timing diagram
LOCKED bit set
4/8 x input freq.
t
STAB t
STARTUP t
LOCK t
When the PLL is started, after reset or wakeup from Halt mode or AWUFH mode, it outputs the clock after a delay of t
STARTUP
.
When the PLL output signal reaches the operating frequency, the LOCKED bit in the
SICSCR register is set. Full PLL accuracy (ACC
PLL
) is reached after a stabilization time of t
STAB
(see Figure 14 ).
Refer to
Section 7.6.5: Register description for a description of the LOCKED bit in the
SICSR register.
Caution: The PLL is not recommended for applications where timing accuracy is required.
Caution: When the RC oscillator and the PLL are enabled, it is recommended to calibrate this clock through the RCCRH and RCCRL registers.
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