Chapter 5 Generic Pin Configuration
DRQ
DRQ asserts to request a DMA transfer cycle. The behavior of the DRQ pin depends on the IN bit in the CFG. For GPIB reads (IN = 1), DRQ asserts when the FIFOs contain a word (or byte, if the 16/8N bit is clear) for the host interface to read. For GPIB writes,
DRQ asserts when there is room for the host interface to write a word (or byte) to the
FIFOs.
Normally, DRQ remains asserted as long as accesses can be made to the FIFOs. You can use the TIMER register and the TMOE and TIM/BYTN bits of the CFG to limit the assertion time of the DRQ signal.
DRQ is an output-only pin. If the application does not require DMA, you can leave DRQ unconnected.
DACKN
The DACKN signal selects the FIFOs for access. If BBUSN and ABUSN are asserted, the TNT4882 performs a 16-bit access. If BBUSN is asserted but ABUSN is unasserted, the TNT4882 performs only an 8-bit access to FIFO B. The TNT4882 ignores the CSN pin when DACKN is asserted.
The DACKN pin is an active low input-only pin with an internal pull-up resistor. If the application does not require DMA, you can connect DACKN to Vdd or leave DACKN unconnected.
BURST_RDN
When BURST_RDN is asserted, the TNT4882 drives Data Bus A and Data Bus B with the next word to be read from the FIFOs. BURST_RDN does not remove data from the
FIFOs; the host interface removes data from the FIFOs by using a normal DMA read access.
Using BURST_RDN does not increase the rate at which data can be read from the FIFOs.
However, by using BURST_RDN, you can guarantee that the data bus is valid on the assertion edge of the RDN signal.
In many applications, you will not need BURST_RDN. You can connect BURST_RDN to Vdd or leave BURST_RDN unconnected.
© National Instruments Corp.
5-5 TNT4882 Programmer Reference
