Chapter 6 ISA Pin Configuration
BHEN_N
BHEN_N enables register accesses through DATA15–8. This pin is usually connected to the ISA BHE* signal. For 8-bit ISA slave applications, you can leave these pins unconnected.
Register Select Pins
ADDR9–5, SW9–5, AEN_N
These pins determine whether the TNT4882 responds to I/O cycles. The TNT4882 responds to an I/O cycle by asserting an internal chip select signal when AEN_N is at a logic low level and the ADDR9–5 pins exactly match the SW9–5 pins.
AEN_N can be connected to the ISA Address Enable signal. ADDR9–5 is usually connected to the ISA address bus. SW9–5 determine the base address of the TNT4882.
SW9–5 are typically connected to a set of dip switches.
ADDR4–0
The ADDR4–0 pins select one of the registers of the TNT4882 during I/O reads or writes.
During DMA accesses, the TNT4882 ignores the ADDR4–0 pins.
IORN, IOWN
During write accesses, the TNT4882 latches data on the rising edge of IOWN. The
TNT4882 drives one or both of the data buses when IORN is asserted during read accesses. You can connect these signals directly to the ISA bus.
Other CPU Interface Pins
DRQ
DRQ asserts to request a DMA transfer cycle. The behavior of the DRQ pin depends on the IN bit in the CFG. For GPIB reads (IN = 1), DRQ asserts when the FIFOs contain a word (or byte, if the 16/8N bit is clear) for the host interface to read. For GPIB writes,
DRQ asserts when there is room for the host interface to write a word (or byte) to the
FIFOs.
The DRQ pin can be tristated by clearing the DMAEN bit in the Accessory Write
Register (ACCWR). See the Accessory Write Register (ACCWR) section in Chapter 3,
TNT4882 Interface Registers.
© National Instruments Corp.
6-3 TNT4882 Programmer Reference
