Determining the PPE Message. NI TNT4882 Programmer Reference

Appendix C Introduction to the GPIB

Determining the PPE Message

The PPE message contains the parallel poll configuration data for a device. Table C-2 shows how you determine the value of DIO[7:1] for the PPE message. As with all commands, the DIO[8] is a don't care bit.

Table C-2. Determining the PPE Message

Sense Bit (S) PPR Message to Send

0

0

0

0

PPR1

PPR2

PPR3

PPR4

1

1

1

1

0

0

0

0

1

1

1

1

PPR5

PPR6

PPR7

PPR8

PPR1

PPR2

PPR3

PPR4

PPR5

PPR6

PPR7

PPR8

PPE Message

(hex)

60

61

62

63

68

69

6A

6B

64

65

66

67

6C

6D

6E

6F

Physical Representation of the PPR Message

To send a PPR message true, a device drives the corresponding GPIB DIO signal low with an open-collector driver. For example, to send the PPR4 message true, a device drives the GPIB DIO4 signal low.

Because devices drive the DIO signals with open-collector drivers during parallel polls, more than one device can share a PPR message. If a Controller detects a PPR message being sent true, the Controller knows that one or more of the devices sharing the PPR message is sending the PPR message true.

© National Instruments Corp.

C-27 TNT4882 Programmer Reference

Introduction to the GPIB Appendix C

Clearing and Triggering Devices

A Controller can clear devices in several ways. It can assert the IFC line to clear all devices, or it can send the Device Clear (DCL) command message to clear all devices on the bus. To clear a single device, a Controller can address the device to listen, then send the Selected Device Clear (SDC) command message.

After a device receives DCL or SDC, its clear state is device dependent. Generally, sending DCL or SDC is a less extreme method of clearing a device than asserting IFC.

Most devices support the DCL and SDC method; all devices support the IFC method.

All devices in multidevice measurement systems must often be sampled as closely together as possible. You can trigger devices simultaneously by using the Group Execute

Trigger (GET) command message. This command message causes all currently addressed devices that have triggering capability to initiate a preprogrammed action.

The action could be, for example, to take a measurement or begin a sweep.

TNT4882 Programmer Reference C-28 © National Instruments Corp.

Appendix D

Introduction to HS488

This appendix describes HS488 and the sequence of events in data transfers.

HS488 is a proposed addition to the ANSI/IEEE Standard 488.1-1987. HS488 specifies using a noninterlocked handshake protocol to transfer data among two or more devices.

By using the HS488 protocol, devices can transfer data at rates that are higher than the rates that are possible by using the IEEE 488.1 protocol.

Objectives of HS488

Fast Transfer Rates

HS488 enables transfer rates that are substantially faster than the IEEE 488.1 standard transfer rates. In small systems, the raw transfer rate can be up to 8 MB/s. The faster raw transfer rates improve system throughput in systems where devices send long blocks of data. The physical limitations of the cabling system, however, limit the transfer rate.

Compatibility with Existing IEEE 488.1 Devices

HS488 devices are compatible with IEEE 488.1 devices. IEEE 488.1 devices and HS488 devices can exist in the same system, and they communicate with each other by using

IEEE 488.1 protocols.

A Controller does not need to be capable of HS488 noninterlocked transfers. While ATN is true, a Controller sources multiline messages to HS488 devices just as it sources multiline messages to any IEEE 488.1 devices.

No Additional Software Overhead—Automatic HS488 Detection

Addressed HS488 devices detect whether other addressed devices are also HS488 capable without the Controller's action.

No Changes to the IEEE 488.2 Standard

The HS488 protocol requires no changes to the IEEE 488.2 standard. HS488 devices do not need to be IEEE 488.2 compliant.

© National Instruments Corp.

D-1 TNT4882 Programmer Reference

Introduction to HS488 Appendix D

No Added Cabling Restrictions beyond IEEE 488.1

Systems that meet the IEEE 488.1 requirements for higher speed operation meet the

HS488 requirements.

You should be aware of the limitations that affect HS488 usage. See Table D-1.

Table D-1. HS488 Limitations

Cabling requirements: Same as IEEE 488.1.

Does not reduce software overhead.

System throughput increases depend on data block size.

IEEE 488.1 Requirements If T1 Delay Is 350 ns

The IEEE 488.1 standard specifies that devices intending high-speed operation must use three-state, 48-mA drivers on most signals. Each device must add no more than 50-pF capacitance on each signal and all devices must be powered on.

The total cable length in a system must be no more than 15 m or 1 m times the number of devices in the system.

Additional HS488 System Requirements

An HS488 system must meet the IEEE 488.1 standard requirements described in the preceding section, and HS488 devices must implement three new interface functions.

Talking devices must use the Source Handshake Extended (SHE) interface function, which is an extension of the IEEE 488.1 SH function. Listening devices use the Acceptor

Handshake Extended (AHE) interface function, which is an extension of the IEEE 488.1

AHE function. Accepting devices must have at least a small buffer to store received data.

HS488 devices must implement the Configuration (CF) interface function. At system power on, the Controller uses previously undefined multiline messages to configure

HS488 devices. The CF function enables devices to interpret these multiline messages.

Sequence of Events in Data Transfers

Figure D-1 shows a typical IEEE 488.1 data transfer. The HS488 protocol modifies the

IEEE 488.1 Source Handshake and Acceptor Handshake functions. At the beginning of each data transfer, the HS488 source and acceptor functions determine whether all active

TNT4882 Programmer Reference D-2 © National Instruments Corp.

Appendix D Introduction to HS488

Talkers and Listeners are capable of HS488 transfers. If the addressed devices are HS488 capable, they use the HS488 noninterlocked handshake protocol for that data transfer. If any addressed device is not HS488 capable, the transfer continues using the standard three-wire handshake.

IEEE 488.1 Three-Wire Transfers

~DIO1-8

(composite)

~DAV

~NFRD

~NDAC

HS488 Transfers

~DIO1-8

(composite)

~DAV

~NFRD

~NDAC

Figure D-1. IEEE 488.1 and HS488 Transfers

The following section describes the sequence of events for data transfers that involve

HS488 devices. Table D-2 summarizes the three transfer cases.

Table D-2. Start of Transfer—Three Cases

Talker is HS488—Listener is HS488.

Talker is HS488—Listener is not HS488.

Talker is not HS488—Listener is HS488.

© National Instruments Corp.

D-3 TNT4882 Programmer Reference

Introduction to HS488 Appendix D

Case 1: Talker and Listener Are HS488 Capable

The following steps describe a typical sequence of events in an HS488 data transfer in which the Talker and Listener are both HS488 capable. Refer to Figure D-2.

T1

1st byte transferred

(using 488.1 handshake).

T13 T14

~ATN

~DIO1-8

(composite)

~DAV

~NRFD

~NDAC

The sending device uses this "high speed capable" signal (the momentary, low-going pulse on ~NRFD) to tell the receiving device that the sending device is capable of sending data using the high-speed handshake.

2nd byte transferred

(using high-speed mode).

Lack of low-going transition on

~NRFD indicates that all receiving devices are high-speed capable.

Figure D-2. Talker and Listener Are HS488 Capable

1. The Controller addresses devices and becomes Standby Controller by unasserting

ATN.

2. The Listener asserts NDAC and NRFD.

3. The Listener unasserts NRFD as it becomes ready to accept a byte.

4. After allowing time for the Listener to detect NRFD unasserted, the Talker indicates that it is capable of HS488 operation by sending the HSC message. To send the

HSC message true, the Talker asserts the NRFD signal.

5. After allowing time for the Listener to respond to the HSC message, the Talker sends the HSC message false. To send the HSC message false, the Talker unasserts the NRFD signal.

6. When the Talker has a byte ready to send, it drives the data on the DIO signal lines, allows some settling time, and asserts DAV.

TNT4882 Programmer Reference D-4 © National Instruments Corp.

Appendix D Introduction to HS488

7. The Listener unasserts NDAC. HS488 Listeners do not assert NRFD as IEEE 488.1

devices would. Because of this behavior, the Talker determines that the addressed

Listener is capable of HS488 transfers.

8. The Talker unasserts DAV and begins to drive the next data byte on the GPIB.

9. After allowing some settling time, the Talker asserts DAV.

10. The Listener latches the byte in response to the assertion (falling) edge of DAV.

11. After allowing some hold time, the Talker unasserts DAV and drives the next data byte on the DIO signal lines.

12. Steps 9–11 are repeated for each data byte.

Case 2: Talker Is HS488 Capable, But Listener Is Not HS488 Capable

The following steps describe a typical sequence of events in an HS488 data transfer in which the Talker is HS488 capable, but the Listener is not. Refer to Figure D-3.

~ATN

~DIO1-8

(composite)

~DAV

T1

~NRFD

~NDAC

"High-speed capable" signal

Low-going transition on~NRFD indicates that not all receiving devices are high-speed capable.

Figure D-3. Talker Is HS488 Capable, But Listener Is Not HS488 Capable

© National Instruments Corp.

D-5 TNT4882 Programmer Reference

Introduction to HS488 Appendix D

Steps 1–6 are identical to steps 1–6 in case 1, Talker and Listener Are HS488 Capable.

The Listener ignores the HSC message from the Talker.

Step 7: The IEEE 488.1 Listener enters ACDS and asserts NRFD. Because of this behavior, the Talker determines that the addressed Listener is not capable of

HS488 transfers. The Talker sources bytes by using the IEEE 488.1 protocol.

Case 3: Talker Is Not HS488 Capable

The Talker does not send an HSC message to the Listener, but begins sourcing bytes by using the IEEE 488.1 protocol.

The Addressed Listener (HS488 or IEEE 488.1) accepts bytes by using the IEEE 488.1

standard three-wire handshake. Refer to Figure D-4.

~ATN

~DIO1-8

(composite)

~DAV

T1

~NRFD

~NDAC

Figure D-4. Talker Is Not HS488 Capable, But Listener Is HS488 Capable

Transfer Holdoffs—3 Cases

There are three transfer holdoff cases:

• Acceptor buffer full.

• Acceptor forces return to three-wire handshake.

• Program message terminator.

TNT4882 Programmer Reference D-6 © National Instruments Corp.

Appendix D Introduction to HS488

Case 1: Listener's Buffer Nearly Full

The following steps describe a typical sequence of events in a transfer holdoff in which the Listener's buffer is nearly full. Refer to Figure D-5.

Transfer paused

T13 T14 T13 T14

~DIO1-8

(composite)

~DAV

~NRFD

~NDAC

Acceptor not ready Talker may send extra DAB after NDAC asserts. Acceptor must be able to receive.

Figure D-5. Acceptor Buffer Full

1. During an HS488 transfer, the buffer of a Listener becomes nearly full. The

Listener asserts NDAC when its buffer is nearly full.

2. The Talker detects that NDAC is asserted and stops sending data bytes.

Note: The Talker can source another byte while the NDAC signal is propagating down the cable system. Asserting NDAC does not interrupt the transfer of this byte. The Listener must be able to accept such bytes.

3. The device function removes data bytes from the Listener's buffer so that it is not nearly full. The Listener unasserts NDAC.

4. The Talker resumes transferring data bytes by using the noninterlocked handshake protocol.

© National Instruments Corp.

D-7 TNT4882 Programmer Reference

Introduction to HS488 Appendix D

Case 2: Listener Wants to Resume Three-Wire Handshake

Near the end of a transfer, the Listener can force the sourcing device to resume using the three-wire handshake. Once the handshake is three-wire, the Listener can hold off on every byte. Refer to Figure D-6.

Three-wire handshake

NRFD holdoff

T13 T14

~DIO1-8

(composite)

~DAV

~NRFD

~NDAC

Acceptor wants to hold off the handshake.

Talker may send extra DAB after NDAC asserts. Acceptor must be able to receive.

Figure D-6. Acceptor Wants to Resume Three-Wire Handshake

The following sequence of events makes the Talker resume the use of the three-wire handshake:

1. The Listener asserts NDAC.

2. The Talker detects NDAC asserted and stops sending data bytes.

Note: The Talker can source another byte while the NDAC signal is propagating down the cable system. Asserting NDAC does not interrupt the transfer of this byte. The Listener must be able to accept such bytes.

3. The Listener waits for the Talker to stop sending data bytes, then asserts NRFD.

4. In response to NRFD, the Talker resumes using the IEEE 488.1 three-wire handshake when the Listener is ready.

TNT4882 Programmer Reference D-8 © National Instruments Corp.

Appendix D Introduction to HS488

Case 3: Talker Sends EOI or EOS

The following steps describe a typical sequence of events in a transfer holdoff in which the Talker sends EOI or EOS. Refer to Figure D-7.

Transfer paused pmt = EOI + EOS

T13 T14 T13 T15

~DIO1-8

(composite)

~DAV

~NRFD

~NDAC

Figure D-7. Program Message Terminator

1. When an HS488 Talking device sends EOI or EOS, the Talker asserts DAV for a longer time than for other bytes. The relatively long DAV pulse gives the Listener enough time to holdoff the Talker before the Talker sends another byte.

2. When the Listener detects EOI or EOS, it asserts NDAC.

3. The Talker detects NDAC asserted and stops sending data bytes.

System Configuration

The HS488 Acceptor Handshake and Source Handshake interface functions depend on several time delays. Some of these delays are a function of the total system cable length.

The Controller must communicate this system configuration data to HS488 devices after the system powers on. The Controller configures HS488 devices by sourcing two multiline messages while ATN is true.

The first message is the CFE message. The Controller sends the CFE message by driving a bit pattern (1E hex) that the IEEE 488.1 standard does not define on the DIO signal lines. The CFE message enables HS488 devices to interpret the SCG message that follows. The second message is a Secondary Command Group (SCG) message that contains the configuration data. The Secondary command has the bit pattern 6n hex, where n is the meters of cable in the system.

© National Instruments Corp.

D-9 TNT4882 Programmer Reference

Appendix E

Standard Commands for Programmable

Instruments (SCPI)

This appendix discusses the Standard Commands for Programmable Instruments (SCPI) document, the required SCPI commands, and SCPI programming.

GPIB instrumentation standards have progressed from the IEEE 488.1 standard to the

IEEE 488.2 standard to SCPI. The IEEE 488.1 standard simplified and standardized the interconnection of programmable instrumentation by defining the electrical, mechanical, and protocol specifications of the GPIB. Before IEEE 488.1, each manufacturer had its own proprietary interface.

The IEEE 488.2 standard kept the IEEE 488.1 standard intact, but it made systems more compatible and program development easier by defining standard data codes and formats, a status-reporting model, a message exchange protocol, a set of common commands for all instruments, and Controller requirements. Because the IEEE 488.1 standard did not address these issues, manufacturers implemented each item differently, thus creating complex programming and unpredictable development costs.

SCPI uses the IEEE 488.2 standard as a basis for defining a single, comprehensive command set that is suitable for all instruments. SCPI users no longer need to learn a different command set for each instrument in their systems.

You can use IEEE 488.1, IEEE 488.2, and SCPI instruments and Controllers together, but you achieve the maximum benefits with a system consisting of an IEEE 488.2 Controller and SCPI instruments.

© National Instruments Corp.

E-1 TNT4882 Programmer Reference

SCPI Appendix E

IEEE 488.2 Common Commands Required by SCPI

All SCPI devices require the mandatory common commands that the IEEE 488.2

standard defines (see Table E-1). This command set consists of program commands and status queries that are common to all devices. These commands and queries do not handle device-specific operations; they handle more general operations such as device identification, operation synchronization, standard event status enabling and reporting, device reset and self-test, and service request enable reporting.

Table E-1. IEEE 488.2 Common Commands Required by SCPI

Command

*CLS

*ESE

*ESE?

*ESR?

*IDN?

*OPC

*OPC?

*RST

*SRE

*SRE?

*STB?

*TST?

*WAI?

Description

Clear Status Command

Standard Event Status Enable Command

Standard Event Status Enable Query

Standard Event Status Register Query

Identification Query

Operation Complete Command

Operation Complete Query

Reset Command

Service Request Enable Command

Service Request Enable Query

Read Status Byte Query

Self-Test Query

Wait-to-Continue Command

TNT4882 Programmer Reference E-2 © National Instruments Corp.

Appendix E SCPI

SCPI Required Commands

In addition to the IEEE 488.2 common commands and queries, SCPI defines its own set of required common commands (see Table E-2). In general, these commands build on the IEEE 488.2 common command set, but SCPI expands the standard status-reporting model defined in the IEEE 488.2 standard with OPERation and QUEStionable status registers. For both of these registers, commands read the contents of the EVENt and

CONDition registers, set the ENABle mask, and read the ENABle mask.

The SYSTem command set defines functions that are not related to instrument performance, such as commands for performing general housekeeping like setting TIME or SECurity. The subcommand query ERRor? requests the next entry from the error/event queue of the device. The PRESet command configures the SCPI and device-dependent status registers to be reported through the SCPI status-reporting model.

Table E-2. SCPI Required Commands

Command

:SYSTem

:ERRor?

:STATus

:OPERation

[:EVENt]?

:CONDition?

:ENABle

:QUEStionable

[:EVENt]?

:CONDition

:ENABle

:ENABle?

:PRESet

Description

Collects functions not related to instrument performance

Requests the next entry from the instrument's error queue

Controls the SCPI-defined status-reporting structures

Selects the Operation structure

Returns the contents of the Event register

Returns the contents of the Condition register

Reads the Enable mask

Selects the Questionable structure

Returns the contents of the Event register

Returns the contents of the Condition register

Sets the Enable mask, which allows event reporting

Reads Enable mask

Enables all required event reporting

SCPI Optional Commands

The SCPI command set that an instrument uses can include a subset of the commands covered in the SCPI specification. An instrument designed to measure voltage does not implement commands to measure frequency. An instrument can also support special commands not presently covered in the SCPI standard.

© National Instruments Corp.

E-3 TNT4882 Programmer Reference

SCPI Appendix E

SCPI commands are not case sensitive. Moreover, a command such as TRIGger can be issued as TRIGGER or as its short-form mnemonic, TRIG. However, SCPI does not recognize any other version of this command. For example, TRIGG is not a valid command.

Programming with SCPI

The functional blocks of the SCPI Instrument model define the command categories.

These categories, along with some other general categories, have a hierarchical structure of subcommands and parameters for more specific functions (see Figure E-1).

. . .

. . .

SENSe

VOLTage

. . .

CURRent

. . .

TRIGger

. . .

. . .

SOURce

. . .

. . .

Figure E-1. Partial Command Categories

Most instruments require commands to execute a specific function. For example, a digital voltmeter can require the MEASure, VOLTage, and AUTO commands to take a voltage reading. To properly interpret these commands, SCPI defines a hierarchical command structure called a command tree. Figure E-2 illustrates a simple command tree for the SENSe command subsystem.

SENSe

. . .

UPPer

. . .

RANge

. . .

VOLTage

. . .

AUTO

. . .

RESolution

AUTO

. . .

UPPer

. . .

RANge

CURRent

. . .

. . .

POWer

RESolution

. . .

AUTO AUTO

Figure E-2. Simple Command Tree for the SENSe Command Subsystem

TNT4882 Programmer Reference E-4 © National Instruments Corp.

Appendix E SCPI

The SENSe commands control the characteristics of the conversion process for the input sensors of the instrument. Examples include the following:

• Signal amplitude for VOLTage, CURRent, and POWer.

• Filter BANDwidth.

• FREQuency characteristics.

The SENSe commands do not mathematically manipulate the data after it has been converted.

Constructing SCPI Commands by Using the Hierarchical

Command Structure

The SENSe commands program an instrument to control the conversion of the signal into internal data that can be manipulated. SENSe commands control such parameters as range, resolution, gate time, and normal mode rejection. By using the partial command tree shown in Figure E-3, you can construct the short form command to configure an instrument for a voltage measurement that uses dynamic autoranging. This command is as follows:

SENS:VOLT:RANG:AUTO:DIR:EITH

. . .

UPPer

. . .

SENSe

. . .

VOLTage

. . .

POWer

.

.

RANGe

LOWer

. . .

AUTO

DIRection

. . .

UP DOWN

CURRent

.

.

EITHer

. . .

. . .

Figure E-3. Partial Command Tree for the SENSe Command Subsystem

© National Instruments Corp.

E-5 TNT4882 Programmer Reference

SCPI Appendix E

The SOURce commands program the instrument to generate a signal based on specified characteristics and internal data. SOURce block functions specify such signal parameters as amplitude modulation, power, current, voltage, and frequency. By using the partial command tree shown in Figure E-4, you can construct the short form command to set the upper limit of the current output to 500 mA. This command is as follows:

SOUR:CURR:LIM:HIGH 0.5

AMPLitude

SOURce

. . .

. . .

CURRent

LIMit

. . .

POWer

.

.

OFFSet HIGH

VOLTage

.

.

. . .

LOW STATe

Figure E-4. Partial Command Tree for the SOURce Command Subsystem

The TRIGger commands program the instrument to synchronize its operation based on some event. Trigger sources include an internal event or condition involving the instrument functionality, an external condition such as an analog or digital signal, or a software command. By using the partial command tree shown in Figure E-5, you can construct the short form command to trigger an instrument from an external source. This command is as follows:

TRIG:SOUR:EXT

BUS ECLTrg EXTernal

. . .

TRIGger

SOURce

. . .

HOLD IMMediate INTernal LINE

Figure E-5. Partial Command Tree for the TRIGger Command Subsystem

LINK

TNT4882 Programmer Reference E-6 © National Instruments Corp.

Appendix E SCPI

Parsing SCPI Commands

Colons separate each command and instruct the instrument parser to move down a level in the command tree hierarchy. In situations where two commands are issued without changing levels, a semicolon separates the commands. Commas separate parameters such as numeric, extended numeric, discrete, and Boolean. Commas are generally ignored with two exceptions:

• Spaces should not break command words.

• Spaces must not separate commands and parameters.

The colon preceding the first command in a SCPI message instructs the parser in the

SCPI instrument to reset itself to the root level in the hierarchy.

Unless specifically noted, all commands have a query form as defined in the IEEE 488.2

standard. When a query command is received, the current instrument settings associated with that command are placed in the instrument output buffer. For more commands, consult the SCPI standard or the user manuals for the SCPI instruments of interest in a particular application.

© National Instruments Corp.

E-7 TNT4882 Programmer Reference

Appendix F

Multiline Interface Command Messages

This appendix lists the multiline interface messages and describes the mnemonics and messages that correspond to the interface functions. The multiline interface messages are

IEEE 488 defined commands that are sent and received with ATN TRUE. The interface functions include initializing the bus, addressing and unaddressing devices, and setting device modes for local or remote programming.

© National Instruments Corp.

F-1 TNT4882 Programmer Reference

Multiline Interface Command Messages

Multiline Interface Command Messages

Appendix F

Hex Oct Dec ASCII Msg

1C

1D

1E

1F

18

19

1A

1B

14

15

16

17

10

11

12

13

0C

0D

0E

0F

08

09

0A

0B

04

05

06

07

00

01

02

03

030

031

032

033

034

035

036

037

020

021

022

023

024

025

026

027

010

011

012

013

014

015

016

017

000

001

002

003

004

005

006

007

28

29

30

31

24

25

26

27

20

21

22

23

16

17

18

19

12

13

14

15

10

11

8

9

6

7

4

5

2

3

0

1

FS

GS

RS

US

CAN

EM

SUB

ESC

DLE

DC1

DC2

DC3

DC4

NAK

SYN

ETB

BS

HT

LF

VT

FF

CR

SO

SI

NUL

SOH

STX

ETX

EOT

ENQ

ACK

BEL

Hex Oct Dec ASCII Msg

48

49

50

51

52

54

55

60

61

62

63

56

57

58

59

44

45

46

47

40

41

42

43

36

37

38

39

32

33

34

35

060

061

062

063

064

066

067

070

071

072

073

074

075

076

077

050

051

052

053

054

055

056

057

040

041

042

043

044

045

046

047

GTL

SDC

PPC

GET

TCT

LLO

DCL 34

PPU 35

36

37

30

31

32

33

SPE

SPD

3C

3D

3E

3F

38

39

3A

3B

2C

2D

2E

2F

28

29

2A

2B

24

25

26

27

20

21

22

23

>

?

<

=

;

:

8

9

6

7

4

5

2

3

0

1

$

%

'

&

"

#

!

SP MLA0

MLA1

MLA2

MLA3

MLA4

MLA5

MLA6

MLA7

*

+

)

( MLA8

MLA9

MLA10

MLA11

/

.

, MLA12

- MLA13

MLA14

MLA15

MLA16

MLA17

MLA18

MLA19

MLA20

MLA21

MLA22

MLA23

MLA24

MLA25

MLA26

MLA27

MLA28

MLA29

MLA30

UNL

Message Definitions

DCL

GET

GTL

LLO

Device Clear

Group Execute Trigger

Go To Local

Local Lockout

MLA My Listen Address

MSA

MTA

PPC

PPD

My Secondary Address

My Talk Address

Parallel Poll Configure

Parallel Poll Disable

TNT4882 Programmer Reference F-2 © National Instruments Corp.

Appendix F Multiline Interface Command Messages

Multiline Interface Command Messages

Hex Oct Dec ASCII Msg Hex Oct Dec ASCII Msg

130

131

132

133

134

135

136

137

120

121

122

123

124

125

126

127

110

111

112

113

114

115

116

117

100

101

102

103

104

105

106

107

92

93

94

95

88

89

90

91

84

85

86

87

80

81

82

83

76

77

78

79

72

73

74

75

68

69

70

71

64

65

66

67

5C

5D

5E

5F

58

59

5A

5B

54

55

56

57

50

51

52

53

4C

4D

4E

4F

48

49

4A

4B

44

45

46

47

40

41

42

43

170

171

172

173

174

175

176

177

160

161

162

163

164

165

166

167

150

151

152

153

154

155

156

157

140

141

142

143

144

145

146

147

7C

7D

7E

7F

78

79

7A

7B

74

75

76

77

70

71

72

73

6C

6D

6E

6F

68

69

6A

6B

64

65

66

67

60

61

62

63

MTA16

MTA17

MTA18

MTA19

MTA20

MTA21

MTA22

MTA23

MTA24

MTA25

MTA26

MTA27

MTA28

MTA29

MTA30

UNT

MTA0

MTA1

MTA2

MTA3

MTA4

MTA5

MTA6

MTA7

MTA8

MTA9

MTA10

MTA11

MTA12

MTA13

MTA14

MTA15

^

_

]

\

[

Z

X

Y

T

U

V

W

P

Q

R

S

L

M

N

O

I

H

J

K

D

E

F

G

@

A

B

C

120

121

122

123

124

125

126

127

112

113

114

115

116

117

118

119

104

105

106

107

108

109

110

111

96

97

98

99

100

101

102

103 f g d e b c

` a

MSA0,PPE

MSA1,PPE

MSA2,PPE

MSA3,PPE

MSA4,PPE

MSA5,PPE

MSA6,PPE

MSA7,PPE i h MSA8,PPE

MSA9,PPE j MSA10,PPE k MSA11,PPE l MSA12,PPE m MSA13,PPE n MSA14,PPE o MSA15,PPE r s p MSA16,PPD q MSA17,PPD

MSA18,PPD

MSA19,PPD t MSA20,PPD u MSA21,PPD v MSA22,PPD w MSA23,PPD x MSA24,PPD y MSA25,PPD z MSA26,PPD

{ MSA27,PPD

| MSA28,PPD

} MSA29,PPD

~ MSA30,PPD

DEL

Message Definitions

PPE

PPU

SDC

SPD

Parallel Poll Enable

Parallel Poll Unconfigure

Selected Device Clear

Serial Poll Disable

SPE

TCT

UNL

UNT

Serial Poll Enable

Take Control

Unlisten

Untalk

© National Instruments Corp.

F-3 TNT4882 Programmer Reference

Appendix G

Mnemonics Key

This appendix defines the mnemonics (abbreviations) that this manual uses for functions, remote messages, local messages, states, bits, registers, integrated circuits, and system functions.

The mnemonic types in this key are abbreviated to mean the following:

A

B

F

IC

LM

P

R

RM

SF

ST

Auxiliary or Accessory Commands

Bit

Function

Integrated Circuit

Local Message

Physical Device Pin

Register

Remote Message

System Function

State

© National Instruments Corp.

G-1 TNT4882 Programmer Reference

Mnemonics Key Appendix G

Mnemonic

16/8N

Type

B

Definition

16- or 8-Bit Mode bit

A

ADM0

ADM1

ADMR

ADR

ADR0

ADR1

ADSC

ADSC IE

ADSR

AEFN

AEHS

AEN_N

AFFN

AH1

AHAS

AIDS

A/BN

ABUS

ABUSN

ACCR

ACCRA

ACCRB

ACCRE

ACCRF

ACCRI

ACCRJ

ACCWR

ACDS

ACG

ACRDY

ACRS

ADHS

ANHS1

ANHS2

ANRS

APT

APT IE

ARS

ATN

ATN*

ATN IE

B

ST

ST

B

B

B

P

B

F

B

B

R

B

R

R

R

R

ST

B

B

B

RM

B

B

ST

B

B

B

R

ST

RM

B

R

R

R

R

P

R

R

R

FIFO First bit

"A" Data Bus

"A" Data Bus Enable Pin

Accessory Register

Accessory Register A

Accessory Register B

Accessory Register E

Accessory Register F

Accessory Register I

Accessory Register J

Accessory Write Register

Acceptor Data State (AH function)

Addressed Command Group

Acceptor Ready State bit

Acceptor Ready State

Acceptor Data Holdoff State bit

Address Mode bit 0

Address Mode bit 1

Address Mode Register

Address Register

Address Register 0

Address Register 1

Address Status Change bit

Address Status Change Interrupt Enable bit

Address Status Register

FIFO A Empty Flag bit

Acceptor End Holdoff State bit

ISA Address Enable Pin

FIFO A Full Flag bit

Acceptor Handshake

Acceptor High-Speed Active State

Acceptor Idle State

Acceptor Not Ready Holdoff bit

Acceptor Not Ready Holdoff Immediately bit

Acceptor Not Ready State

Address Pass Through bit

Address Pass Through Interrupt Enable bit

Address Register Select bit

Attention

Attention bit

Attention Interrupt Enable bit

TNT4882 Programmer Reference G-2 © National Instruments Corp.

Appendix G Mnemonics Key

B

BBUS

BBUSN

BCR

BEFN

BFFN

BHE

BHEN

BI

BI IE

BIN

BO

BO IE

BSR

BTO

Mnemonic

ATNI

ATNI IE

AUXCR

AUXMR

AUXRA

AUXRB

AUXRE

AUXRF

AUXRG

AUXRI

AUXRJ

AWNS

Type

R

R

R

R

B

B

R

R

R

R

R

ST

Definition

ATN Interrupt bit

ATN Interrupt Enable bit

Auxiliary Command Register

Auxiliary Mode Register

Auxiliary Register A

Auxiliary Register B

Auxiliary Register E

Auxiliary Register F

Auxiliary Register G

Auxiliary Register I

Auxiliary Register J

Acceptor Wait For New Cycle State

B

B

B

R

B

P

B

B

P

R

B

B

"B" Data Bus

"B" Data Bus Enable Pin

Bus Control Register

FIFO B Empty Flag bit

FIFO B Full Flag bit

ISA Byte High Enable Signal

Byte High Enable Pin

Byte In bit

Byte In Interrupt Enable bit

Binary bit

Byte Out bit

Byte Out Interrupt Enable bit

Bus Status Register

Byte Timeout bit

C

C

CACS

CCEN

CCR

CDOR

CFG

CHES ch_rst

CIC

CIC IE clear ADSC clear ATNI

R

R

R

B

F

ST

B

A

B

B

A

A

© National Instruments Corp.

Controller

Controller Active State (C function)

Carry Cycle Enable bit

Carry Cycle Register

Command/Data Out Register

Configuration Register

Clear Holdoff On End Select bit

Chip Reset auxiliary command

Controller-In-Charge bit

Controller-In-Charge Interrupt Enable bit

Clear ADSC Interrupt auxiliary command

Clear ATNI Interrupt auxiliary command

G-3 TNT4882 Programmer Reference

Mnemonics Key Appendix G

Mnemonic Type clear DEC clear DET clear END clear ERR clear IFCI clear LOKC clear REMC clrpi

CMDR

CNT0

CNT1

CNT2

CNT3

R

R

CPT B

CPT ENABLE B

A

R

R

R

CPT IE

CPTR

CPUACC

CSN

CSR

P

P

B

R

R

A

A

A

A

A

A

A

Definition

Clear DEC Interrupt auxiliary command

Clear DET Interrupt auxiliary command

Clear END Interrupt auxiliary command

Clear ERR Interrupt auxiliary command

Clear IFCI Interrupt auxiliary command

Clear LOKC Interrupt auxiliary command

Clear REMC Interrupt auxiliary command

Clear Page-In Registers auxiliary command

Command Register

Count 0 Register

Count 1 Register

Count 2 Register

Count 3 Register

Command Pass Through bit

Command Pass Through Enable bit

Command Pass Through Interrupt Enable bit

Command Pass Through Register

CPU Access Pin

Chip Select Pin

Chip Signature Register

D

DAC

DACKN dacr dai dai dal dat

DAV

DAV

DC1

DCAS

DCAS IE

DCL

DCR

DEC

DEC IE

DET

DET IE

DGA

DGB

DHADC

RM

P

A

A

B

B

B

B

B

B

F

B

B

B

B

B

RM

RM

R

B

B

Data Accepted

DMA Acknowledge Pin

Release DAC Holdoff auxiliary command

Disable IMR2, IMR1, And IMR0 Interrupts auxiliary command

Disable IMR2, IMR1, And IMR0 Interrupts bit

Disable Listener bit

Disable Talker bit

Data Valid

GPIB Data Valid Signal bit

Device Clear

Device Clear Active State bit

Device Clear Active State Interrupt Enable bit

Device Clear

DIO Control Register

Device Clear bit

Device Clear Interrupt Enable bit

Device Execute Trigger bit

Device Execute Trigger Interrupt Enable bit

Deglitch Selector A

Deglitch Selector B

DAC Holdoff On DCL Or SDC Command bit

TNT4882 Programmer Reference G-4 © National Instruments Corp.

Appendix G Mnemonics Key

Mnemonic

DHADT

DHALA

DHALL

DHATA

DHDC

DHDT

DHUNTL

DI

DI IE

DIR

DL

DL0

DL1

DMAE

DMAEN

DMAI

DMAO

DO

DO IE

DONE

DONE IE

DRQ

DSR

DT

DT

DT0

DT1

DTAS

Type

B

B

B

B

B

B

B

B

B

B

B

B

B

B

R

B

B

B

R

B

F

B

B

B

B

B

B

ST

Definition

DAC Holdoff On GET Command bit

DAC Holdoff On All Listener Addresses Command bit

DAC Holdoff On All UCG, ACG, And SCG Commands bit

DAC Holdoff On All Talker Addresses Command bit

DAC Holdoff On DCAS Command bit

DAC Holdoff On DTAS Command bit

DAC Holdoff On The UNL Or UNT Command bit

Data In bit

Data In Interrupt Enable bit

Data In Register

Disable Listener bit

Disable Listener 0 bit

Disable Listener 1 bit

DMA Enable bit

DMA Enable bit

DMA Input Enable bit

DMA Output Enable bit

Data Out bit

Data Out Interrupt Enable bit

GPIB Transfer Status bit

GPIB Transfer Status Interrupt Enable bit

DMA Request Pin Status bit

DIO Status Register

Disable Talker bit

Device Trigger function

Disable Talker 0 bit

Disable Talker 1 bit

Device Trigger Active State

E

edpa

END

END IE

END RX

EOI

EOI

EOS

EOS0

EOS1

EOS2

EOS3

EOS4

EOS5

B

B

B

B

B

RM

RM

B

B

B

B

B

B

© National Instruments Corp.

Enable Dual Primary Addressing Mode bit

End Received bit

End Received Interrupt Enable bit

End Received bit

End-or-Identify bit

End or Identify

End of String

End-of-String bit 0

End-of-String bit 1

End-of-String bit 2

End-of-String bit 3

End-of-String bit 4

End-of-String bit 5

G-5 TNT4882 Programmer Reference

Mnemonics Key

Mnemonic

EOS6

EOS7

EOSR

ERR

ERR IE

EXTDAC

F

feoi fget

FIFOA

FIFOB

G

GET

GET IE

GND

GO

GO2SIDS

GSYNC

GTL

H

HALT hdfa hdfe

HIER

HLDA

HLDE hldi

HSC

HSE

HSSEL

HSTS

HWE

A

A

R

R

RM

B

P

B

B

B

RM

B

B

A

B

A

A

R

B

R

ST

Type

B

B

R

B

B

Appendix G

Definition

End-of-String bit 6

End-of-String bit 7

End-of-String Register

Error bit

Error Interrupt Enable bit

External DAC

Send EOI With The Next Byte

Force Group Execute Trigger auxiliary command

First-In First-Out Buffer A

First-In First-Out Buffer B

Group Execute Trigger bit

Group Execute Trigger Interrupt Enable bit

Ground Pin

GO Command bit

Go To SIDS bit

GPIB Synchronization bit

Go To Local

Turbo488 Transfer State Machine Halted bit

Holdoff On All Data auxiliary command

Holdoff On End Only auxiliary command

High-Speed Enable Register

Holdoff On All Data bit

Holdoff On End bit

Holdoff Handshake Immediately

HS488 Capable Signal

High-Speed Enable bit

Handshake Select Register

High-Speed T1 State

High Write Enable

TNT4882 Programmer Reference G-6 © National Instruments Corp.

Appendix G

Mnemonic

I

Type

IDY

IFC

IFC IE

IFCI

IFCI IE

IMR0

IMR1

IMR2

IMR3

IN

INT

INT0

INT1

INTEN

INTR

INTSRC2 B

INTSRC2 IE B

IOCHRDY

IORN

P

P

IOWN

ISR0

ISR1

ISR2

P

R

R

R

ISR3

ISS ist ist

R

B

A

LM

B

B

B

R

R

R

B

B

B

B

R

R

RM

RM

B

K

KCR

KEYCLK

R

B

KEYDATA B

KEYDATEN B

KEYDQ

KEYREG

KEYRST*

B

R

B

Mnemonics Key

Definition

Identify

Interface Clear

Interface Clear Interrupt Enable bit

IFC Interrupt bit

IFC Interrupt Enable bit

Interrupt Mask Register 0

Interrupt Mask Register 1

Interrupt Mask Register 2

Interrupt Mask Register 3

Data Direction Transfer bit

Interrupt Request Pin bit

Interrupt Register 0 Interrupt bit

Interrupt Register 1 Interrupt bit

Interrupt Enable bit

Board Interrupt Register

Interrupt Source 2 bit

Interrupt Source 2 Interrupt Enable bit

ISA Pin

ISA Pin

ISA Pin

Interrupt Status Register 0

Interrupt Status Register 1

Interrupt Status Register 2

Interrupt Status Register 3

Individual Status Select bit

Parallel Poll Flag auxiliary command

Individual Status

Key Control Register

Key Clock bit

Key Data bit

Key Data Enable bit

Key Data bit

Key Control Register

Key Reset bit

© National Instruments Corp.

G-7 TNT4882 Programmer Reference

Mnemonics Key

Mnemonic

L

lon lon

LPAS

LPAS

LPIS lul lun lut

LWLS

L

LA

LACS

LADCS

LADS

LAG

LE3

LIDS

LLO

LLOC

LLOC IE

LOCS

LOK

LOKC

LOKC IE

M

MA

MA IE

MAC

MAC IE

MISC

MJMN

MLA

MODE

MSA

MSTD

MTA

Type

B

B

B

B

R

B

RM

B

RM

B

RM

ST

B

B

B

ST

B

B

B

F

B

ST

ST

ST

RM

F

B

LM

B

ST

ST

A

LM

A

ST

Appendix G

Definition

Listen

Listener Active bit

Listener Active State

Listener Addressed Or Active State

Listener Addressed State (L function)

Listener Address Group

Extended Listener

Listener Idle State

Local Lockout bit

Local Lockout Change bit

Local Lockout Change Interrupt Enable bit

Local State

Lockout bit

Lockout Change bit

Lockout Change Interrupt Enable bit

Listen-Only bit

Listen Only

Listener Primary Addressed State bit

Listener Primary Addressed State

Listener Primary Idle State

Unlisten auxiliary command

Local Unlisten

Local Untalk auxiliary command

Local With Lockout State

My Address bit

My Address Interrupt Enable bit

My Address Change bit

My Address Change Interrupt Enable bit

Miscellaneous Register

Major–Minor bit

My Listen Address

MODE bit

My Secondary Address

Modify Short T1 Delay bit

My Talk Address

TNT4882 Programmer Reference G-8 © National Instruments Corp.

Appendix G Mnemonics Key

Mnemonic

N

Type nba nba nbaf nbaf

NDAC

NEF

NEF IE

NFF

NFF IE

NL

NL IE

NLEE

NOAS

NODMA

Nonvalid

NOTS B

NO_TSETUP B

NPRS

NRFD

ST

RM

NRFD*

NTNL

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

LM

A

Definition

New Byte Available local message bit

New Byte Available

New Byte Available False auxiliary command

New Byte Available False bit

Not Data Accepted bit

Not Empty FIFO bit

Not Empty FIFO Interrupt Enable bit

Not Full FIFO bit

Not Full FIFO Interrupt Enable bit

New Line Receive bit

New Line Receive Interrupt Enable bit

New Line End Enable bit

No HALT On ATN Or STBQ Interrupts bit

No DMA bit

Nonvalid auxiliary command issued

No HALT On TO And SRQ Interrupts bit

No TSETUP Delay bit

Negative Poll Response State

Not Ready For Data Message

GPIB Not Ready For Data Status bit

No Talking When No Listener bit

O

ONEC

OSA

OTA

B

RM

RM

One-Chip bit

Other Secondary Address

Other Talk Address

P

P1

P2

P3

PACS

PCG

PEND piaccr pibcr pieosr piimr2

PMT

B

B

B

ST

RM

B

A

A

A

A

© National Instruments Corp.

Parallel Poll Response bit 1

Parallel Poll Response bit 2

Parallel Poll Response bit 3

Parallel Poll Addressed To Configure state

Primary Command Group

Pending bit

Page-In Accessory Register auxiliary command

Page-In Bus Control Register auxiliary command

Page-In End-of-String Register auxiliary command

Page-In Interrupt Mask Register 2 auxiliary command

Programmed Message Terminator

G-9 TNT4882 Programmer Reference

Mnemonics Key

Mnemonic

PMT_W_EOS pon

PPC

PPD

PPE

PPIS

PPR

PPR

PPSS

PPU

PT1

PT1_ENA pts

PTS

PUCS

Type

RM

R

B

A

LM

ST

LM

RM

RM

RM

ST

R

RM

ST

R

RDN rdy

RDY1

REM

REMC

REMC IE

REMS

REN

REOS reqf

B

A reqt A

RESET FIFO B

RESETN

RFD rhdf

RL1

P

RM

B

F

P

LM

P

B

B

B

ST

RM rlc

RLC

RLC IE rqc

B

B

B

B

RQS rsv

RM

B rsv LM rsv2 A rtl

RWLS

A

ST

Appendix G

Definition

PMT signal is asserted with EOS

Power On

Parallel Poll Configure

Parallel Poll Disable

Parallel Poll Enable

Parallel Poll Idle State

Parallel Poll Register

Parallel Poll Response

Parallel Poll Standby Active

Parallel Poll Unconfigure

Programmable T1 Register

Programmable T1 enable

Pass Through Next Secondary auxiliary command

Pass Through Next Secondary local message

Parallel Poll Unaddressed To Configure state

Read Pin

Ready For Next Message

Ready Pin

Remote bit

Remote Change bit

Remote Change Interrupt Enable bit

Remote State

Remote Enable

End On EOS Received bit

Request rsv False auxiliary command

Request rsv True auxiliary command

Reset FIFO Command bit

Reset Pin

Ready For Data

Release RFD Holdoff

Remote/Local

Release Control command

Remote/Local Change bit

Remote/Local Change Interrupt Enable bit

Request Control command

Request Service

Request Service bit

Request Service Bit 2 auxiliary command

Return To Local auxiliary command

Remote With Lockout State

TNT4882 Programmer Reference G-10 © National Instruments Corp.

Appendix G Mnemonics Key

Mnemonic

S

Type

SRQS

STB

STBO

STBO IE stdl

STOP

STOP IE

STRS

STS1

STS2 sw7210

SWAP

SWAPN

S

SASR

SCG

SDC

SDYS

SDYS1

SDYS2 seoi

SGNS

SH1

SH1A

SH1B

SHAS

SH_CNT

SIDS

SISB

SLOW

B

B

SOFT RESET B

SPAS ST

SPAS IE

SPD

SPE

SPEOI

B

RM

RM

B

SPIS

SPMR

SPMS

SPMS

SPSR

SR1

SRAS

SRQ

ST

R

B

ST

R

F

ST

RM

B

ST

R

ST

A

ST

F

B

B

R

RM

RM

ST

ST

ST

A

B

B

ST

ST

RM

B

B

R

R

A

B

P

Definition

© National Instruments Corp.

Status Bit Polarity (Sense) bit

Source Acceptor Status Register

Secondary Command Group

Selected Device Clear

Source Delay State

Source Delay State 1

Source Delay State 2

Send EOI auxiliary command

Source Generate State

Source Handshake function

Source Handshake State bit A

Source Handshake State bit B

Source High-Speed Active State

SH_CNT Register

Source Idle State

Static Interrupt Status bits

Slow Handshake Lines

Soft Reset Command bit

Serial Poll Active State

Serial Poll Active State Interrupt Enable bit

Serial Poll Disable

Serial Poll Enable

Send Serial Poll EOI bit

Serial Poll Idle State

Serial Poll Mode Register

Serial Poll Mode State bit

Serial Poll Mode State

Serial Poll Status Register

Service Request function

System Control Remote Enable Active State

Service Request

Service Request State

Status Byte

Status Byte Out bit

Status Byte Out Interrupt Enable bit

Set Short T1 Delay auxiliary command

Turbo488 Transfer State Machine Status bit

STOP Interrupt Enable bit

Source Transfer State

Status 1 Register

Status 2 Register

Switch To Turbo+7210 Mode auxiliary command

SWAP bit

SWAP Pin

G-11 TNT4882 Programmer Reference

Mnemonics Key Appendix G

Mnemonic swrst

SYNC

SYNC IE

SYNS

T

T

T12

T13

T17

TA

TACS

TADCS

TADS

TAG

TCT

TE

TE5

TIDS

TIM/BYTN

TIMER

TLC

TLCHLTE

TLCINT

TLCINT IE

TMOE

TO

TO IE ton ton

TPAS

TPAS

TPIS

TRI trig

U

U

UCG

UDPCF ulpa

F

ST

B

R

ST

RM

RM

F

IC

B

F

R

R

R

B

ST

ST

B

B

B

B

ST

ST

B

B

B

LM

B

A

Type

B

B

B

ST

B

RM

RM

B

Definition

Software Reset auxiliary command issued

GPIB Synchronization bit

GPIB Synchronization Interrupt Enable bit

Synchronization state

Talker

T12 Register

T13 Register

T17 Register

Talker Active bit

Talker Active State (T function)

Talker Active Or Addressed State

Talker Addressed State

Talk Address Group

Take Control

Extended Talker

Talker Extended

Talker Idle State

Time Or Byte Limit bit

Timer Register

Talker/Listener/Controller (GPIB Adapter)

TLC (GPIB Adapter) Halt Enable bit

NAT4882 Interrupt Line bit

NAT4882 Interrupt Line Interrupt Enable bit

Timer Timeout Enable bit

Timeout bit

Timeout Interrupt Enable bit

Talk Only

Talk-Only bit

Talker Primary Addressed State bit

Talker Primary Addressed State

Talker Primary Idle State

Three-State Timing bit

Trigger auxiliary command

Unconfigure bit

Universal Command Group

Undefined Primary Command Function

Upper/Lower Primary Address bit

TNT4882 Programmer Reference G-12 © National Instruments Corp.

Appendix G

W

WRAP

WRN

X

X

XEOS

XTALI

XTALO

Mnemonic Type

UNC

UNC IE unl

B

B

A

UNL unt

RM

A

UNT RM

USTD B

V

valid vstdl

B

A

B

P

P

P

B

B

Mnemonics Key

Definition

Unrecognized Command bit

Unrecognized Command Interrupt Enable bit

Unlisten auxiliary command

Unlisten command

Untalk auxiliary command

Ultra Short T1 Delay bit

Valid auxiliary command

Very Short T1 Delay auxiliary command

Wrap Back bit

Write Pin

Don't Care bit

Transmit END With EOS bit

Crystal In Pin

Crystal Out Pin

© National Instruments Corp.

G-13 TNT4882 Programmer Reference

Appendix H

Customer Communication

For your convenience, this appendix contains forms to help you gather the information necessary to help us solve technical problems you might have as well as a form you can use to comment on the product documentation. Filling out a copy of the Technical

Support Form before contacting National Instruments helps us help you better and faster.

National Instruments provides comprehensive technical assistance around the world. In the U.S. and Canada, applications engineers are available Monday through Friday from

8:00 a.m. to 6:00 p.m. (central time). In other countries, contact the nearest branch office.

You may fax questions to us at any time.

Corporate Headquarters

(512) 795-8248

Technical support fax: (800) 328-2203

(512) 794-5678

Branch Offices

Australia

Austria

Belgium

Denmark

Finland

France

Germany

Hong Kong

Italy

Japan

Korea

Mexico

Netherlands

Norway

Singapore

Spain

Sweden

Switzerland

Taiwan

U.K.

Phone Number

03 9 879 9179

0662 45 79 90 19

02 757 03 11

45 76 71 11

90 502 2930

1 48 14 24 14

089 714 60 35

2686 8505

02 48301915

03 5472 2977

02 596 7455

5 202 2544

03480 30673

32 84 86 00

2265887

91 640 0533

08 730 43 70

056 20 51 55

02 737 4644

01635 523154

Fax Number

03 9 879 9422

0662 45 79 90 0

02 757 00 20

45 76 26 00

90 527 2321

1 48 14 24 24

089 741 31 30

2645 3186

02 48301892

03 5472 2970

02 596 7456

5 520 3282

03480 33466

32 84 84 00

2265886

91 640 0085

08 730 49 70

056 20 51 51

02 377 1200

01635 523545

© National Instruments Corp.

H-1 TNT4882 Programmer Reference

Technical Support Form

Technical support is available at any time by fax. Include the information from your configuration form. Use additional pages if necessary.

Name

Company

Address

Fax ( )

Computer brand

Model

Operating system

RAM MB

Display adapter

Mouse no

Other adapters installed

Brand

Instruments used

National Instruments hardware product(s)

Revision

Configuration

(continues)

The problem is

List any error messages

The following steps will reproduce the problem

TNT4882 Hardware Configuration Form

Record the settings and revisions of your hardware and software on the line to the right of each item. Update this form each time you revise your software or hardware configuration, and use this form as a reference for your current configuration.

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Title: TNT4882 TM Programmer Reference Manual

Edition Date: July 1995

Part Number: 370872A-01

Please comment on the completeness, clarity, and organization of the manual.

(continues)

If you find errors in the manual, please record the page numbers and describe the errors.

Thank you for your help.

Name

Title

Company

Address

Phone ( )

Mail to:

Fax to:

Technical Publications

National Instruments Corporation

6504 Bridge Point Parkway, MS 53-02

Austin, TX 78730-5039

Technical Publications

National Instruments Corporation

MS 53-02

(512) 794-5678

I/O

ISA m

MB

NL s

TL

W

ANSI

ASIC

C0

CPU

DACK

DMA

DRQ

EOI

EOS

ESP

F

GPIB hex

Hz

IEEE

Glossary

Prefix pn-

µ

m-

M-

Meaning piconanomicromillimega-

Value

10

-12

10

-9

10

-6

10

-3

10

6

American National Standards Institute application-specific integrated circuit

No Controller capability central processing unit

DMA Acknowledge direct memory access

DMA Request

End-or-Identify

End-of-String

Engineering Software Package

Farads

General Purpose Interface Bus hexadecimal hertz

Institute of Electrical and Electronic Engineers input/output

Industry Standard Architecture meters megabytes of memory

New Line seconds

Talker/Listener watts

© National Instruments Corp.

Glossary-1 TNT4882 Programmer Reference

Index

Numbers/Symbols

16/8N bit

Configuration Register (CFG), 3-68

Status 2 Register (STS2), 3-132

A

A[5-1] bit, Address Register (ADR), 3-23

A/BN bit, Configuration Register (CFG),

3-66

ABUSN signal, 5-3

ABUS_OEN signal, 5-3 acceptor handshake holdoffs in one-chip mode

DAC holdoffs, 4-16 to 4-17

GPIB rdy message and RFD holdoffs, 4-15 to 4-16

Accessory Register (ACCR) offset

(table), 3-9

Accessory Register A (ACCRA), 3-12

Accessory Register B (ACCRB), 3-13

Accessory Register E (ACCRE), 3-14

Accessory Register F (ACCRF), 3-15

Accessory Register I (ACCRI), 3-16

Accessory Register J (ACCRJ), 3-17 to 3-18

Accessory Write Register

(ACCWR), 3-19

ACCWR (Accessory Write

Register), 3-19

ACRDY bit, Source/Acceptor Status

Register (SASR), 3-124

AD[5-0 -- 1-0] bits, Address Register 0

(ADR0), 3-24

AD[5-1] bit, ADR (Address

Register), 3-22

AD[5-1 -- 1-1] bits, Address Register 1

(ADR1), 3-25

ADDR4-0 pins generic pin configuration, 5-3

ISA pin configuration, 6-3

ADDR9-5 pin, 6-3

Address Mode Register (ADMR), 3-20 to 3-21 addressing modes extended dual addressing, 3-21 extended single addressing, 3-20 listen only (lon), 3-21 no addressing, 3-20 normal dual addressing, 3-20 talk only (ton), 3-21

Address Register (ADR) one-chip mode, Turbo+7210 mode, 3-22

Turbo+9914 mode, 3-23

Address Register 0 (ADR0) description, 3-24 hidden registers (table), 3-4

Address Register 1 (ADR1) description, 3-25 hidden registers (table), 3-4

Address Status Register (ADSR)

Turbo+7210 mode, 3-26 to 3-28

Turbo+9914 mode, 3-29 to 3-31 addressing, GPIB. See GPIB addressing.

ADHS bit, Source/Acceptor Status

Register (SASR), 3-124

ADMR (Address Mode Register). See

Address Mode Register (ADMR).

ADR (Address Register) one-chip mode, Turbo+7210 mode, 3-22

Turbo+9914 mode, 3-23

ADR0 (Address Register 0) description, 3-24 hidden registers (table), 3-4



National Instruments Corp.

I-1 TNT4882 Programmer Reference

Index

ADR1 (Address Register 1) description, 3-25 hidden registers (table), 3-4

ADSC bit, Interrupt Status Register 2

(ISR2), 3-106

ADSC IE bit, Interrupt Mask Register 2

(IMR2), 3-106

ADSR (Address Status Register)

Turbo+7210 mode, 3-26 to 3-28

Turbo+9914 mode, 3-29 to 3-31

AEFN bit, Status 2 Register

(STS2), 3-132

AEHS bit, Source/Acceptor Status

Register (SASR), 3-124

AEN_N pin, 6-3

AFFN bit, Status 2 Register

(STS2), 3-132

ANHS1 bit, Source/Acceptor Status

Register (SASR), 3-124

ANHS2 bit, Source/Acceptor Status

Register (SASR), 3-124

ANSI/IEEE standard. See IEEE 488.1 standard.

APT bit, Interrupt Status Register 1

(ISR1) one-chip mode, Turbo+7210 mode,

3-93 to 3-94

Turbo+9914 mode, 3-100

APT IE bit, Interrupt Mask Register 1

(IMR1) one-chip mode, Turbo+7210 mode,

3-93 to 3-94

Turbo+9914 mode, 3-100

ARS bit, ADR (Address Register), 3-22

ATN bit

Address Status Register

(ADSR), 3-29

Bus Control Register (BCR)/Bus

Status Register (BSR), 3-63

ATN* bit, Address Status Register

(ADSR), 3-26

ATN (Attention) line, GPIB, C-9

ATNI bit

Interrupt Status Register 0

(ISR0), 3-87

Interrupt Status Register 2

(ISR2), 3-109

ATNI IE bit

Interrupt Mask Register 0

(IMR0), 3-87

Interrupt Mask Register 2

(IMR2), 3-109

Attention (ATN) line, GPIB, C-9

Auxiliary Command Register (AUXCR),

3-32 to 3-40

Chip Reset (ch_rst), 3-38

Clear DAC Holdoff (nonvalid), 3-34

Clear DAC Holdoff (valid), 3-34

Clear Disable IMR2, IMR1, And

IMR0 Interrupts (dai), 3-36

Clear Force Group Execute Trigger

(~fget), 3-35

Clear Holdoff On All Data

(~hdfa), 3-34

Clear Holdoff On END Only

(~hdfe), 3-35

Clear Listen Only (~lon), 3-36

Clear Page-In Registers (clrpi), 3-40

Clear Parallel Poll Flag (~ist), 3-39

Clear Return to Local (~rtl), 3-35

Clear Short T1 Delay (~stdl), 3-37

Clear Software Reset (~swrst), 3-34

Clear Talk Only (~ton), 3-36

Clear Very Short T1 Delay

(~vstdl), 3-37

New Byte Available False

TNT4882 Programmer Reference I-2



National Instruments Corp.

Index

(nbaf), 3-35

Page-In Accessory Register

(piaccr), 3-40

Page-In Bus Register (pibcr), 3-39

Page-In End-of-String Registers

(pieosr), 3-40

Page-In Interrupt Mask Register 2

(piimr2), 3-39

Pass Through Next Secondary

(pts), 3-37

Release RFD Holdoff (rhdf), 3-34

Request rsv False (reqf), 3-38

Request rsv True (reqt), 3-38

Send EOI With The Next Byte

(feoi), 3-36

Set Disable IMR2, IMR1, And IMR0

Interrupts (dai), 3-36

Set Force Group Execute Trigger

(fget), 3-35

Set Holdoff On All Data (hdfa), 3-34

Set Holdoff On END Only

(hdfe), 3-35

Set Listen Only (lon), 3-36

Set Parallel Poll Flag (ist), 3-39

Set Return to Local (rtl), 3-35

Set Short T1 Delay (stdl), 3-37

Set Software Reset (swrst), 3-34

Set Talk Only (ton), 3-36

Set Very Short T1 Delay (vstdl), 3-37 summary of commands (table), 3-32 to 3-33

Switch To 7210 Mode

(sw7210), 3-38

Auxiliary Mode Register (AUXMR),

3-41 to 3-50

Chip Reset, 3-45

Clear ADSC, 3-49

Clear ATNI, 3-49

Clear DEC, 3-49

Clear DET, 3-48

Clear END, 3-49

Clear ERR, 3-49

Clear IFCI, 3-49

Clear LOKC, 3-49

Clear Parallel Poll Flag (ist), 3-44

Clear REMC, 3-49

Clear SYNC, 3-50

Finish Handshake (rhdf), 3-45 hidden registers (table), 3-4 to 3-5

Immediate Execute Power-On

(pon), 3-44

Immediate Holdoff, 3-48

New Byte Available False

(nbaf), 3-47

Nonvalid Secondary Command Or

Address (nonvalid), 3-46

Page-In Additional Registers

(page-in), 3-48

Request rsv True (reqt), 3-48

Return to Local (rtl), 3-46

Send EOI (seoi), 3-46

Set Parallel Poll Flag (ist), 3-44

Set SYNC, 3-50 summary of commands (table), 3-42 to 3-43

Switch to 9914A Mode, 3-47

Trigger (trig), 3-46

Unlisten (lul), 3-47

Untalk (lut), 3-46

Valid Secondary Command Or

Address (valid), 3-47

Auxiliary Register A (AUXRA), 3-51 to 3-52

Auxiliary Register B (AUXRB), 3-53 to 3-54

Auxiliary Register E (AUXRE), 3-55



National Instruments Corp.

I-3 TNT4882 Programmer Reference

Index

Auxiliary Register F (AUXRF), 3-56

Auxiliary Register G (AUXRG), 3-57 to 3-58

Auxiliary Register I (AUXRI), 3-59 to 3-60

Auxiliary Register J (AUXRJ), 3-61 to 3-62

B

BBUS_OEN signal, 5-3

BBUSN signal, 5-3

BCR (Bus Control Register)/BSR (Bus

Status Register), 3-63

BEFN bit, Status 2 Register

(STS2), 3-132

BFFN bit, Status 2 Register (STS2), 3-132

BHEN_N signal, 6-3

BI bit, Interrupt Status Register 0

(ISR0), 3-89

BI IE bit, Interrupt Mask Register 0

(IMR0), 3-89

BIN bit

Accessory Register A

(ACCRA), 3-12

Auxiliary Register A

(AUXRA), 3-51 bit descriptions

8-bit versus 16-bit accesses, 3-10

16/8N, 3-68, 3-132

9914 and 7210 registers with identical names, 3-11

A[5-1], 3-23

A/BN, 3-66

ACRDY, 3-124

AD[5-0 -- 1-0], 3-24

AD[5-1], 3-22

AD[5-1 -- 1-1], 3-25

TNT4882 Programmer Reference I-4

ADHS, 3-124

ADSC, 3-106

ADSC IE, 3-106

AEFN, 3-132

AEHS, 3-124

AFFN, 3-132

ANHS1, 3-124

ANHS2, 3-124

APT, 3-93 to 3-94, 3-100

APT IE, 3-93 to 3-94, 3-100

ARS, 3-22

ATN, 3-29, 3-63

ATN*, 3-26

ATNI, 3-87, 3-109

ATNI IE, 3-87, 3-109

BEFN, 3-132

BFFN, 3-132

BI, 3-89

BI IE, 3-89

BIN, 3-12, 3-51

BO, 3-89

BO IE, 3-89

BTO, 3-86, 3-109

CCEN, 3-67

CHES, 3-58

CPT, 3-92

CPT ENABLE, 3-54

CPT IE, 3-92 dal, 3-23 dat, 3-23

DAV, 3-63, 3-130

DCAS, 3-101

DCAS IE, 3-101

DEC, 3-95

DEC IE, 3-95

DET, 3-94

DET IE, 3-94

DG[A-B], 3-81



National Instruments Corp.

DHADC, 3-14, 3-55

DHADT, 3-14, 3-55

DHALA, 3-15, 3-56

DHALL, 3-15, 3-56

DHATA, 3-15, 3-56

DHDC, 3-55

DHDT, 3-55

DHUNTL, 3-15, 3-56

DI, 3-97

DI IE, 3-97

DIO[8-0], 3-75

DIO[8-1], 3-77

DL, 3-22

DL0, 3-24

DL1, 3-25

DMAE, 3-16

DMAEN, 3-19

DMAI, 3-89, 3-105

DMAO, 3-88, 3-104 to 3-105

DO, 3-96 to 3-97

DO IE, 3-96 to 3-97

DONE, 3-113, 3-129

DONE IE, 3-113

DRQ, 3-129

DT, 3-22

DT0, 3-24

DT1, 3-25 edpa, 3-23

END, 3-90

END IE, 3-90, 3-94 to 3-95

END RX, 3-94 to 3-95

EOI, 3-25, 3-63

EOS, 3-86, 3-109

EOS[7-0], 3-78

ERR, 3-95 to 3-96, 3-99

ERR IE, 3-95 to 3-96, 3-99

GET, 3-98 to 3-99

GET IE, 3-98 to 3-99



National Instruments Corp.

Index

GO2SIDS, 3-83

GSYNC, 3-130 to 3-131

HALT, 3-130

HLDA, 3-52

HLDE, 3-52

HSE, 3-117

IFC, 3-63, 3-102

IFC IE, 3-102

IFCI, 3-86

IFCI IE, 3-86

IN, 3-66, 3-129

INT, 3-103 to 3-104, 3-111

INT0, 3-88

INT1, 3-89

INTEN, 3-114

INTSRC2, 3-112

INTSRC2 IE, 3-112

ISS, 3-13, 3-53

KEYCLK, 3-115

KEYDATA, 3-116

KEYDATEN, 3-116

KEYDQ, 3-74

KEYRST*, 3-116

LA, 3-27, 3-30

LLO, 3-29

LLOC, 3-109

LLOC IE, 3-109

LOK, 3-104

LOKC, 3-105

LOKC IE, 3-105

LPAS, 3-27, 3-29

MA, 3-101

MA IE, 3-101

MAC, 3-91

MAC IE, 3-91

MJMN, 3-28

MODE, 3-74

MSTD, 3-115

I-5 TNT4882 Programmer Reference

Index nba, 3-84 to 3-85, 3-107, 3-124

NDAC, 3-63

NEF, 3-112

NEF IE, 3-112

NFF, 3-112

NFF IE, 3-112

NL, 3-85, 3-108

NLEN, 3-86, 3-109

NOAS, 3-118

NODMA, 3-83

NOTS, 3-118

NO_TSETUP, 3-81 to 3-82

NRFD, 3-63

NTNL, 3-57 to 3-58

ONEC, 3-83

P[3-1], 3-120

PEND, 3-128

PMT_W_EOS, 3-82

PP1, 3-16

PP2, 3-59

PP8-PP1, 3-122

PT1_[4-0], 3-123

PT1_ENA, 3-123

REM, 3-29, 3-104

REMC, 3-105 to 3-106

REMC IE, 3-105 to 3-106

REN, 3-63

REOS, 3-12, 3-52

RLC, 3-90

RLC IE, 3-90 rsv/RQS, 3-128

S, 3-120

S[6-1], 3-127 to 3-128

S8, 3-127

SH1A SH1B, 3-125

SISB, 3-60

SLOW, 3-117 to 3-118

SPAS, 3-90

TNT4882 Programmer Reference I-6

SPAS IE, 3-90

SPEOI, 3-13, 3-54

SPMS, 3-26

SRQ, 3-63

STBO, 3-85, 3-108

STBO IE, 3-108

STOP, 3-112, 3-129 to 3-130

STOP IE, 3-112

SWAP, 3-9 to 3-10, 3-115

SYNC, 3-87

SYNC IE, 3-87

T12_[4-0], 3-133

T17_[4-0], 3-135

TA, 3-27 to 3-28, 3-30 to 3-31

TIM/BYTN, 3-67 to 3-68

TLCHLTE, 3-66

TLCINT, 3-113

TLCINT IE, 3-113

TM[3-0], 3-17 to 3-18

TMOE, 3-67

TO, 3-87, 3-110

TO IE, 3-87, 3-110

TPAS, 3-27, 3-30

TRI, 3-54

U, 3-119 ulpa, 3-31

UNC, 3-99 to 3-100

UNC IE, 3-99 to 3-100

USTD, 3-16, 3-59

V[3-0], 3-74

WRAP, 3-118

XEOS, 3-12, 3-51

BO bit, Interrupt Status Register 0

(ISR0), 3-89

BO IE bit, Interrupt Mask Register 0

(IMR0), 3-89

Board Interrupt Register (INTR), 3-114

BTO bit



National Instruments Corp.

Index

Interrupt Mask Register 0

(IMR0), 3-86

Interrupt Mask Register 2

(IMR2), 3-109

BURST_RDN pin, 5-5

Bus Control Register (BCR)/Bus Status

Register (BSR), 3-63

C

capabilities of INT4882 interface (table),

1-1 to 1-2

Carry Cycle Register (CCR), 3-64

CCEN bit, Configuration Register (CFG),

3-67

CCR (Carry Cycle Register), 3-64

CDOR (Command/Data Out

Register), 3-65

CHES bit, Auxiliary Register G

(AUXRG), 3-58 chip initialization, 4-1 to 4-3 configuring TNT4882 clearing local power-on message, 4-3

GPIB operation, 4-2 to 4-3 one-chip mode, 4-2 placing TNT4882 in Turbo+7210 mode, 4-1 to 4-2 resetting Turbo488 circuitry, 4-1

Chip Reset (ch_rst) command,

AUXCR, 3-38

Chip Reset command, AUXMR, 3-45

Chip Signature Register (CSR), 3-74

Clear ADSC command, 3-49

Clear ATNI command, 3-49

Clear DAC Holdoff (nonvalid) command, 3-34

Clear DAC Holdoff (valid) command, 3-34

Clear DEC command, 3-49

Clear DET command, 3-48

Clear Disable IMR2, IMR1, And IMR0

Interrupts (dai) command, 3-36

Clear END command, 3-49

Clear ERR command, 3-49

Clear Force Group Execute Trigger

(~fget) command, 3-35

Clear Holdoff On All Data (~hdfa) command, 3-34

Clear Holdoff On END Only (~hdfe) command, 3-35

Clear IFCI command, 3-49

Clear Listen Only (~lon) command, 3-36

Clear LOKC command, 3-49

Clear Page-In Registers (clrpi) command, 3-40

Clear Parallel Poll Flag (ist) command

Auxiliary Command Register

(AUXCR), 3-39

Auxiliary Mode Register

(AUXMR), 3-44

Clear REMC command, 3-49

Clear Request Service bit 2 (~rsv2) command, 3-37

Clear Return to Local (~rtl) command, 3-35

Clear Short T1 Delay (~stdl) command, 3-37

Clear Software Reset (~swrst) command, 3-34

Clear SYNC command, 3-50

Clear Talk Only (~ton) command, 3-36

Clear Very Short T1 Delay (~vstdl) command, 3-37 clearing devices, C-28 clrpi (Clear Page-In Registers)



National Instruments Corp.

I-7 TNT4882 Programmer Reference

Index command, 3-40

CMDR. See Command Register (CMDR).

CNT0 (Count 0 Register), 3-71

CNT1 (Count 1 Register), 3-71

CNT2 (Count 2 Register), 3-71

CNT3 (Count 3 Register), 3-71 command messages, GPIB. See also messages, GPIB.

data and command messages, C-17 unaddressing, C-19

Command Pass Through Register

(CPTR), 3-73

Command Register (CMDR)

GO, 3-69

RESET FIFO, 3-70

SOFT RESET, 3-70

STOP, 3-70

Command/Data Out Register

(CDOR), 3-65 commands. See Auxiliary Command

Register (AUXCR); Auxiliary Mode

Register (AUXMR); Standard

Commands for Programmable

Instrumentation (SCPI).

Configuration Register (CFG), 3-66 to 3-68

Controller. See GPIB Controller.

count registers

16-bit mode, 3-72

32-bit mode, 3-72

Count 0 Register (CNT0), 3-71

Count 1 Register (CNT1), 3-71

Count 2 Register (CNT2), 3-71

Count 3 Register (CNT3), 3-71 description, 3-72 count termination method, GPIB, C-20 to C-21

CPT bit, Interrupt Status Register 1

(ISR1), 3-92

CPT ENABLE bit, Auxiliary Register B

(AUXRB), 3-54

CPT IE bit, Interrupt Mask Register 1

(IMR1), 3-92

CPT[7-0] bits, Command Pass Through

Register (CPTR), 3-73

CPTR (Command Pass Through

Register), 3-73

CPUACC pin, 5-3 to 5-4 crystal oscillator, 5-9

CSN pin, 5-3

CSR (Chip Signature Register), 3-74 customer communication, xvii, H-1

D

D15_8_OEN and D7_0_OEN signals, 6-2

DAC holdoffs, 4-16 to 4-17

DACKN pin generic pin configuration, 5-5

ISA pin configuration, 6-4

~dai (Clear Disable IMR2, IMR1, And

IMR0 Interrupts) command, 3-36 dai (Set Disable IMR2, IMR1, And IMR0

Interrupts) command, 3-36 dal bit, Address Register (ADR), 3-23 dat bit, Address Register (ADR), 3-23 data and command messages. See command messages, GPIB.

data bus control signals generic pin configuration, 5-3 to 5-5

ABUSN and BBUSN, 5-3

ABUS_OEN and BBUS_OEN,

5-3

ISA pin configuration

BHEN_N, 6-3

TNT4882 Programmer Reference I-8



National Instruments Corp.

Index

D15_8_OEN and D7_0_OEN,

6-2 data buses, 5-1 to 5-2 generic pin configuration

8-bit DMA accesses, 5-2

8-bit I/O accesses, 5-1

16-bit DMA accesses, 5-2

16-bit I/O accesses, 5-2 byte lane table (I/O accesses), 5-2

ISA pin configuration

DATA7-0, 6-2

DATA15-8, 6-1 to 6-2

Data In Register (DIR), 3-76 data lines, GPIB, C-7 data messages, GPIB, C-17. See also messages, GPIB.

data transfers. See GPIB data transfers.

Data Valid (DAV) line, GPIB, C-12

DATA15-8 and DATA7-0 signals, 6-1 to 6-2

DAV bit

Bus Control Register (BCR)/Bus

Status Register (BSR), 3-63

Status 1 Register (STS1), 3-130

DCAS bit, Interrupt Status Register 1

(ISR1), 3-101

DCAS IE bit, Interrupt Mask Register 1

(IMR1), 3-101

DCAS--Device Clear pin, 5-8

DCR (DIO Control Register), 3-75

DEC bit, Interrupt Status Register 1

(ISR1), 3-95

DEC IE bit, Interrupt Mask Register 1

(IMR1), 3-95

DET bit, Interrupt Status Register 1

(ISR1), 3-94

DET IE bit, Interrupt Mask Register 1

(IMR1), 3-94 device status reporting, 4-13 to 4-15. See also parallel polling; serial polling.

requesting service, 4-13 responding to parallel polls, 4-14 to 4-15 responding to serial polls, 4-14 devices addressing. See GPIB addressing.

clearing, 4-20, C-28 triggering, 4-20, C-28

DG[A-B] bits, High-Speed Enable

Register (HIER), 3-81

DHADC bit

Accessory Register E

(ACCRE), 3-14

Auxiliary Register E (AUXRE), 3-55

DHADT bit

Accessory Register E

(ACCRE), 3-14

Auxiliary Register E (AUXRE), 3-55

DHALA bit

Accessory Register F

(ACCRF), 3-15

Auxiliary Register F (AUXRF), 3-56

DHALL bit

Accessory Register F

(ACCRF), 3-15

Auxiliary Register F (AUXRF), 3-56

DHATA bit

Accessory Register F

(ACCRF), 3-15

Auxiliary Register F (AUXRF), 3-56

DHDC bit, Auxiliary Register E

(AUXRE), 3-55

DHDT bit, Auxiliary Register E

(AUXRE), 3-55

DHUNTL bit



National Instruments Corp.

I-9 TNT4882 Programmer Reference

Index

Accessory Register F (ACCRF), 3-15

Auxiliary Register F (AUXRF), 3-56

DI bit, Interrupt Status Register 1

(ISR1), 3-97

DI IE bit, Interrupt Mask Register 1

(IMR1), 3-97

DIO Control Register (DCR), 3-75

DIO Status Register (DSR), 3-77

DIO[8-0] bits, DIO Control Register

(DCR), 3-75

DIO[8-1] bits

Command/Data Out Register

(CDOR), 3-65

Data In Register (DIR), 3-76

DIO Status Register (DSR), 3-77

DIR (Data In Register), 3-76 discrete oscillator circuit component values (table), 3-10 quartz crystal specifications

(table), 3-10 recommended circuit for third overtone mode crystal

(illustration), 3-9

DL bit, ADR (Address Register), 3-22

DL0 bit, Address Register 0

(ADR0), 3-24

DL1 bit, Address Register 1

(ADR1), 3-25

DMA accesses. See data buses.

DMAE bit, Accessory Register I

(ACCRI), 3-16

DMAEN bit, Accessory Write Register

(ACCWR), 3-19

DMAI bit

Interrupt Mask Register 0

(IMR0), 3-89

Interrupt Mask Register 2

(IMR2), 3-105

DMAO bit

Interrupt Mask Register 0

(IMR0), 3-88

Interrupt Mask Register 2 (IMR2),

3-104 to 3-105

DO bit, Interrupt Status Register 1

(ISR1), 3-96 to 3-97

DO IE bit, Interrupt Mask Register 1

(IMR1), 3-96 to 3-97 documentation conventions used in manual, xvi mnemonics key, G-1 to G-13 organization of manual, xv-xvi related documentation, xvi-xvii

DONE bit

Interrupt Status Register 3

(ISR3), 3-113

Status 1 Register (STS1), 3-129

DONE IE bit, Interrupt Mask Register 3

(IMR3), 3-113

DRQ bit, Status 1 Register (STS1), 3-129

DRQ pin asserting at low clock frequencies, B-4 generic pin configuration, 5-5

ISA pin configuration, 6-3 to 6-4

DS1204 key reading, 4-21 writing, 4-21

DSR (DIO Status Register), 3-77

DT bit, ADR (Address Register), 3-22

DT0 bit, Address Register 0

(ADR0), 3-24

DT1 bit, Address Register 1

(ADR1), 3-25

TNT4882 Programmer Reference I-10



National Instruments Corp.

Index

E

edpa bit, Address Register (ADR), 3-23 electrical specifications, GPIB, C-13 to C-14

END bit, Interrupt Status Register 0

(ISR0), 3-90

END IE bit

Interrupt Mask Register 0

(IMR0), 3-90

Interrupt Mask Register 1 (IMR1),

3-94 to 3-95

END RX bit, Interrupt Status Register 1

(ISR1), 3-94 to 3-95

End-of-String Register (EOSR), 3-78

End-or-Identify (EOI) line, GPIB, C-10

EOI, sending (seoi) command, 3-46

EOI bit

Address Register 1 (ADR1), 3-25

Bus Control Register (BCR)/Bus

Status Register (BSR), 3-63

EOI (End-or-Identify) line, GPIB, C-10

EOI termination method, GPIB, C-20

EOS bit

Interrupt Status Register 0

(ISR0), 3-86

Interrupt Status Register 2

(ISR2), 3-109

EOS termination method, GPIB, C-20

EOS[7-0] bits, End-of-String Register

(EOSR), 3-78

EOSR (End-of-String Register), 3-78

ERR bit, Interrupt Status Register 1

(ISR1) one-chip mode, Turbo+7210 mode,

3-95 to 3-96

Turbo+9914 mode, 3-99

ERR IE bit, Interrupt Mask Register 1

(IMR1) one-chip mode, Turbo+7210 mode,

3-95 to 3-96

Turbo+9914 mode, 3-99

ESB (Event Status Bit), C-23

Event Status Register (ESR), C-23, C-24 extended addressing. See GPIB addressing.

F

fax technical support, H-1 feoi (Send EOI With The Next Byte) command, 3-36

~fget (Clear Force Group Execute

Trigger) command, 3-35 fget (Set Force Group Execute Trigger) command, 3-35

FIFO_RDY pin, 5-6

FIFO(A/B) (First-In First-Out Buffer) register, 3-79 to 3-80

Finish Handshake (rhdf), AUXMR, 3-45

First-In First-Out Buffer (FIFO(A/B)),

3-79 to 3-80 frequencies, less than 40 MHz, A-1

G

General Purpose Interface Bus. See GPIB.

generic pin configuration

CPU interface pins data bus control signals, 5-3 to 5-5

ABUSN and BBUSN, 5-3

ABUS_OEN and

BBUS_OEN, 5-3 register select pins, 5-3 data buses, 5-1 to 5-2

8-bit DMA accesses, 5-2

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National Instruments Corp.

I-11 TNT4882 Programmer Reference

Index

8-bit I/O accesses, 5-1

16-bit DMA accesses, 5-2

16-bit I/O accesses, 5-2 byte lane table (I/O accesses), 5-2

FIFO_RDY, 5-6 illustration, 5-1

INTR, 5-6 mode pins

MODE, 5-6, 5-7

RESETN, 5-7

SWAPN, 5-6, 5-7

PAGED, 5-6 register select pins

ADDR4-0 and CSN pins, 5-3

BURST_RDN, 5-5

CPUACC and RDY1, 5-3 to 5-4

DACKN, 5-5

DRQ, 5-5

RDN and WRN, 5-3 configuring the TNT4882 for, A-1

GPIB device status pins, 5-7 to 5-8

DCAS--Device Clear pin, 5-8

LACDS--Listener Addressed signal, 5-7

REM--Remote signal, 5-8

TADCS--Talker Addressed signal, 5-7

TRIG--Trigger signal, 5-8

GPIB signal pins, 5-8 to 5-10 key pins, 5-8 to 5-9 oscillator pins, 5-9 to 5-10 crystal oscillator, 5-9 discrete oscillator circuit, 5-9 to 5-10

GET bit, Interrupt Status Register 1

(ISR1), 3-98 to 3-99

GET IE bit, Interrupt Mask Register 1

(IMR1), 3-98 to 3-99

GO command, 3-69

GO2SIDS bit, Handshake Select Register

(HSSEL), 3-83

GPIB addressing protocol, C-17 to C-18.

See also GPIB addressing.

examples, C-18 reading multiline interface command messages table, C-19 secondary addressing, C-19 unaddressing command messages, C-19 clearing devices, C-28

Controller. See GPIB Controller.

data and command messages, C-17 data lines, C-7 handshake lines, C-11 to C-13

Data Valid (DAV), C-12

Not Data Accepted

(NDAC), C-12

Not Ready For Data

(NRFD), C-11 three-wire handshake process,

C-12 to C-13 hardware configuration, C-4 to C-6 history, C-1

IEEE 488.1 specification, C-2

IEEE 488.2 specification, C-2 to C-3 interface management lines, C-8 to C-11

Attention (ATN), C-9

End-or-Identify (EOI), C-10

Interface Clear (IFC), C-8

Remote Enable (REN), C-10

TNT4882 Programmer Reference I-12

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National Instruments Corp.

Index

Service Request (SRQ), C-11

Listeners. See Listeners.

parallel polling, C-25 to C-27. See also parallel polling.

configuring devices, C-26 determining PPE message, C-27 determining value of PPR message, C-26 example exchange of messages

(illustration), C-25 overview, C-25 physical representation of PPR message, C-27 physical and electrical specifications,

C-13 to C-14

SCPI specification, C-3 to C-4 serial polling. See also serial polling.

ESR and SRE registers, C-23 to C-24 serial polling devices, C-21 to C-22 servicing SRQs, C-21 status byte model for IEEE

488.1, C-23 status byte model for IEEE 488.2,

A-23 to C-24 signals and lines, C-7

Talkers. See Talkers.

termination methods, C-19 to C-21 combinations of methods, C-21 count method, C-20 to C-21

EOI method, C-20

EOS method, C-20 triggering devices, C-28

GPIB addressing, 4-3 to 4-7 addressing modes extended dual addressing, 3-21 extended single addressing, 3-20 listen only (lon), 3-21 no addressing, 3-20 normal dual addressing, 3-20 talk only (ton), 3-21 addressing protocol, C-17 to C-18 examples, C-18 format of address command messages, C-17 primary address, C-17 reading multiline interface command messages table, C-19 secondary addressing, C-19 unaddressing command messages, C-19 unique addresses, C-17 logical and physical devices, 4-3 normal and extended addressing, 4-3 to 4-4 one logical device, 4-4 setting, 4-2 three or more logical devices, 4-6 to 4-7 two logical devices, 4-4 to 4-6

GPIB Controller. See also System

Controller.

Controller-In-Charge (CIC), C-14 defining System Controller, C-14 responsibilities, C-14

GPIB data transfers, 4-7 to 4-13 conducting the transfer, 4-8 to 4-11

DMA, 4-11 flow chart of polled transfers

(illustration), 4-9

HS488

IEEE 488.1 and HS488 transfers

(illustration), D-3 sequence of events, D-2 to D-3

Talker and Listener are HS488

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National Instruments Corp.

I-13 TNT4882 Programmer Reference

Index capable, D-4 to D-5

Talker is HS488 capable but

Listener is not, D-5 to D-6

Talker is not HS488 capable, D-6 initialization, 4-7 to 4-8 interrupt-driven status reporting, 4-11 post termination, 4-12 to 4-13 programmed I/O, 4-9 to 4-11 termination, 4-12

GPIB device status pins, 5-7 to 5-8

DCAS--Device Clear pin, 5-8

LACDS--Listener Addressed signal, 5-7

REM--Remote signal, 5-8

TADCS--Talker Addressed signal, 5-7

TRIG--Trigger signal, 5-8

GPIB handshake lines, C-11 to C-13

Data Valid (DAV), C-12

Not Data Accepted (NDAC), C-12

Not Ready For Data (NRFD), C-11 three-wire handshake process, C-12 to C-13

GPIB handshake parameters, setting, 4-3.

See also T1 delay generation.

GPIB operation, configuring TNT4882 for, 4-2

GPIB rdy message and RFD holdoffs,

4-15 to 4-16 data byte RFD holdoffs, 4-16 normal mode, 4-16

RFD holdoff on all data (hlda) mode, 4-16

RFD holdoff on END (hlde) mode, 4-16 generating rdy message, 4-15 immediate RFD holdoff, 4-15 to 4-16

GPIB signal pins, 5-8 to 5-10 key pins, 5-8 to 5-9 oscillator pins, 5-9 to 5-10 crystal oscillator, 5-9 discrete oscillator circuit, 5-9 to 5-10

GSYNC bit, Status 1 Register (STS1),

3-130 to 3-131

H

HALT bit, Status 1 Register

(STS1), 3-130 handshake lines, GPIB. See GPIB handshake lines.

handshake parameters, setting, 4-3

Handshake Select Register

(HSSEL), 3-83 hardware configuration, GPIB, C-4 to C-6 hardware interrupts

INTR pin, 4-18

TLCINT signal, 4-18 to 4-19

TNT4882_INT signal, 4-18

~hdfa (Clear Holdoff On All Data) command, 3-34 hdfa (Set Holdoff On All Data) command, 3-34

~hdfe (Clear Holdoff On END Only) command, 3-35 hdfe (Set Holdoff On END Only) command, 3-35

Hewlett-Packard Interface Bus

(HP-IB), C-1 hidden registers one-chip mode/Turbo+7210 mode,

3-4 to 3-5

TNT4882 Programmer Reference I-14

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National Instruments Corp.

Index

Turbo+9914 mode, 3-9 to 3-10

High-Speed Enable Register (HIER),

3-81 to 3-82

HLDA bit, Auxiliary Register A

(AUXRA), 3-52 hlda mode, 4-16

HLDE bit, Auxiliary Register A

(AUXRA), 3-52 hlde mode, 4-16 holdoffs

DAC holdoffs, 4-16 to 4-17

GPIB rdy message and RFD holdoffs, 4-15 to 4-16 data byte RFD holdoffs, 4-16 normal mode, 4-16

RFD holdoff on all data

(hlda) mode, 4-16

RFD holdoff on END (hlde) mode, 4-16 generating rdy message, 4-15 immediate RFD holdoff, 4-15 to 4-16

HS488 transfer holdoffs

Listener wants to resume threewire handshake, D-8

Listener's buffer nearly full, D-7

Talker sends EOI or EOS, D-9

HS488 advantages, D-1 to D-2 data transfers

IEEE 488.1 and HS488 transfers

(illustration), D-3 sequence of events, D-2 to D-3

Talker and Listener are HS488 capable, D-4 to D-5

Talker is HS488 capable but

Listener is not, D-5 to D-6

Talker is not HS488 capable, D-6 clock frequency, B-1 definition, D-1

IEEE 488.1 requirements if T1 delay is 350 ns, D-2 limitations (table), D-2 objectives, D-1 system configuration, D-9 system requirements, D-2 transfer holdoffs

Listener wants to resume threewire handshake, D-8

Listener's buffer nearly full, D-7

Talker sends EOI or EOS, D-9

HSE bit, Miscellaneous Register

(MISC), 3-117

HSSEL (Handshake Select

Register), 3-83

HSTS definition, 4-22

I

IEEE 488 Bus. See GPIB.

IEEE 488.1 standard. See also HS488.

compatibility of TNT4882, D-1 history, C-1 problems with IEEE 488.1 compatible devices, C-2 specification, C-2 status byte model for serial polling, C-23

IEEE 488.2 service requesting, 4-13

IEEE 488.2 standard compatibility of TNT4882, D-1 history, C-1 specification, C-2 to C-3 status byte model for serial polling,

C-23 to C-24

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National Instruments Corp.

I-15 TNT4882 Programmer Reference

Index

IFC bit

Bus Control Register (BCR)/Bus

Status Register (BSR), 3-63

Interrupt Status Register 1

(ISR1), 3-102

IFC IE bit, Interrupt Mask Register 1

(IMR1), 3-102

IFC (Interface Clear) line, GPIB, C-8

IFCI bit, Interrupt Status Register 0

(ISR0), 3-86

IFCI IE bit, Interrupt Mask Register 0

(IMR0), 3-86

Immediate Execute Power-On (pon) command, 3-44

Immediate Holdoff command, 3-48

IMR0 (Interrupt Mask Register 0) one-chip mode, Turbo+7210 mode,

3-84 to 3-87

Turbo+9914 mode, 3-88 to 3-91

IMR1 (Interrupt Mask Register 1) one-chip mode, Turbo+7210 mode,

3-92 to 3-97

Turbo+9914 mode, 3-98 to 3-102

IMR2 (Interrupt Mask Register 2) one-chip mode, Turbo+7210 mode,

3-103 to 3-106

Turbo+9914 mode, 3-107 to 3-110

IMR3 (Interrupt Mask Register 3), 3-111 to 3-113

IN bit

Configuration Register (CFG), 3-66

Status 1 Register (STS1), 3-129 initialization sequence. See chip initialization.

INT bit

Interrupt Status Register 2 (ISR2),

3-103 to 3-104

Interrupt Status Register 3

(ISR3), 3-111

INT0 bit, Interrupt Status Register 0

(ISR0), 3-88

INT1 bit, Interrupt Status Register 0

(ISR0), 3-89

INTEN bit, Board Interrupt Register

(INTR), 3-114

Interface Clear (IFC) line, GPIB, C-8 interface management lines, GPIB, C-8 to C-11

Attention (ATN), C-9

End-or-Identify (EOI), C-10

Interface Clear (IFC), C-8

Remote Enable (REN), C-10

Service Request (SRQ), C-11 interrupt bits, enabling, 4-3

Interrupt Mask Register 0 (IMR0) one-chip mode, Turbo+7210 mode,

3-84 to 3-87

Turbo+9914 mode, 3-88 to 3-91

Interrupt Mask Register 1 (IMR1) one-chip mode, Turbo+7210 mode,

3-92 to 3-97

Turbo+9914 mode, 3-98 to 3-102

Interrupt Mask Register 2 (IMR2) one-chip mode, Turbo+7210 mode,

3-103 to 3-106

Turbo+9914 mode, 3-107 to 3-110

Interrupt Mask Register 3 (IMR3), 3-111 to 3-113

Interrupt Status Register 0 (ISR0) one-chip mode, Turbo+7210 mode,

3-84 to 3-87

Turbo+9914 mode, 3-88 to 3-91

Interrupt Status Register 1 (ISR1) one-chip mode, Turbo+7210 mode,

3-92 to 3-97

Turbo+9914 mode, 3-98 to 3-102

TNT4882 Programmer Reference I-16



National Instruments Corp.

Index

Interrupt Status Register 2 (ISR2) one-chip mode, Turbo+7210 mode,

3-103 to 3-106

Turbo+9914 mode, 3-107 to 3-110

Interrupt Status Register 3 (ISR3), 3-111 to 3-113 interrupts, hardware. See hardware interrupts.

INTR (Board Interrupt Register), 3-114

INTR pin asserting, A-1 generic pin configuration, 5-6

ISA pin configuration, 6-4

INTSRC2 bit, Interrupt Status Register 3

(ISR3), 3-112

INTSRC2 IE bit, Interrupt Mask Register

3 (IMR3), 3-112

I/O accesses. See data buses.

IOCHRDY pin, ISA pin configuration, 6-4

IOCS16N pin, ISA pin configuration, 6-5

IORN, IOWN pins, 6-3

ISA pin configuration

CPU interface pins

DACKN, 6-4 data bus control signals

BHEN_N, 6-3

D15_8_OEN and

D7_0_OEN, 6-2 data buses byte lane table, 6-2

DATA7-0, 6-2

DATA15-8, 6-1 to 6-2

DRQ, 6-3 to 6-4 illustration, 6-1

INTR, 6-4

IOCHRDY, 6-4

IOCS16N, 6-5

MODE, 6-5 register select pins

ADDR4-0, 6-3

ADDR9-5, SW9-5,

AEN_N, 6-3

IORN, IOWN, 6-3

RESET, 6-5

SENSE_8_16N, 6-5 other pins, 6-5

ISR0 (Interrupt Status Register 0) one-chip mode, Turbo+7210 mode,

3-84 to 3-87

Turbo+9914 mode, 3-88 to 3-91

ISR1 (Interrupt Status Register 1) one-chip mode, Turbo+7210 mode,

3-92 to 3-97

Turbo+9914 mode, 3-98 to 3-102

ISR2 (Interrupt Status Register 2) one-chip mode, Turbo+7210 mode,

3-103 to 3-106

Turbo+9914 mode, 3-107 to 3-110

ISR3 (Interrupt Status Register 3), 3-111 to 3-113

ISS bit

Accessory Register B

(ACCRB), 3-13

Auxiliary Register B

(AUXRB), 3-53

~ist (Clear Parallel Poll Flag) command

Auxiliary Command Register

(AUXCR), 3-39

Auxiliary Mode Register

(AUXMR), 3-44 ist (Set Parallel Poll Flag) command

Auxiliary Command Register

(AUXCR), 3-39

Auxiliary Mode Register

(AUXMR), 3-44



National Instruments Corp.

I-17 TNT4882 Programmer Reference

Index ist message, 4-14

K

Key Control Register (KEYREG), 3-115 to 3-116

KEY pins generic pin configuration, 5-8 to 5-9 reading DS1204 key, 4-21 using as general purpose I/O pins, 4-21 writing DS1204 key, 4-21

KEYCLK bit, Key Control Register

(KEYREG), 3-115

KEYDATA bit, Key Control Register

(KEYREG), 3-116

KEYDATEN bit, Key Control Register

(KEYREG), 3-116

KEYDQ bit, Chip Signature Register

(CSR), 3-74

KEYREG (Key Control Register), 3-115 to 3-116

KEYRST* bit, Key Control Register

(KEYREG), 3-116

L

LA bit, Address Status Register (ADSR)

Turbo+7210 mode, 3-27

Turbo+9914 mode, 3-30

LACDS--Listener Addressed signal, 5-7

Listeners. See also GPIB Controller;

Talkers.

HS488 data transfers

Talker and Listener are HS488 capable, D-4 to D-5

Talker is HS488 capable but

Listener is not, D-5 to D-6 programmed implementation, 4-7 properties, C-15 system setup example

(illustration), C-16

LLOC bit, Interrupt Status Register 2

(ISR2), 3-109

LLOC IE bit, Interrupt Mask Register 2

(IMR2), 3-109 local power-on message asserting, 4-2 clearing, 4-2 logical devices, addressing. See GPIB addressing.

LOK bit, Interrupt Status Register 2

(ISR2), 3-104

LOKC bit, Interrupt Status Register 2

(ISR2), 3-105

LOKC IE bit, Interrupt Mask Register 2

(IMR2), 3-105 lon (listen only) addressing mode, 3-21

~lon (Clear Listen Only) command, 3-36 lon (Set Listen Only) command, 3-36

LPAS bit, Address Status Register

(ADSR)

Turbo+7210 mode, 3-27

Turbo+9914 mode, 3-29 lul (Unlisten) command, AUXMR, 3-47 lut (Untalk) command, AUXMR, 3-46

M

MA bit, Interrupt Status Register 1

(ISR1), 3-101

MA IE bit, Interrupt Mask Register 1

(IMR1), 3-101

MAC bit, Interrupt Status Register 0

(ISR0), 3-91

MAC IE bit, Interrupt Mask Register 0

(IMR0), 3-91

TNT4882 Programmer Reference I-18



National Instruments Corp.

Index manual. See documentation.

MAV (Message Available) bit, C-23 messages, GPIB data messages compared with command messages, C-17 format of address command messages, C-17 mnemonics key, G-1 to G-13 multiline interface command messages, F-1 to F-3 unaddressing command messages, C-19

Miscellaneous Register (MISC), 3-117 to 3-118

MJMN bit, Address Status Register

(ADSR), 3-28 mnemonics key, G-1 to G-13

MODE bit, Chip Signature Register

(CSR), 3-74 mode pins

MODE generic pin configuration,

5-6, 5-7

ISA pin configuration, 6-5

RESETN, 5-7

SWAPN, 5-6, 5-7

MSS (Master Summary Status) bit, C-23

MSTD bit, Key Control Register

(KEYREG), 3-115 multiline messages mnemonics and definitions, F-1 to F-3 reading, C-19

N

nba bit

Interrupt Mask Register 2

(IMR2), 3-107

Interrupt Status Register 0 (ISR0),

3-84 to 3-85

Source/Acceptor Status Register

(SASR), 3-124 nbaf (New Byte Available False) command

Auxiliary Command Register

(AUXCR), 3-35

Auxiliary Mode Register

(AUXMR), 3-47

NDAC bit, Bus Control Register (BCR)/

Bus Status Register (BSR), 3-63

NEF bit, Interrupt Status Register 3

(ISR3), 3-112

NEF IE bit, Interrupt Mask Register 3

(IMR3), 3-112

New Byte Available False (nbaf) command

Auxiliary Command Register

(AUXCR), 3-35

Auxiliary Mode Register

(AUXMR), 3-47

NFF bit, Interrupt Status Register 3

(ISR3), 3-112

NFF IE bit, Interrupt Mask Register 3

(IMR3), 3-112

NL bit

Interrupt Status Register 0

(ISR0), 3-85

Interrupt Status Register 2

(ISR2), 3-108

NLEN bit

Interrupt Mask Register 0

(IMR0), 3-86

Interrupt Mask Register 2

(IMR2), 3-109

NOAS bit, Miscellaneous Register

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National Instruments Corp.

I-19 TNT4882 Programmer Reference

Index

(MISC), 3-118

NODMA bit, Handshake Select Register

(HSSEL), 3-83

Nonvalid Secondary Command Or

Address (nonvalid) command,

AUXMR, 3-46 normal addressing. See GPIB addressing.

Not Data Accepted (NDAC) line

GPIB, C-12

Not Ready For Data (NRFD) line,

GPIB, C-11

NOTS bit, Miscellaneous Register

(MISC), 3-118

NO_TSETUP bit, High-Speed Enable

Register (HIER), 3-81 to 3-82

NRFD bit, Bus Control Register (BCR)/

Bus Status Register (BSR), 3-63

NTNL bit, Auxiliary Register G

(AUXRG), 3-57 to 3-58

O

ONEC bit, Handshake Select Register

(HSSEL), 3-83 one-chip mode acceptor handshake holdoffs, 4-15 to 4-16 block diagram, 2-2 changing to another mode illustration, 2-3

Turbo+7210 mode, 2-4 configuring TNT4882 for, 4-2 description, 2-2

GPIB rdy message and RFD holdoffs, 4-15 to 4-16 data byte RFD holdoffs, 4-16 generating rdy message, 4-15 immediate RFD holdoff, 4-15 to 4-16 when to use, 2-2 to 2-3 oscillator pins, 5-9 to 5-10 crystal oscillator, 5-9 discrete oscillator circuit, 5-9 to 5-10 component values (table), 5-10 quartz crystal specifications

(table), 5-10 recommended circuit for third overtone mode crystal

(illustration), 5-9

P

P[3-1] bits, Parallel Poll Register

(PPR), 3-120

PAGED pin, 5-6 paged register, accessing, A-1

Page-In Accessory Register (piaccr) command, 3-40

Page-In Additional Registers (page-in) command, 3-48

Page-In Bus Register (pibcr) command, 3-39

Page-In End-of-String Registers (pieosr) command, 3-40

Page-In Interrupt Mask Register 2

(piimr2) command, 3-39

Page-In state one-chip mode/Turbo+7210 mode,

3-5 to 3-6 how to page in, 3-6 register offsets (table), 3-6 when to use, 3-5

Turbo+9914 mode, 3-10

Parallel Poll Register (PPR)

Turbo+7210 mode, 3-119 to 3-121

Turbo+9914 mode, 3-122

TNT4882 Programmer Reference I-20



National Instruments Corp.

Index parallel polling configuring devices for parallel polls, C-26 determining PPE message, C-27 determining value of PPR message, C-26 example exchange of messages

(illustration), C-25 overview, C-25 physical representation of PPR message, C-27 responding to parallel polls, 4-14 to 4-15 disabling response, 4-15 ist message, 4-14 local configuration, 4-15 remote configuration, 4-14 writing initial parallel poll response, 4-2

Pass Through Next Secondary (pts) command, 3-37

PEND bit, Serial Poll Status Register

(SPSR), 3-128 physical specifications, GPIB, C-13 to C-14 piaccr (Page-In Accessory Register) command, 3-40 pibcr (Page-In Bus Register) command, 3-39 pieosr (Page-In End-of-String Registers) command, 3-40 piimr2 (Page-In Interrupt Mask Register

2) command, 3-39 pin configuration. See generic pin configuration; ISA pin configuration.

PMT_W_EOS bit, High-Speed Enable

Register (HIER), 3-82 polling. See parallel polling; serial polling.

pon (Immediate Execute Power-On) command, 3-44

PP1 bit, Accessory Register I

(ACCRI), 3-16

PP2 bit, Auxiliary Register I

(AUXRI), 3-59

PP8-PP1 bits, Parallel Poll Register

(PPR), 3-122

PPE message, determining, C-27

PPR (Parallel Poll Register)

Turbo+7210 mode, 3-119 to 3-121

Turbo+9914 mode, 3-122

PPR message determining, C-26 physical representation, C-27 primary address, GPIB, C-17

Programmable T1 Register (PT1), 3-123 programmed implementation of Talker or

Listener, 4-7 programming considerations acceptor handshake holdoffs in one-chip mode

DAC holdoffs, 4-16 to 4-17

GPIB rdy message and RFD holdoffs, 4-15 to 4-16 chip initialization, 4-1 to 4-3 configuring TNT4882 clearing local power-on message, 4-3

GPIB operation, 4-2 to 4-3 one-chip mode, 4-2 placing TNT4882 in

Turbo+7210 mode, 4-1 to 4-2 resetting Turbo488 circuitry, 4-1 device clearing, 4-20 device status reporting, 4-13 to 4-15 requesting service, 4-13



National Instruments Corp.

I-21 TNT4882 Programmer Reference

Index responding to parallel polls, 4-14 to 4-15 responding to serial polls, 4-14 device triggering, 4-20

GPIB addressing, 4-3 to 4-7 logical and physical devices, 4-3 normal and extended addressing,

4-3 to 4-4 one logical device, 4-4 three or more logical devices,

4-6 to 4-7 two logical devices, 4-4 to 4-6

GPIB data transfers, 4-7 to 4-13 conducting the transfer, 4-8 to 4-11

DMA, 4-11 flow chart of polled transfers

(illustration), 4-9 initialization, 4-7 to 4-8 interrupt-driven status reporting, 4-11 post termination, 4-12 to 4-13 termination, 4-12 hardware interrupts

INTR pin, 4-18

TLCINT signal, 4-18 to 4-19

TNT4882_INT signal, 4-18

KEY pins reading DS1204 key, 4-21 using as general purpose I/O pins, 4-21 writing DS1204 key, 4-21 programmed implementation of

Talker or Listener, 4-7 remote/local state considerations,

4-19 to 4-20

T1 delay generation, 4-21 to 4-22

HSTS definition, 4-22

T1 delay, 4-21 to 4-22

T1 delay for various settings

(table), 4-22 timer and timeouts, 4-19 using SCPI, E-4 to E-7 constructing commands using hierarchical command structure, E-5 to E-6 parsing commands, E-7 partial command categories

(illustration), E-4 partial command tree

SENSe command subsystem

(illustration), E-5

SOURce command subsystem

(illustration), E-6

TRIGger command subsystem

(illustration), E-6 simple command tree for SENSe command subsystem

(illustration), E-4

PT1 (Programmable T1 Register), 3-123

PT1_[4-0] bits, Programmable T1

Register (PT1), 3-123

PT1_ENA bit, Programmable T1

Register (PT1), 3-123, B-3 pts (Pass Through Next Secondary) command, 3-37

R

RDN pin, 5-3 rdy message. See GPIB rdy message and

RFD holdoffs.

RDY1 pin, 5-3 to 5-4

TNT4882 Programmer Reference I-22

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National Instruments Corp.

time required to assert, B-4 register bit descriptions. See bit descriptions.

register select pins generic pin configuration

ADDR4-0 and CSN pins, 5-3

BURST_RDN, 5-5

CPUACC and RDY1, 5-3 to 5-4

DACKN, 5-5

DRQ, 5-5

RDN and WRN, 5-3 types of 7210 or 9914 accesses, 5-4

ISA pin configuration

ADDR4-0, 6-3

ADDR9-5, SW9-5, AEN_N, 6-3

IORN, IOWN, 6-3 registers

Accessory Register A

(ACCRA), 3-12

Accessory Register B

(ACCRB), 3-13

Accessory Register E

(ACCRE), 3-14

Accessory Register F (ACCRF), 3-15

Accessory Register I (ACCRI), 3-16

Accessory Register J (ACCRJ), 3-17 to 3-18

Accessory Write Register

(ACCWR), 3-19

Address Mode Register (ADMR),

3-20 to 3-21

Address Register (ADR) one-chip mode, Turbo+7210 mode, 3-22

Turbo+9914 mode, 3-23

Address Register 0 (ADR0), 3-24

Address Register 1 (ADR1), 3-25

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National Instruments Corp.

Address Status Register (ADSR)

Turbo+7210 mode, 3-26 to 3-28

Turbo+9914 mode, 3-29 to 3-31

Auxiliary Command Register

(AUXCR), 3-32 to 3-40

Auxiliary Mode Register (AUXMR),

3-41 to 3-50

Auxiliary Register A (AUXRA),

3-51 to 3-52

Auxiliary Register B (AUXRB), 3-

53 to 3-54

Auxiliary Register E (AUXRE), 3-55

Auxiliary Register F (AUXRF), 3-56

Auxiliary Register G (AUXRG),

3-57 to 3-58

Auxiliary Register I (AUXRI), 3-59 to 3-60

Auxiliary Register J (AUXRJ), 3-61 to 3-62

Board Interrupt Register

(INTR), 3-114

Bus Control Register (BCR)/Bus

Status Register (BSR), 3-63

Carry Cycle Register (CCR), 3-64

Chip Signature Register (CSR), 3-74

Command Pass Through Register

(CPTR), 3-73

Command/Data Out Register

(CDOR), 3-65

Configuration Register (CFG),

3-66 to 3-68 count registers

16-bit mode, 3-72

32-bit mode, 3-72

Index

Count 0 Register (CNT0), 3-71

Count 1 Register (CNT1), 3-71

Count 2 Register (CNT2), 3-71

Count 3 Register (CNT3), 3-71

I-23 TNT4882 Programmer Reference

Index description, 3-72

Data In Register (DIR), 3-76

DIO Control Register (DCR), 3-75

DIO Status Register (DSR), 3-77

End-of-String Register (EOSR), 3-78

First-In First-Out Buffer

(FIFO(A/B)), 3-79 to 3-80

Handshake Select Register

(HSSEL), 3-83 hidden registers one-chip mode/Turbo+7210 mode, 3-4 to 3-5

Turbo+9914 mode, 3-9

High-Speed Enable Register (HIER),

3-81 to 3-82

Interrupt Mask Register 0 (IMR0) one-chip mode, Turbo+7210,

3-84 to 3-87

Turbo+9914 mode, 3-88 to 3-91

Interrupt Mask Register 1 (IMR1) one-chip mode, Turbo+7210 mode, 3-92 to 3-97

Turbo+9914 mode, 3-98 to 3-102

Interrupt Mask Register 2 (IMR2) one-chip mode, Turbo+7210 mode, 3-103 to 3-106

Turbo+9914 mode, 3-107 to 3-110

Interrupt Mask Register 3 (IMR3),

3-111 to 3-113

Interrupt Status Register 0 (ISR0),

3-84 to 3-87

Turbo+9914 mode, 3-88 to 3-91

Interrupt Status Register 1 (ISR1) one-chip mode, Turbo+7210 mode, 3-92 to 3-97

Turbo+9914 mode, 3-98 to 3-102

Interrupt Status Register 2 (ISR2) one-chip mode, Turbo+7210 mode, 3-103 to 3-106

Turbo+9914 mode, 3-107 to 3-110

Interrupt Status Register 3 (ISR3),

3-111 to 3-113

Key Control Register (KEYREG),

3-115 to 3-116

Miscellaneous Register (MISC),

3-117 to 3-118

Parallel Poll Register (PPR)

Turbo+7210 mode, 3-119 to 3-121

Turbo+9914 mode, 3-122

Programmable T1 Register

(PT1), 3-123 register map one-chip mode and Turbo+7210 mode, 3-2 to 3-3

Turbo+9914 mode, 3-7 to 3-8

Serial Poll Mode Register (SPMR),

3-127 to 3-128

Serial Poll Status Register (SPSR),

3-127 to 3-128

SH_CNT Register (SH_CNT), 3-126

Source/Acceptor Status Register

(SASR), 3-124 to 3-125

Status 1 Register (STS1), 3-129 to 3-131

Status 2 Register (STS2), 3-132

T12 Register (T12), 3-133

T13 Register (T13), 3-134

T17 Register (T17), 3-135

Timer Register (TIMER), 3-136 to 3-137

Release RFD Holdoff (rhdf)

TNT4882 Programmer Reference I-24

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National Instruments Corp.

Index command, 3-34

REM bit

Address Status Register

(ADSR), 3-29

Interrupt Status Register 2

(ISR2), 3-104

REMC bit, Interrupt Status Register 2

(ISR2), 3-105 to 3-106

REMC IE bit, Interrupt Mask Register 2

(IMR2), 3-105 to 3-106

Remote Enable (REN) line, GPIB, C-10 remote multiline messages. See multiline messages.

remote/local state considerations, 4-19 to 4-20

REM--Remote signal, 5-8

REN bit, Bus Control Register (BCR)/Bus

Status Register (BSR), 3-63

REN (Remote Enable) line, GPIB, C-10

REOS bit

Accessory Register A

(ACCRA), 3-12

Auxiliary Register A

(AUXRA), 3-52 reqf (Request rsv False) command

Auxiliary Command Register

(AUXCR), 3-38

Auxiliary Mode Register

(AUXMR), 3-48 reqt (Request rsv True) command

Auxiliary Command Register

(AUXCR), 3-38

Auxiliary Mode Register command

(AUXMR), 3-48

Request rsv False (reqf) command

Auxiliary Command Register

(AUXCR), 3-38

Auxiliary Mode Register

(AUXMR), 3-48

Request rsv True (reqt) command

Auxiliary Command Register

(AUXCR), 3-38

Auxiliary Mode Register command

(AUXMR), 3-48

RESET FIFO command, 3-70

RESET pin, ISA pin configuration, 6-5

RESETN pin, 5-7

Return to Local (rtl) commands,

AUXMR, 3-46

RFD holdoffs. See GPIB rdy message and

RFD holdoffs.

rhdf command

Finish Handshake, 3-45

Release RFD Holdoff, 3-34

RLC bit, Interrupt Status Register 0

(ISR0), 3-90

RLC IE bit, Interrupt Mask Register 0

(IMR0), 3-90

RQS bit, C-23

~rsv2 (Clear Request Service bit 2) command, purpose, 3-37 rsv2 (Set Request Service bit 2) command, purpose, 3-37 rsv/RQS bit, Serial Poll Mode Register

(SPMR), 3-128 rtl command

Return to Local, AUXMR, 3-46

Set Return To Local, AUXCR, 3-35

~rtl (Clear Return to Local) command, 3-35

S

S bit, Parallel Poll Register (PPR), 3-120

S[6-1] bits, Serial Poll Mode Register

(SPMR)/Serial Poll Status Register

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National Instruments Corp.

I-25 TNT4882 Programmer Reference

Index

(SPSR), 3-127 to 3-128

S8 bit, Serial Poll Status Register

(SPSR), 3-127

SASR (Source/Acceptor Status Register),

3-124 to 3-125

SCPI. See Standard Commands for

Programmable Instrumentation (SCPI).

secondary addressing, GPIB, C-19

Send EOI (seoi) command,

AUXMR, 3-46

Send EOI With The Next Byte (feoi) command, AUXCR, 3-36

SENSE_8_16N, ISA pin configuration, 6-5 seoi (Send EOI) command,

AUXMR, 3-46

Serial Poll Mode Register (SPMR), 3-127 to 3-128

Serial Poll Status Register (SPSR), 3-127 to 3-128 serial polling events during serial poll

(illustration), C-22 responding to serial polls, 4-14 serial polling devices, C-21 to C-22 servicing SRQs, C-21 status byte model

IEEE 488.1, C-23

IEEE 488.2, C-23 to C-24 writing initial serial poll response, 4-2

Service Request Enable Register (SRE),

C-23, C-24

Service Request (SRQ) line, GPIB, C-11 service requesting

7210-style service requesting, 4-13 asserting the SRQ signal, 4-13

IEEE 488.2 service requesting, 4-13

Set Disable IMR2, IMR1, And IMR0

Interrupts (dai) command, 3-36

Set Force Group Execute Trigger (fget) command, 3-35

Set Holdoff On All Data (hdfa) command, 3-34

Set Holdoff On END Only (hdfe) command, 3-35

Set Listen Only (lon) command, 3-36

Set Parallel Poll Flag (ist) command

Auxiliary Command Register

(AUXCR), 3-39

Auxiliary Mode Register

(AUXMR), 3-44

Set Request Service bit 2 (rsv2) command, 3-37

Set Return To Local (rtl) command,

Auxiliary Command Register

(AUXCR), 3-35

Set Short T1 Delay (stdl) command, 3-37

Set Software Reset (swrst) command, 3-34

Set SYNC command, 3-50

Set Talk Only (ton) command, 3-36

Set Very Short T1 Delay (vstdl) command, 3-37

SH1A SH1B bit, Source/Acceptor Status

Register (SASR), 3-125

SH_CNT Register (SH_CNT) description, 3-126 hidden registers (table), 3-5 signals and lines, GPIB, C-7

SISB bit, Auxiliary Register I

(AUXRI), 3-60

SLOW bit, Miscellaneous Register

(MISC), 3-117 to 3-118

SOFT RESET command, 3-70

Source/Acceptor Status Register (SASR),

TNT4882 Programmer Reference I-26

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National Instruments Corp.

Index

3-124 to 3-125

SPAS bit, Interrupt Status Register 0

(ISR0), 3-90

SPAS IE bit, Interrupt Mask Register 0

(IMR0), 3-90

SPEOI bit

Accessory Register B

(ACCRB), 3-13

Auxiliary Register B

(AUXRB), 3-53

SPMR (Serial Poll Mode Register), 3-127 to 3-128

SPMS bit, Address Status Register

(ADSR), 3-26

SPSR (Serial Poll Status Register), 3-127 to 3-128

SRE (Service Request Enable Register),

C-23, C-24

SRQ bit, Bus Control Register (BCR)/Bus

Status Register (BSR), 3-63

SRQ (Service Request) line, GPIB, C-11

SRQ signal, asserting, 4-13

Standard Commands for Programmable

Instrumentation (SCPI) history, C-1, E-1

IEEE 488.2 common commands required by SCPI, E-2 optional commands, E-3 to E-4 programming with SCPI, E-4 to E-7 constructing commands using hierarchical command structure, E-5 to E-6 parsing commands, E-7 partial command categories

(illustration), E-4 partial command tree

SENSe command subsystem

(illustration), E-5

SOURce command subsystem

(illustration), E-6

TRIGger command subsystem

(illustration), E-6 simple command tree for SENSe command subsystem

(illustration), E-4 required commands, E-3 specification, C-3 to C-4 standards. See IEEE 488.1 standard.

Status 1 Register (STS1), 3-129 to 3-131

Status 2 Register (STS2), 3-132

STBO bit

Interrupt Status Register 0

(ISR0), 3-85

Interrupt Status Register 2

(ISR2), 3-108

STBO IE bit

Interrupt Mask Register 0

(IMR0), 3-85

Interrupt Mask Register 2

(IMR2), 3-108

~stdl (Clear Short T1 Delay) command, 3-37 stdl (Set Short T1 Delay) command, 3-37

STOP bit

Interrupt Status Register 3

(ISR3), 3-112

Status 1 Register (STS1), 3-129 to 3-130

STOP command, 3-70

STOP IE bit, Interrupt Mask Register 3

(IMR3), 3-112

STS1 (Status 1 Register), 3-129 to 3-131

SW9-5 pin, 6-3

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National Instruments Corp.

I-27 TNT4882 Programmer Reference

Index sw7210 (Switch To 7210 Mode) command, definition, 3-38

SWAP bit

Key Control Register

(KEYREG), 3-115 offsets and, 3-9 setting, 3-9 to 3-10

SWAPN pin, 5-6, 5-7

Switch to 9914A Mode command,

AUXMR, 3-47

~swrst (Clear Software Reset) command, 3-34 swrst (Set Software Reset) command, 3-34

SYNC bit, Interrupt Status Register 0

(ISR0), 3-87

SYNC IE bit, Interrupt Mask Register 0

(IMR0), 3-87

System Controller, C-14. See also GPIB

Controller.

T

T1 delay generation, 4-21 to 4-22 byte sourcing speed, B-2

HS488 requirements if T1 delay is

350 ns, D-2

HSTS definition, 4-22

T1 delay, 4-21 to 4-22

T1 delay for various settings

(table), 4-22

T12 Register (T12), 3-133

T12_[4-0] bit, T12 Register (T12), 3-133

T13 Register (T13), 3-134

T13_[4-0] bit, T13 Register (T13), 3-134

T17_[4-0] bit, T17 Register (T17), 3-135

TA bit, Address Status Register (ADSR)

Turbo+7210 mode, 3-27 to 3-28

Turbo+9914 mode, 3-30 to 3-31

TADCS--Talker Addressed signal, 5-7

Talkers. See also GPIB Controller;

Listeners.

HS488 data transfers

Talker and Listener are HS488 capable, D-4 to D-5

Talker is HS488 capable but

Listener is not, D-5 to D-6

Talker is not HS488 capable, D-

6 programmed implementation, 4-7 properties, C-15 system setup example

(illustration), C-16 technical support, H-1 termination methods, GPIB, C-19 to C-21 combination of methods, C-21 count method, C-20 to C-21

EOI method, C-20

EOS method, C-20 termination of GPIB data transfer, 4-12 three-wire handshake process description, C-13 illustration, C-12

TIM/BYTN bit, Configuration Register

(CFG), 3-67 to 3-68 timer and low clock frequencies, B-3 byte timeouts, 4-19 description, 4-19 generating interrupts, 4-19 global timeouts, 4-19 timeout values supported by Accessory

Register J (table), 3-17 to 3-18 supported by Auxiliary Register

TNT4882 Programmer Reference I-28

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National Instruments Corp.

Index

J (table), 3-61 to 3-62

Timer Register (TIMER), 3-136 to 3-137

TLCHLTE bit, Configuration Register

(CFG), 3-66

TLCINT bit, Interrupt Status Register 3

(ISR3), 3-113

TLCINT IE bit, Interrupt Mask Register 3

(IMR3), 3-113

TLCINT signal hardware interrupts, 4-18 to 4-19 termination of GPIB data transfer, 4-12

TM[3-0] bits

Accessory Register J (ACCRJ), 3-17 to 3-18

Auxiliary Register J (AUXRJ), 3-61 to 3-62

TMOE bit, Configuration Register (CFG),

3-67

TNT4882 bus interface capabilities, 1-4 capabilities (table), 1-1 to 1-2

CPU interface features, 1-4 features, 1-3 to 1-4 initializing. See chip initialization.

overview, 1-1

TNT4882 architectures architecture after hardware reset, 2-4 changing modes, 2-3 to 2-4 one-chip mode, 2-2 selecting a mode, 2-2 to 2-3

Turbo+7210 mode, 2-1

Turbo+9914 mode, 2-2

TNT4882_INT signal, 4-18

TO bit

Interrupt Status Register 0

(ISR0), 3-87

Interrupt Status Register 2

(ISR2), 3-110

TO IE bit

Interrupt Mask Register 0

(IMR0), 3-87

Interrupt Mask Register 2

(IMR2), 3-110 ton (talk only) addressing mode, 3-21

~ton (Clear Talk Only) command, 3-36 ton (Set Talk Only) command, 3-36

TPAS bit, Address Status Register

(ADSR)

Turbo+7210 mode, 3-27

Turbo+9914 mode, 3-30 transfer holdoffs, HS488

Listener wants to resume three-wire handshake, D-8

Listener's buffer nearly full, D-7

Talker sends EOI or EOS, D-9

TRI bit, Auxiliary Register B

(AUXRB), 3-53

Trigger (trig) command, AUXMR, 3-46 triggering devices, C-28

TRIG--Trigger signal, 5-8

Turbo+7210 mode block diagram, 2-1 changing to another mode illustration, 2-3 one-chip mode, 2-4

Turbo+9914 mode, 2-4 description, 2-1 placing TNT4882 in Turbo+7210 mode, 4-1 to 4-2 when to use, 2-3

Turbo+9914 mode block diagram, 2-1 changing to another mode illustration, 2-3

Turbo+7210 mode, 2-4

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National Instruments Corp.

I-29 TNT4882 Programmer Reference

Index description, 2-2 when to use, 2-3

U

U bit, Parallel Poll Register (PPR), 3-119 ulpa bit, Address Status Register

(ADSR), 3-31

UNC bit, Interrupt Status Register 1

(ISR1), 3-99 to 3-100

UNC IE bit, Interrupt Mask Register 1

(IMR1), 3-99 to 3-100

Unlisten (lul) command, AUXMR, 3-47

Untalk (lut) command, AUXMR, 3-46

USTD bit

Accessory Register I (ACCRI), 3-16

Auxiliary Register I (AUXRI), 3-59

V

V[3-0] bit, Chip Signature Register

(CSR), 3-74

Valid Secondary Command Or Address

(valid), AUXMR, 3-47

~vstdl (Clear Very Short T1 Delay) command, 3-37 vstdl (Set Very Short T1 Delay) command, 3-37

W

WRAP bit, Miscellaneous Register

(MISC), 3-118

WRN pin, 5-3

WR* signal, B-1

X

XEOS bit

Accessory Register A

(ACCRA), 3-12

Auxiliary Register A

(AUXRA), 3-51

TNT4882 Programmer Reference I-30

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National Instruments Corp.