General
Hardware compatibility relating to the bus manager
General
Availability
Capacity
The binary flow of the bus is 1 Mbits/s and it can extend to a length of up to 15 Km, with four optical or electric repeaters (TSX FP ACC 6).
The FIPIO bus links up to Hirshmann optical transmitters, which allows medium redundancy architectures to be created.
This type of communication is available via built-in links on Premium PLCs from version V3.0 onwards.
The PLCs with built-in FIPIO links are the following: z z
TSX type processors: z TSX P57 153, z z
TSX P57 253, TSX P57 2823,
TSX P57 353/353A z TSX P57 453/453A, TSX P57 4823/4823A.
PCX type processors: z PCX57353.
The bus manager can also be a PLC of the following type: z z
TSX 47-107 version 5.3 minimum,
S1000.
Processors with built-in FIPIO links are used to manage 128 connection points
(TSX P57 153 = 64) on the bus (addresses 0 to 127).
The bus manager is connected to address 0, and address 63 is reserved for the programming and diagnostics terminal.
These processors have a RAM memory for saving the configurations of devices connected to the bus. This memory has a maximum capacity of 94,320 bytes and
213,104 for (TSX P57 453/453A/4823/4823A) processors.
242
35013154.02 07/2208
