3.6. Si. Silicon Laboratories SI5369, SI5322, SI5327, SI5326, SI5366, SI5319, SI5316, SI5325, SI5367, SI5368

S i 5 3 x x - R M

3.6. Si5325

The Si5325 is a low jitter, precision clock multiplier for applications requiring clock multiplication without jitter attenuation. The Si5325 accepts dual clock inputs ranging from 10 to 710 MHz and generates two independent, synchronous clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The Si5325 input clock frequency and clock multiplication ratios are programmable through an I

2

C or SPI interface. The DSPLL loop bandwidth is digitally programmable from 150 kHz to 1.3 MHz. Operating from a single 1.8, 2.5, or 3.3 V supply, the

Si5325 is ideal for providing clock multiplication in high performance timing applications. See "7. Microprocessor

Controlled Parts (Si5319, Si5324, Si5325, Si5326, Si5327, Si5367, Si5368, Si5369, Si5374, Si5375)" on page 76

for a complete description.

CKIN_1 +

CKIN_1 –

CKIN_2 +

CKIN_2 –

2

2

INT_C1B

C2B

÷ N31

÷ N32

Signal

Detect

0

1

0

1 f

3

DSPLL

®

÷ N2

BYPASS

f

OSC

÷ NC1

1

0

÷ N1_HS

÷ NC2

1

0

2

/

CKOUT_1 +

CKOUT_1 –

2

/

CKOUT_2 +

CKOUT_2 –

CMODE

SDA_SDO

SCL

SDI

A[2]/SS

A[1:0]

RST

Control

VDD

GND

Figure 6. Si5325 Low Jitter Clock Multiplier Block Diagram

22 Rev. 0.5