6. Pin Control Parts (Si5316, Si5322, Si5323, Si5365, Si5366). Silicon Laboratories SI5369, SI5322, SI5327, SI5326, SI5366, SI5319, SI5316, SI5325, SI5367, SI5368

S i 5 3 x x - R M

6. Pin Control Parts (Si5316, Si5322, Si5323, Si5365, Si5366)

These parts provide high-performance clock multiplication with simple pin control. Many of the control inputs are three levels: High, Low, and Medium. High and Low are standard voltage levels determined by the supply voltage:

V

DD

and Ground. If the input pin is left floating, it is driven to nominally half of V

DD

. Effectively, this creates three logic levels for these controls.

These parts span a range of applications and I/O capacity as shown in Table 12.

Table 12. Si5316, Si5322, Si5323, Si5365 and Si5366 Key Features

SONET Frequencies

DATACOM Frequencies

DATACOM/SONET internetworking

Fixed Ratio between input clocks

Flexible Frequency Plan

Number of Inputs

Number of Outputs

Jitter Attenuation

Si5316







2

1



Si5322









2

2

Si5323









2

2



Si5365









4

5



4

5



Si5366







6.1. Clock Multiplication (Si5316, Si5322, Si5323, Si5365, Si5366)

By setting the tri-level FRQSEL[3:0] pins these devices provide a wide range of standard SONET and data communications frequency scaling, including simple integer frequency multiplication to fractional settings required for coding and decoding.

6.1.1. Clock Multiplication (Si5316)

The device accepts dual input clocks in the 19, 39, 78, 155, 311, or 622 MHz frequency range and generates a dejittered output clock at the same frequency. The frequency range is set by the FRQSEL [1:0] pins, as shown in

Table 13.

Table 13. Frequency Settings

FRQSEL[1:0]

LL

LM

LH

ML

MM

MH

Output Frequency (MHz)

19.38–22.28

38.75–44.56

77.50–89.13

155.00–178.25

310.00–356.50

620.00–710.00

50 Rev. 0.5

Si53xx-RM

The Si5316 can accept a CKIN1 input at a different frequency than the CKIN2 input. The frequency of one input clock can be 1x, 4x, or 32x the frequency of the other input clock. The output frequency is always equal to the lower of the two clock inputs and is set via the FRQSEL [1:0] pins. The frequency applied at each clock input is divided

down by a pre-divider as shown in the Figure 1 on page 17. These pre-dividers must be set such that the two

resulting clock frequencies, f3_1 and f3_2 must be equal and are set by the FRQSEL [1:0] pins. Input divider

settings are controlled by the CK1DIV and CK2DIV pins, as shown in Table 14.

Table 14. Input Divider Settings

CKnDIV

L

M

H

N3n Input Divider

1

4

32

Table 15. Si5316 Bandwidth Values

FRQSEL[1:0] Nominal Frequency Values (MHz)

LL LM LH ML MM MH

BW[1:0]

19.44 MHz 38.88 MHz 77.76 MHz 155.52 MHz 311.04 MHz 622.08 MHz

HM

HL

MH

MM

ML

100 Hz

210 Hz

410 Hz

1.7 kHz

7.0 kHz

100 Hz

210 Hz

410 Hz

1.7 kHz

7.0 kHz

100 Hz

200 Hz

400 Hz

1.6 kHz

6.8 kHz

100 Hz

200 Hz

400 Hz

1.6 kHz

6.7 kHz

100 Hz

200 Hz

400 Hz

1.6 kHz

6.7 kHz

100 Hz

200 Hz

400 Hz

1.6 kHz

6.7 kHz

CKIN1

CKIN2

One-to-one frequency ratio

 1,  4,  32 f

3

DSPLL

F out

 1,  4,  32

Figure 24. Si5316 Divisor Ratios

f

3

= F out

Rev. 0.5

51