7.3. Input Clock Configurations (Si5367 and Si5368). Silicon Laboratories SI5369, SI5322, SI5327, SI5326, SI5366, SI5319, SI5316, SI5325, SI5367, SI5368

Si53xx-RM

7.3. Input Clock Configurations (Si5367 and Si5368)

The device supports two input clock configurations based on CK_CONFIG_REG. See "6.5. Frame Synchronization

(Si5366)" on page 70 for additional details.

7.4. Input Clock Control

This section describes the clock selection capabilities (manual input selection, automatic input selection, hitless switching, and revertive switching). The Si5319, Si5327, and Si5375 support only pin-controlled manual clock

selection. Figure 27 and Figure 28 provide top level overviews of the clock selection logic, though they do not

cover wideband or frame sync applications. Register values are indicated by underscored italics. Note that, when switching between two clocks, LOL may temporarily go high if the clocks differ in frequency by more than 100 ppm.

CKIN1

CKIN2

Selected

Clock

CK_PRIORn

4

Clock priority logic

CS_CA pin

CKSEL_REG

AUTOSEL_REG

2

1 decode

Auto

Manual

0

0

1

CK_ACTV_PIN

CKSEL_PIN

Figure 27. Si5324, Si5325, Si5326, Si5327, and Si5374 Input Clock Selection

Rev. 0.5

81