6.2. PLL Self-Calibration. Silicon Laboratories SI5369, SI5322, SI5327, SI5326, SI5366, SI5319, SI5316, SI5325, SI5367, SI5368


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6.2. PLL Self-Calibration. Silicon Laboratories SI5369, SI5322, SI5327, SI5326, SI5366, SI5319, SI5316, SI5325, SI5367, SI5368 | Manualzz

Si53xx-RM

6.2. PLL Self-Calibration

An internal self-calibration (ICAL) is performed before operation to optimize loop parameters and jitter performance. While the self-calibration is being performed, the DSPLL is being internally controlled by the selfcalibration state machine, and the LOL alarm will be active for narrowband parts. The self-calibration time t

LOCKHW

is given in Table 8, “AC Characteristics—All Devices”.

Any of the following events will trigger a self-calibration:

Power-on-reset (POR)

Release of the external reset pin RST (transition of RST from 0 to 1)

Change in FRQSEL, FRQTBL, BWSEL, or RATE pins

Internal DSPLL registers out-of-range, indicating the need to relock the DSPLL.

In any of the above cases, an internal self-calibration will be initiated if a valid input clock exists (no input alarm) and is selected as the active clock at that time. For the Si5316, Si5323 and Si5366, the external crystal or reference clock must also be present for the self-calibration to begin. If valid clocks are not present, the selfcalibration state machine will wait until they appear, at which time the calibration will start. All outputs are on during the calibration process.

After a successful self-calibration has been performed with a valid input clock, no subsequent self-calibrations are performed unless one of the above conditions are met. If the input clock is lost following self-calibration, the device enters digital hold mode. When the input clock returns, the device relocks to the input clock without performing a self-calibration. (Narrow band devices only).

6.2.1. Input Clock Stability during Internal Self-Calibration (Si5316, Si5322, Si5323, Si5365, Si5366)

An exit from reset must occur when the selected CKINn clock is stable in frequency with a frequency value that is within the operating range that is reported by DSPLLsim. The other CKINs must also either be stable in frequency or squelched during a reset.

6.2.2. Self-Calibration caused by Changes in Input Frequency (Si5316, Si5322, Si5323, Si5365, Si5366)

If the selected CKINn varies by 500 ppm or more in frequency since the last calibration, the device may initiate a self-calibration.

6.2.3. Recommended Reset Guidelines (Si5316, Si5322, Si5323, Si5365, Si5366)

Follow the recommended RESET guidelines in Table 20 and Table 21 when reset should be applied to a device.

Rev. 0.5

65

S i 5 3 x x - R M

71

80

95

61

66

67

68

69

70

51

54

55

60

Pin #

4

32

42

19

20

22

23

2

11

14

15

24

25

26

27

30

33

Pin # Si5316 Pin

Name

N/A

RATE 0

DBL_BY

RATE1

N/A

N/A

BWSEL0

BWSEL1

FRQSEL0

FRQSEL1

N/A

N/A

SFOUT1

SFOUT0

Table 20. Si5316, Si5322, and Si5323 Pins and Reset

Must Reset after Changing Si5322 Pin

Name

FRQTBL

N/A

DBL2_BY

N/A

N/A

N/A

BWSEL0

BWSEL1

FRQSEL0

FRQSEL1

FRQSEL2

FRQSEL3

N/A

N/A

Si5323 Pin

Name

FRQTBL

RATE 0

DBL2_BY

RATE1

DEC

INC

BWSEL0

BWSEL1

FRQSEL0

FRQSEL1

FRQSEL2

FRQSEL3

SFOUT1

SFOUT0

No

No

Yes

Yes

Yes

Yes

No

Yes

Yes

Yes

Yes

Yes

No, but skew not guaranteed without Reset

No, but skew not guaranteed without Reset

Table 21. Si5365 and Si5366 Pins and Reset

Si5365 Pin Name

FRQTBL

N/A

N/A

N/A

N/A

N/A

BWSEL0

BWSEL1

DIV34_0

DIV34_1

FRQSEL0

FRQSEL1

FRQSEL2

FRQSEL3

N/A

N/A

Si5366 Pin Name

FRQTBL

RATE 0

RATE 1

CK_CONF

DEC

INC

BSWEL0

BWSEL1

DIV34_0

DIV34_1

FRQSEL0

FRQSEL1

FRQSEL2

FRQSEL3

SFOUT1

SFOUT0

Must Reset after Changing

Yes

Yes

Yes

Yes

No

No

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

No, but skew not guaranteed without Reset

No, but skew not guaranteed without Reset

66 Rev. 0.5

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