User’s Manual PCI-CAMAC
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2 PCIADA INTERFACE CARD
2.1
32 Kbytes Address range
Attention:
The CAMAC version of PCIADA to be used with the CAMAC controller CC32 is configured to use a 32 Kbytes address area instead of the original 8K for use with VMEMM.
Thus instead of address bits A0 and A1 the higher address bits A13 u. A14 are transmitted. The
CAMAC version of PCIADA is labeled with a “
C”
on the EEPROM.
If necessary it is possible to re-program the EEPROM. This can be done by the user via the computer where the PCIADA is plugged in.
All instructions are given on the enclosed CD-ROM at WORKAROUND.TXT
2.2
General description and function
Attention:
It is assumed that the PC is equipped with a self-configuring PCI-BIOS (“Plugand-Play Bios “) which automatically recognizes the card.
To guarantee a maximum PCI compatibility and performance the PCIADA is based on the
PCI-bus target- interface-Chip
PLX9050
produced by
PLX-Technology
, which manages the PCI communication.
At booting time necessary settings are configured by PCI auto setup. No jumpers have to be set on the interface card. All PCIADA information such as memory and IRQ requirements are stored in an EEPROM. Some IDs can be read out from PCR:
During PCI setup PCIADA calls for three different memory areas:
1.
54 byte Local Configuration Register (LCR) of the I/O area. Different control status register and base addresses are available in the LCR.
Note
: Some computer architectures do not provide register mappings in the I/O area. Please refer to LCR in memory area.
2.
32 Kbytes of the memory area for direct access to local CC32 address space and transparent CAMAC data way access
2.3
Major PC-Register (PCR)
The following ID’s are used to identify the connected hardware. These values are determined by the PCI-Bios and software drivers:
ID
PCIADA Defined value for CC32
Vendor ID
Device ID
0x10B5
0x2258
Subsystem Vendor ID 0x9050
Subsystem Device ID 0x2258
PCIADA Defined value for VMEMM (ref. only)
0x10B5
0x9050
0x9050
0x1167
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User’s Manual PCI-CAMAC
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2.4
Major LC-Registers (LCR)
According to the PCI specification the Base addresses for the LC-Register and CC32 memory areas are automatically allocated during booting of the computer. They can be obtained via BIOS from the PLX chip. Please refer to the software section and the PCI9050 data sheet on the CD-ROM. ( see CD-ROM ..PCIADA\Chipdocu\9050-1ds.pdf)
There are no additional registers to be programmed by the user.
2.4.1
Interrupt Control/Status Register
INTERRUPT-1
Interrupt requests, initiated by CC32 (LAM-FF), will set INTERRUPT-1 status bit to 1. For this purpose the interrupt request has to be enabled.
INTERRUPT-2
The INTERRUPT-2 status bit will be activated by local PCIADA events. The following sources can cause
INTERRUPT-2:
1. Access without connection between CC32 and PCIADA (no cable connection)
2. Access to CAMAC crate which is not switched on (CC32 not working)
3. CC32 access has not yet been enabled. The user bit I/O 2 has to be set to enable the access to the
CAMAC crate controller.
INTCSR; LCR-Baseadr + 0x4c
( by word-access) byte RD WR after Init
2
3
0
1
Local Interrupt 1 enable: 1 = enable / 0 = disable (source = CC32)
Local Interrupt 1 polarity : 1 = active high / 0 = active low yes yes 1 yes yes 0
Local Interrupt 1 status: 1 = active. 0 = not active yes no 0
Local Interrupt 2 enable: 1 = enable / 0 = disable (source = PCIADA) yes yes 1
4
5
6
Local Interrupt 2 polarity: 1 = active high / 0 = active low
Local Interrupt 2 status: 1 = active. 0 = not active
PCI Interrupt enable: 1 = enable / 0 = disable (source = global)
7 Software Interrupt: 1 = generate Interrupt
15..8
not used yes yes 0 yes no yes yes yes yes yes no
0
0
0
00000000 b
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2.4.2
User I/O Register / Reset Interrupt
USERI/O2:
The
User I/O Register
(
CNTRL
) is divided into two parts which are summarized in the following. The register USER I/O2:
1.
locks CC32 during boot time to prevent any access of the Operating System.
2.
resets interrupt 2 if it is deleted.
USER I/O3:
Register USER I/O3 monitors the status of the CAMAC crate and the cable connection, i.e. it shows the switched on CAMAC crate and the proper cable connection.
CNTRL; LCR-Baseadr + 0x50
( by word-access) byte
5..0
6
7
8 do not modify !
USER I/O2 Type, must always be 0
USER I/O2 Direction, must always be 1 = output
USER I/O2 output, 0 = disable access to CC32, 1 = enable access
9
10
11
USER I/O3 Type, must always be 0
USER I/O3 Direction, must always be 0 = input
USER I/O3 Input, 0 = CC32 failed , 1 = CC32 OK
15..12
do not modify
Write 0x4184 for enable access to CC32
Write 0x4084 for disable access to CC32
RD WR after Init yes yes 000100 b yes yes 0 yes yes 1 yes yes 0 yes yes 0 yes yes 0 yes no 0 yes yes 0100 b
2.5
Access-Timeout
An
Access Timeout
is implemented in the PCIADA interface, which is currently set to about 35 µs.
Reaching this time-out the current transaction will be terminated and an INTERRUPT-2 initiated. If the
CC32 is switched off or disconnected the same INTERRUPT-2 is activated.
2.6
Interrupts
The PCI-CAMAC system can generate interrupts on the PC caused by two different interrupt sources.
PCIADA can activate a Timeout Interrupt which should be routed via software to the interrupt vector number 1. All CC32 generated interrupts should be routed via software to the interrupt vector number 2.
Interrupt Source
PCIADA Interrupt (Timeout)
CC32 Interrupt (LAM-FF)
Vector No.
1
2
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2.7
Power Consumption
Voltage
+5V
PCI-CAMAC
Max. current
ca. 0,5 A
Power
Ca. 2,5W
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2.8
PCIADA Layout
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