CC32 CONTROLLER. W-Ie-Ne-R PCIADA, CC32

Below you will find brief information for CAMAC crate controller CC32, PCI interface card PCIADA. The CC32 CAMAC crate controller supports the FAST CAMAC (see DOE/SC-0002 or http://www.yale.edu/fastCAMAC) BASIC level 1 using multiple S1 strobes to increase the data transfer speed. For optimized timing it is possible to adjust the CAMAC cycle time. In addition the width of the S1 and S2 strobe signals can be set optionally to the shorter value of 100ns. The PCIADA interface card supports 16 and 32 – bit PCI bus slave access. It provides programmable interrupt generation on PC. PCIADA is also compatible to the PCI-VME system.

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User’s Manual PCI-CAMAC

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3 CC32 CONTROLLER

3.1 Special Features

3.1.1 FASTCAMAC basic Level 1

The CC32 CAMAC crate controller supports the FAST CAMAC (see DOE/SC-0002 or http://www.yale.edu/fastCAMAC ) BASIC level 1 using multiple S1 strobes to increase the data transfer speed (theoretical max. 7.5Mbytes/s). As defined within the FAST CAMAC specification the function code F = 5 is used to read data from a module supporting this mode. Getting the first data set in this mode the controller continues automatically to read the following one to have it available without any delay for the next data request from the computer. Thus it is possible to read data with the maximum transfer rate between CC32 and PCIADA which saves about 400ns per read-cycle. This FAST CAMAC level 1 read via F = 5 is stopped if the Q-response is missing.

The FAST CAMAC level 1 cycle can be interrupted by another F –command. In this case the new command is executed correctly however, the data which have been already buffered in the CC32 are lost.

3.1.2 CAMAC-Cycle-Tuning

For optimized timing it is possible to adjust the CAMAC cycle time (time between begin of BUSY = active to S1) for each individual CAMAC station C-Station via software. Possible values are 200ns,

300ns and 400ns (default). In addition the width of the S1 and S2 strobe signals can be set optionally to

100ns.

3.1.3 DATAWAY-DISPLAY

To extend the functionality of the CC32 crate controller it is equipped with an integrated CAMAC data way display. This allows to monitor the activity in the CAMAC crate and is a helpful tool to locate faults in the system. The internal data registers (data and control bits) used for this purpose can be accessed also in CC32 controllers without display. The CC32-LED card which is internally plugged onto the CC32 normal station shows the following signals with color LED’s:

•

Station number N1, N2, N4, N8 and N16

•

Sub-address A1, A2, A4 and A8

•

Function F1, F2, F4, F8 and F16

•

Data 1 – 24 (shared for R1...R24 and W1...W24

•

Q, X, (Q and X response)

•

C, Z (Clear) and Z (Initialize)

•

I (Inhibit)

•

Local and CAMAC cycle

•

LAM (Look-at-me request from station)

•

6V power line

Please note that the N LED is also responding on local CC32 commands.

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3.2 CC32 Normal-Station

To allow an easy test of the controller and PCIADA to CC32 connection the following test functions are implemented in the CC32 Normal-Station. The station number

corresponds to the left one of the two CAMAC slots occupied by the CAMAC controller. As given in 1.4.2 the CC32 has to be plugged in into the most right slots of the CAMAC crate (normally slot 24 and 25).

(

= CC32 Control-Station

– 1

)

Write

Nn * A0 * F16

data <> 5

Nn * A0 * F16

data = 5

Nn * A1 * F16

data = 0..15

Read

Nn * A0 * F0

data = 0 generate Q and X generate Q ,X and LAM ( LAM 200ns active) load test counter, generate Q and X generate Q and X

Read in Fast CAMAC Level 1 mode

Nn * A1 * F5

data = 0 decrement test counter, generate X and Q only if test counter content > 0

3.3 NAF Commands and Addressing

A 32 Kbytes memory window is used to access the CC32 and to perform CAMAC operations. This 32

Kbytes area is mapped into the PCI address space. The position (e.g. Basic address) within the PCI address space is dynamically allocated.

For CAMAC commands the

N, A

and

numbers are coded into the Address bits

A14 … A2.

Thus these bits have to be understood as NAF bits. Also local calls are performed as NAF commands. Only word and long word accesses are possible to the CC32 (see 3.4.)

3.3.1 NAF bit coding

32K address CC32 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

CAMAC-Function-bit N16 N8 N4 N2 N1 A4 A3 A2 A0 F8 F4 F2 F1 -

3.3.2 NAF calculation

The F16 bit is automatically defined by the kind of operation, i.e. it is not considered in the NAF code calculation!

WRITE to CC32

defines automatically

F16 = 1

READ from CC32

defines automatically

F16 = 0

The different address offsets for N, A and F into the 32 Kbytes memory window can be calculated as shown below:

Pascal:

NAF := N shl 10 + A shl 6 + (F AND $f) shl 2;

C / C++:

#define MAKE_CC32_OFFSET(N,A,F) ((N<<10) + (A<<6) + ((F & 0xf)<<2))

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To reduce the time required by the software for coding the NAF address it can be helpful to define constants for these values in the user program. This can increase the data rates. Further it is recommended to set the F16-bit to 0 before calculating the address as shown above to avoid an overlap with the A1 bit.

3.4 CC32 Address map

The 32 Kbytes memory window can be accessed only by word and long word calls. byte calls are not processed and answered by the CC32. They are terminated by a TIME-OUT signal from the PCIADA card. All word and long word calls are accepted by the CC32. Please note in case of a long word (Lword) access to an address specified for word only :

Long word-Read from CC32 word address: D31..D16 equals to D15..D00.

Long word-Write to CC32 word address: only D15..D00 will be transferred. D31..D16 are ignored.

All CC32-commands described following are given within the CAMAC NAF-notation. This includes internal CC32 commands. The gray marked cells in the next table indicate operations to the CAMAC stations via the CAMAC data way. All the other described commands are special functions of the CC32 controller.

NAF

N31*A0*Fx

N30*A2*Fx

N30*A1*Fx

N30*A0*Fx

N29*A0*Fx

N28*A4*Fx

N28*A3*Fx

N28*A2*Fx

N28*A1*Fx

N28*A0*Fx

November 00

Access WR-Function / F16-bit=1

Word

CC32 RESET

Word

CYCLE-TUNE-RegC

D15..D00 >> N24..N17

Word

CYCLE-TUNE-RegB

D15..D00 >> N16-N9

Word

Lword

CYCLE-TUNE-RegA

D15..D00 >> N8..N1

Lword

LAM-MASK

D23..D00 >> LMASK23-LMASK0

D31..D24 = xx

Word

LAM_FF reset

D15..D00 = xx

RD-Function / F16-bit=0

CYCLE-TUNE-RegC

D15..D00 << N24..N17

CYCLE-TUNE-RegB

D15..D00 << N16..N9

CYCLE-TUNE-RegA

D15..D00 << N8..N1

LED-Status

D23..D00 << LED24..LED1

D27..D24 << C,Z,CT1,CT0

D31..D28 << Q,X,INH,LAM-FF

LAM-BUS

D23..D00 << LAM24..LAM1

D31..D24 is equal LAM-MASK

LAM-NOT = LAMn & !LMASKn

D23..D00 << NOT24..NOT1

D31..D24 is equal LAM-MASK

LAM-AND = LAMn & LMASKn

D23..D00 << AND24..AND1

D31..D24 is equal LAM-MASK

LAM-MASK

D23..D00 << LMASK24..LMASK1

D27..D24 = 0

D28 = LAM-BUS-OR

D29 = LAM-NOT-OR

D30 = LAM-AND-OR

D31 = LAM-FF

LAM-FF Status

D00 = 1 LAM-FF set

D00 = 0 LAM-FF not set

D15..D01 = 0

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N27*A0*Fx

N27*A1*Fx

N26*A0*Fx

Word

INHIBIT on

INHIBIT off

D31..D00 = xx

Lword

Broadcast-MASK

D23..D00 >> BMASK24..BMASK1

INHIBIT Status

D00 = INHIBIT on = 1

D01 = INHIBIT Dataway on = 0

D15..D02 = 0

Broadcast-MASK

D23..D00 << BMASK24..BMASK1

D24..D31 << 0

N25*Ax*Fx

Lword

Broadcast-WR=allN & BMASKn

D23..D00 >>W1..W24

N1-24*Ax*Fx

Lword

CAMAC-DATAWAY WRITE *1

D23..D00 >> W24..W1 *3

N1-24*Ax*Fx

N0*A0*Fx

N0*A1*Fx

N0*A2*Fx

N0*A3*Fx

Word

CAMAC-DATAWAY WRITE *1

D00..D15 > W1..W16 *3

Word

CAMAC C *2

CAMAC Z *2

CAMAC C + INHIBIT off *2

CAMAC Z + INHIBIT on *2

D15..D00 = xx

Standard CAMAC -Access

Standard CAMAC -Access without S1 no W-Data on CAMAC -Dataway when F8-bit is active if test Q- or X-Status then use Lword-Access

CAMAC-DATAWAY READ *1

D23..D00 << R23..R00

D29..D24 = 0

D31,D30 Q,X

CAMAC-DATAWAY READ *1

D00..D15 < R1..R16 *4

CC32-STATUS

D03..D00 << Q,X,INH,LAM-FF

D07..D04 << Modul-Number

D11..D08 << FPGA-Revision

D15..D12 << Modul-Type 1000b

3.5

CC32-Status

N0*A0*Fx

(Read Word)

This register contains the CC32 configuration and status, including the CAMAC status lines Q, X, I and LAM. The module type identification (bit 12 .. 15) and module number (bit 4 … 7) can be used to identify the CC32.

CC32-Status (word read access only)

Bit RD WR after Init

15..12

Module type identification, 1000b for CC32 (0001b VMEMM) yes no 1000b

11..8

FPGA-Revision yes no xxxx

7..4

Module number, Coding of Jumpers J304..J301

yes no Jumpers

Q – Response

X – Response

State of Inhibit-Flip-Flop

State of LAM-Flip-Flop yes no yes no yes no yes no x x

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3.6

CC32-C,Z,Inhibit,LAM-FF

N0*A0*Fx

N0*A1*Fx

N0*A2*Fx

N0*A3*Fx

N27*A0*Fx

N27*A1*Fx

N28*A0*Fx

(CAMAC Clear)

(CAMAC Initialize)

C + I

nhibit off

Z + I

nhibit on

nhibit on nhibit off

LAM

3.7

Broadcast-Mask-Register

-FF reset

(Write Word)

N26*A0*Fx

(Read/Write

Allows to enable / disable CAMAC stations for broadcast write commands. All stations (N1 … N24) with Broadcast mask bit = 1 are enabled.

Data

Broadcast-Mask for:

D23 D22 D21..D3

N24 N23 N22..N4

D2 D1 D0

N3 N2 N1

3.8

Broadcast CAMAC-Write

N25*Ax*Fx

(CAMAC-Write-Cycle Word or Lword)

Broadcast write command, has to be performed with a correct A(x), F(x) and W-Data CAMAC command. Stations N1..N24 are active for this write operation if the corresponding Broadcast-Maskbit is 1.

3.9

LAM-Mask-Register

N28*A1*Fx

(Read/Write

All stations (with station number N) with enabled Broadcast Mask-bit (=1) can generate a LAM-FF in the CC32 controller which can yield in an interrupt on the PCIADA card.

Data D23 D22 D21..D3

Enable LAM from Station N24 N23 N22..N4

D2 D1 D0

N3 N2 N1

The negative edge of the LAM-signal arriving from any station is only transmitted to the LAM-Flip-

Flop if the corresponding LAM-Mask-bit is active (=1). The LAM-FF stays on the active level until a reset command N28*A0*F16 occurs.

The following status bits can be used to get a more detailed information about the LAM conditions:

D28 = 1 (LAM-BUS-OR) if at least one LAM is pending

D29 = 1 (LAM-NOT-OR) if at least one LAM is pending from disabled stations (LAM-Maskbit =0)

D30 = 1 (LAM-AND-OR) if at least one LAM is pending from enabled stations (LAM-Maskbit =1)

D31 = 1 (LAM-Flip-Flop) if LAM request

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3.10 LAM-AND-Status

N28*A2*Fx

(Read

Dxx = 1 if LAM = active and LAM-Maskbit = 1.

Data

LAM status & LMASK

D23 D22 D21..D3

N24 N23 N22..N4

( bits D28..D31 as described in

3.8)

3.11 LAM-NOT-Status

N28*A3*Fx

(Read

Dxx = 1 if LAM = active and LAM-Maskbit = 0.

Data D23 D22 D21..D3

LAM Status & not LMASK N24 N23 N22..N4

( bits D28..D31 as described in

3.8)

3.12

LAM-BUS-

Status

N28*A4*Fx

(Read

Dxx = 1 if LAM = active.

LAM-BUS D23 D22 D21..D3

LAM Status CAMAC-Bus N24 N23 N22..N4

( bits D28..D31 as described in

3.8)

3.13

LED-Status

N29*A0*Fx

(Read

This function can be used to read back the information of the optional dataway display. If no dataway display is installed the function can be used to determine the CAMAC data and status signals of the last

CAMAC dataway operation. The LED24..LED1 bits correspond to the write (W) or read (R) data of the last CAMAC cycle.

Data D24..D29 used for CC32 functional tests.

Data

LED-Status

D23 D22 D21..D3

LED

LED22..LED3

D2 D1 D0

LED

Data

LED-Status

D31 D30 D29

Q X

D28 D27 D26

Inhibit LAM-FF CT1 CT0

D25

D24

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3.14 CAMAC Cycle-Tune-Register

N30*A2*Fx

(Write/Read Word)

N30*A1*Fx

N30*A0*Fx

(Write/Read Word)

For optimized timing it is possible to adjust the CAMAC cycle time (time between begin of BUSY = active to negative edge of S1 strobe signal) for each individual CAMAC station. Possible values are

200ns, 300ns and 400ns (default). In addition the width of the S1 and S2 strobe signals can be set optionally to the shorter value of 100ns.

For each station this is done by defining the 2-bit CT1 and CT0 registers. These registers are in the following named Nx-1 and Nx-0 to consider the station number.

Nx-1,Nx-0 = 00 > 400ns CAMAC-Standard

Nx-1,Nx-0 = 01 > 300ns

Nx-1,Nx-0 = 10 > 200ns

Nx-1,Nx-0 = 11 > 200ns / S1 and S2 = 100ns

DATA

Cycle-tune RegC

Cycle-tune RegB

Cycle-tune RegA

D07

N20-1

N12-1

N4-1

D06

N20-0

N12-0

N4-0

D05

N19-1

N3-1

D04

N18-0

N11-0

N3-0

D04

N18-1

N2-1

D02

N18-0

N10-0

N2-0

D01

N17-1

N9-1

N1-1

D00

N16-0

N9-0

N1-0

DATA

Cycle-tune RegC

Cycle-tune RegB

Cycle-tune RegA

D15

N24-1

N17-1

N8-1

D14

N24-0

N16-0

N8-0

D13

N23-1

N^5-1

N7-1

D12

N23-0

N15-0

N7-0

D11

N22-1

N14-1

N6-1

D10

N22-0

N14-0

N6-0

D09

N21-1

N13-1

N5-1

D08

N21-0

N13-0

N5-0

Attention: These options do not confirm the CAMAC standard. They can be used to improve the data transfer and / or the communication with CAMAC modules. It has to be tested by the user which CAMAC module can be used for different CAMAC cycle timing.

3.15 CC32-Reset

N31*A0*Fx (

Write Word)

Resetting the CC32 initializes the following registers:

•

Inhibit-FF

•

LAM-FF

•

BROADCAST-MASK-, and LAM-MASK-REGISTER

•

CYCLE-TUNE-REGISTER

3.16 Power consumption

Voltage

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Power

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PCI-CAMAC

1,7 A 10,2 W

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3.17 Component location CC32 Control-Station

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U301

U402

U401

U502

U501

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3.18 Component location CC32 Normal-Station

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3.19 CC32 data way connector pin assignment

R14

R12

R10

W22

W20

W18

W16

W14

W12

W10

W24

R24

R22

R20

R18

R16

CC32 pin assignment

Sig.Top

Gnd

Normal-Station

Sig.Bott.

F16

W23

W21

W19

W17

W15

W13

W11

R23

R21

R19

R17

R15

R13

R11

Nr.

Gnd

Contol-Station

Sig.Top

Gnd

Nr.

L11

L10

L24

L23

L22

L21

L20

L19

L18

L17

L16

L15

L14

L13

L12

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Gnd

Sig.Bott.

F16

N24

N23

N22

N21

N20

N19

N18

N17

N16

N15

N14

N13

N12

N11

N10

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Key features

supports FASTCAMAC BASIC level 1
CAMAC cycle time adjustable
S1 and S2 strobe width adjustable
supports 16 and 32-bit PCI bus slave access
programmable interrupt generation
compatible with PCI-VME system

Frequently asked questions

The CC32 CAMAC crate controller provides a way to control and read data from CAMAC modules, which are commonly used in scientific and industrial applications.

The PCIADA interface card acts as a bridge between the CAMAC crate controller (CC32) and the PC's PCI bus, allowing data to be transferred between the two systems.

The PCIADA interface card can generate two types of interrupts: a Timeout Interrupt, which is caused by a timeout during a data transfer, and a LAM-FF Interrupt, which is triggered by a Look-At-Me (LAM) signal from a CAMAC module.