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D a t a S h e e t
( A d v a n c e I n f o r m a t i o n )
7.
Device Operations
This section describes the read and write bus operations, program, erase, simultaneous read/write, handshaking, and reset features of the Flash devices.
The address space of the Flash Memory Array is divided into banks. There are three operation modes for each bank:
Read Mode
Embedded Algorithm (EA) Mode
Address Space Overlay (ASO) Mode
Each bank of the device can be in any operation mode but, only one bank can be in EA or ASO mode at any one time.
In Read Mode a Flash Memory Array bank may be read by simply selecting the memory, supplying the address, and taking read data when it is ready. This is done by asynchronous or burst accesses from the host system bus. The CU puts all banks in Read mode during Power-on, a Hardware Reset, after a Command
Reset, or after a bank is returned to Read mode from EA mode.
During a burst read access valid read data is indicated by the RDY signal being High. When RDY is Low burst read data is not valid and wait states must be added. The use of the RDY signal to indicate when valid data is transferred on the system data bus is called handshaking or flow control.
EA and ASO modes are initiated by writing specific address and data patterns into command registers (see
write bus cycles with the address and data information needed to execute a command. The contents of the registers serve as input to the Control Unit (CU) and the CU dictates the function of the device. Writing incorrect address and data values or writing them in an improper sequence may place the device in an unknown state, in which case the system must write the reset command to return all banks to Read mode.
The Flash memory array data in a bank that is in EA mode, is stable but undefined, and effectively unavailable for read access from the host system. While in EA mode the bank is used by the CU in the execution of commands. Typical command operations are programming or erasing of data in the Flash array.
All other banks are available for read access while the one bank is in EA mode. This ability to read from one bank while another bank is used in the execution of a command is called Simultaneous Read and Write
(SRW) and allows for continued operation of the system via the reading of data or code from other banks while one bank is programming or erasing data as a relatively long time frame background task. Only a status register read command can be used in a bank in EA mode to retrieve the EA status.
While any one of the overlay address spaces are overlaid in a bank (entered) that bank is in ASO mode and no other bank may be in EA or ASO mode. All EA activity must be completed or suspended before entering any ASO mode. A command for entering an EA or ASO mode while another bank is in EA or ASO mode will be ignored.
While an ASO mode is active (entered) in a bank, a read for Flash array data to any other bank is allowed.
ASO mode selects a specific sector for the overlaid address space. Other sectors in the ASO bank still provide Flash array data and may be read during ASO mode.
While SSR Lock, SSR, or Configuration Register is overlaid only the SSR Lock, SSR, or Configuration
Register respectively may be programmed in the overlaid sector. While any of these ASO areas are being programmed the ASO bank switches to EA mode. The ID/CFI and factory portion of the SSR ASO is not customer programmable. An attempt to program in these areas will fail.
July 30, 2012 S29VS_XS-R_00_08 S29VS/XS-R MirrorBit
®
Flash Family 21
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Table of contents
- 3 Features
- 3 General Description
- 3 Performance Characteristics
- 7 Ordering Information
- 7 Valid Combinations
- 8 Input/Output Descriptions & Logic Symbol
- 9 Block Diagrams
- 10 Physical Dimensions/Connection Diagrams
- 10 Related Documents
- 10 Special Handling Instructions for FBGA Package
- 12 Product Overview
- 13 Address Space Maps
- 14 Data Address & Quantity Nomenclature
- 15 Flash Memory Array
- 17 Address/Data Interface
- 18 Bus Operations
- 19 Device ID and CFI (ID-CFI)
- 21 Device Operations
- 22 Asynchronous Read
- 22 Synchronous (Burst) Read Mode and Configuration Register
- 28 Status Register
- 31 Blank Check
- 31 Simultaneous Read/Write
- 32 Writing Commands/Command Sequences
- 32 Program/Erase Operations
- 38 Handshaking
- 39 Hardware Reset
- 39 Software Reset
- 39 Sector Protection/Unprotection
- 39 Sector Lock/Unlock Command
- 40 Sector Lock Range Command
- 40 Hardware Data Protection Methods
- 41 SSR Lock
- 41 Secure Silicon Region
- 43 Power Conservation Modes
- 43 Standby Mode
- 43 Automatic Sleep Mode
- 43 Output Disable (OE#)
- 44 Electrical Specifications
- 44 Absolute Maximum Ratings
- 44 Operating Ranges
- 45 DC Characteristics
- 46 Capacitance
- 46 AC Test Conditions
- 46 Key to Switching Waveforms
- 47 Power Up
- 47 CLK Characterization
- 48 AC Characteristics
- 56 Appendix
- 56 Command Definitions
- 58 Device ID and Common Flash Memory Interface Address Map
- 70 Revision History
- 48 S29VS_XS-R_00_08 July
- 31 Simultaneous Operation Circuit
- 32 44-Ball Very Thin Fine-Pitch Ball Grid Array, Top View, Balls Facing Down
- 33 VDJ044—44-Ball Very Thin Fine-Pitch Ball Grid Array
- 48 Synchronous Read
- 66 Maximum Negative Overshoot Waveform
- 66 Maximum Positive Overshoot Waveform
- 68 Input Pulse and Test Point
- 68 Output Load
- 69 Power-up Diagram
- 69 CLK Characterization
- 70 Synchronous Read Mode - ADM Interface
- 71 Asynchronous Mode Read - ADM Interface
- 72 Asynchronous Program Operation Timings - ADM Interface