datasheet for S29XS256R by Spansion

A/DQ15 - A/DQ0

RDY(with data)

RDY(before data)

CLK

CE#

AVD#

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

Figure 11.7 Synchronous Read Wrapped Burst Address Low Only - AADM Interface t

IA t

CES t

AVDS t

AVDP t

AVDH t

AVDS t

AVDH

OE# low with AVD# low signals the presence of Address-High.

The Address-High cycle is optional. When the high part of address does not change only the Address-Low cycle is needed.

Address-Low only cycle

OE# enables data output only after the Address-Low cycle in which AVD# is Low and OE# is High.

OE# is ignored after OE# returns high between accesses until the next Address-Low is received.

OE#

WE# t

ACS t

ACH

AH AL t

RACC t

CR t

OE t

BACC t

BDH t

RACC t

RACC t

OEZ t

RACC t

RACC

AL t

OE t

BDH t

BACC t

OEZ t

CEZ t

RACC t

RACC

CLK

CE#

A/DQ15-A/DQ0

RDY(with data)

RDY(before data)

AVD#

OE#

WE#

Figure 11.8 Synchronous Read Continuous Burst - AADM Interface tIA tCES tIA

In continuous burst, wait states equal to the internal access time are inserted between the end of one cache line and the start of the next cache line tAVDS tAVDH tAVDP tAVDS tAVDH tBACC tACS tACH tRACC tCR tOE tBACC tBDH tRACC tRACC tRACC tRACC tRACC tOEZ tCEZ

66 S29VS/XS-R MirrorBit

®

Flash Family S29VS_XS-R_00_08 July 30, 2012

A/DQ15-A/DQ0

RDY(with data)

RDY(before data)

CLK

CE#

AVD#

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n ) t

CES

Figure 11.9 Synchronous Read Wrapped Burst - AADM Interface t

IA

15 initial access cycles setting shown. t

IA

measured from CLK rising edge during AVD# Low to CLK rising edge at beginning of first data out.

t

AVDS t

AVDP t

AVDH

OE# low with AVD# low signals the presence of Address-High.

The Address-High cycle is optional. When the high part of address does not change only the Address-Low cycle is needed. t

AVDS t

AVDH

OE# enables data output only after the Address-Low cycle in which AVD# is Low and OE# is High.

OE# is ignored after OE# returns high between accesses until the next Address-Low is received.

OE#

WE# t

BACC t

BDH t

ACS t

ACH

AH AL t

RACC t

CR t

OE t

RACC t

RACC

CLK

CE#

A/DQ15 - A/DQ0

RDY(with data)

RDY(before data)

AVD#

OE#

WE# t

OEZ

Figure 11.10 Synchronous Read Followed By Read Burst - AADM Interface t

IA t

IA t

CES t

AVDS t

AVDP t

AVDH t

AVDS t

AVDH t

ACS t

ACH

AH AL t

RACC t

CR t

OE t

BACC t

BDH t

OEZ t

RACC t

RACC t

RACC t

RACC

AH AL

ASIC_t

CO t

OE t

BACC t

RACC t

RACC t

OEZ t

CEZ t

CEZ t

CEZ

July 30, 2012 S29VS_XS-R_00_08 S29VS/XS-R MirrorBit

®

Flash Family 67