datasheet for S29XS256R by Spansion

D a t a S h e e t

( A d v a n c e I n f o r m a t i o n )

Section

Table Address Latency for 10 -13 Wait

States

Added note

Table Address Latency for 9 Wait States Added note

Figure Synchronous Read

CLK Characterization

Erase and Programming Performance

Revision 06 (July 22, 2010)

DC Characteristics

Performance Characteristics

Removed note 1

Removed note 2

Corrected note 2

Changed I

CC

Description

Read test conditions to OE#=H with relevant values

Updated tables

Changed typical programming times Erase and Programming Performance

Revision 07 (November 18, 2010)

Erase and Programming Performance

ID/CFI Data

Changed maximum chip erase times

Corrected Data and Description for Word Offset 03h, 55h, 56h

Corrected Data for Word Offset 1Dh, 1Eh, 52h

Revision 08 (July 30, 2012)

Command Definitions Corrected number of cycles for Write Buffer Load

July 30, 2012 S29VS_XS-R_00_08 S29VS/XS-R MirrorBit

®

Flash Family 71