- No category
advertisement
▼
Scroll to page 2
of
302
About Code
Examples
This datasheet contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.
8
ATmega8(L)
2486Z–AVR–02/11
advertisement
Related manuals
advertisement
Table of contents
- 1 Features
- 2 Pin Configurations
- 3 Overview
- 3 Block Diagram
- 4 Disclaimer
- 5 Pin Descriptions
- 5 VCC
- 5 GND
- 5 Port B (PB7..PB0) XTAL1/XTAL2/TOSC1/ TOSC2
- 5 Port C (PC5..PC0)
- 5 PC6/RESET
- 5 Port D (PD7..PD0)
- 5 RESET
- 6 AVCC
- 6 AREF
- 6 ADC7..6 (TQFP and QFN/MLF Package Only)
- 7 Resources
- 7 Data Retention
- 8 About Code Examples
- 9 Atmel AVR CPU Core
- 9 Introduction
- 9 Architectural Overview
- 11 Arithmetic Logic Unit – ALU
- 11 Status Register
- 12 General Purpose Register File
- 13 The X-register, Y- register and Z-register
- 13 Stack Pointer
- 13 Instruction Execution Timing
- 14 Reset and Interrupt Handling
- 16 Interrupt Response Time
- 17 AVR ATmega8 Memories
- 17 In-System Reprogrammable Flash Program Memory
- 18 SRAM Data Memory
- 19 Data Memory Access Times
- 19 EEPROM Data Memory
- 19 EEPROM Read/Write Access
- 20 The EEPROM Address Register – EEARH and EEARL
- 20 The EEPROM Data Register – EEDR
- 20 The EEPROM Control Register – EECR
- 23 EEPROM Write during Power-down Sleep Mode
- 23 Preventing EEPROM Corruption
- 24 I/O Memory
- 25 System Clock and Clock Options
- 25 Clock Systems and their Distribution
- 25 CPU Clock – clkCPU
- 25 I/O Clock – clkI/O
- 25 Flash Clock – clkFLASH
- 26 Asynchronous Timer Clock – clkASY
- 26 ADC Clock – clkADC
- 26 Clock Sources
- 27 Crystal Oscillator
- 28 Low-frequency Crystal Oscillator
- 28 External RC Oscillator
- 30 Calibrated Internal RC Oscillator
- 31 Oscillator Calibration Register – OSCCAL
- 32 External Clock
- 32 Timer/Counter Oscillator
- 33 Power Management and Sleep Modes
- 33 MCU Control Register – MCUCR
- 34 Idle Mode
- 34 ADC Noise Reduction Mode
- 34 Power-down Mode
- 34 Power-save Mode
- 35 Standby Mode
- 35 Minimizing Power Consumption
- 35 Analog-to-Digital Converter (ADC)
- 35 Analog Comparator
- 36 Brown-out Detector
- 36 Internal Voltage Reference
- 36 Watchdog Timer
- 36 Port Pins
- 37 System Control and Reset
- 37 Resetting the AVR
- 37 Reset Sources
- 39 Power-on Reset
- 40 External Reset
- 40 Brown-out Detection
- 41 Watchdog Reset
- 41 MCU Control and Status Register – MCUCSR
- 42 Internal Voltage Reference
- 42 Voltage Reference Enable Signals and Start-up Time
- 43 Watchdog Timer
- 43 Watchdog Timer Control Register – WDTCR
- 45 Timed Sequences for Changing the Configuration of the Watchdog Timer
- 45 Safety Level 1 (WDTON Fuse Unprogrammed)
- 45 Safety Level 2 (WDTON Fuse Programmed)
- 46 Interrupts
- 46 Interrupt Vectors in ATmega8
- 49 Moving Interrupts Between Application and Boot Space
- 49 General Interrupt Control Register – GICR
- 51 I/O Ports
- 51 Introduction
- 52 Ports as General Digital I/O
- 52 Configuring the Pin
- 53 Reading the Pin Value
- 55 Digital Input Enable and Sleep Modes
- 56 Unconnected pins
- 56 Alternate Port Functions
- 58 Special Function IO Register – SFIOR
- 58 Alternate Functions of Port B
- 61 Alternate Functions of Port C
- 63 Alternate Functions of Port D
- 65 Register Description for I/O Ports
- 65 The Port B Data Register – PORTB
- 65 The Port B Data Direction Register – DDRB
- 65 The Port B Input Pins Address – PINB
- 65 The Port C Data Register – PORTC
- 65 The Port C Data Direction Register – DDRC
- 65 The Port C Input Pins Address – PINC
- 65 The Port D Data Register – PORTD
- 65 The Port D Data Direction Register – DDRD
- 65 The Port D Input Pins Address – PIND
- 66 External Interrupts
- 66 MCU Control Register – MCUCR
- 67 General Interrupt Control Register – GICR
- 67 General Interrupt Flag Register – GIFR
- 69 8-bit Timer/Counter0
- 69 Overview
- 69 Registers
- 69 Definitions
- 70 Timer/Counter Clock Sources
- 70 Counter Unit
- 70 Operation
- 70 Timer/Counter Timing Diagrams
- 71 8-bit Timer/Counter Register Description
- 71 Timer/Counter Control Register – TCCR0
- 72 Timer/Counter Register – TCNT0
- 72 Timer/Counter Interrupt Mask Register – TIMSK
- 72 Timer/Counter Interrupt Flag Register – TIFR
- 73 Timer/Counter0 and Timer/Counter1 Prescalers
- 73 Internal Clock Source
- 73 Prescaler Reset
- 73 External Clock Source
- 74 Special Function IO Register – SFIOR
- 75 16-bit Timer/Counter1
- 75 Overview
- 76 Registers
- 77 Definitions
- 77 Compatibility
- 77 Accessing 16-bit Registers
- 80 Reusing the Temporary High Byte Register
- 80 Timer/Counter Clock Sources
- 80 Counter Unit
- 81 Input Capture Unit
- 82 Input Capture Pin Source
- 83 Noise Canceler
- 83 Using the Input Capture Unit
- 83 Output Compare Units
- 85 Force Output Compare
- 85 Compare Match Blocking by TCNT1 Write
- 85 Using the Output Compare Unit
- 85 Compare Match Output Unit
- 87 Compare Output Mode and Waveform Generation
- 87 Modes of Operation
- 87 Normal Mode
- 87 Clear Timer on Compare Match (CTC) Mode
- 88 Fast PWM Mode
- 90 Phase Correct PWM Mode
- 92 Phase and Frequency Correct PWM Mode
- 94 Timer/Counter Timing Diagrams
- 96 16-bit Timer/Counter Register Description
- 96 Timer/Counter 1 Control Register A – TCCR1A
- 98 Timer/Counter 1 Control Register B – TCCR1B
- 99 Timer/Counter 1 – TCNT1H and TCNT1L
- 99 Output Compare Register 1 A – OCR1AH and OCR1AL
- 99 Output Compare Register 1 B – OCR1BH and OCR1BL
- 100 Input Capture Register 1 – ICR1H and ICR1L
- 100 Timer/Counter Interrupt Mask Register – TIMSK(1)
- 101 Timer/Counter Interrupt Flag Register – TIFR(1)
- 102 8-bit Timer/Counter2 with PWM and Asynchronous Operation
- 102 Overview
- 103 Registers
- 103 Definitions
- 103 Timer/Counter Clock Sources
- 104 Counter Unit
- 105 Output Compare Unit
- 106 Force Output Compare
- 106 Compare Match Blocking by TCNT2 Write
- 106 Using the Output Compare Unit
- 107 Compare Match Output Unit
- 108 Compare Output Mode and Waveform Generation
- 108 Modes of Operation
- 108 Normal Mode
- 109 Clear Timer on Compare Match (CTC) Mode
- 110 Fast PWM Mode
- 111 Phase Correct PWM Mode
- 112 Timer/Counter Timing Diagrams
- 114 8-bit Timer/Counter Register Description
- 114 Timer/Counter Control Register – TCCR2
- 116 Timer/Counter Register – TCNT2
- 116 Output Compare Register – OCR2
- 117 Asynchronous Operation of the Timer/Counter
- 117 Asynchronous Status Register – ASSR
- 117 Asynchronous Operation of Timer/Counter2
- 119 Timer/Counter Interrupt Mask Register – TIMSK
- 119 Timer/Counter Interrupt Flag Register – TIFR
- 120 Timer/Counter Prescaler
- 120 Special Function IO Register – SFIOR
- 121 Serial Peripheral Interface – SPI
- 125 SS Pin Functionality
- 125 Slave Mode
- 125 Master Mode
- 125 SPI Control Register – SPCR
- 126 SPI Status Register – SPSR
- 127 SPI Data Register – SPDR
- 127 Data Modes
- 129 USART
- 129 Overview
- 130 AVR USART vs. AVR UART – Compatibility
- 130 Clock Generation
- 131 Internal Clock Generation – The Baud Rate Generator
- 132 Double Speed Operation (U2X)
- 132 External Clock
- 132 Synchronous Clock Operation
- 133 Frame Formats
- 134 Parity Bit Calculation
- 134 USART Initialization
- 136 Data Transmission – The USART Transmitter
- 136 Sending Frames with 5 to 8 Data Bits
- 137 Sending Frames with 9 Data Bits
- 137 Transmitter Flags and Interrupts
- 138 Parity Generator
- 138 Disabling the Transmitter
- 138 Data Reception – The USART Receiver
- 138 Receiving Frames with 5 to 8 Data Bits
- 139 Receiving Frames with 9 Data Bits
- 141 Receive Compete Flag and Interrupt
- 141 Receiver Error Flags
- 141 Parity Checker
- 142 Disabling the Receiver
- 142 Flushing the Receive Buffer
- 142 Asynchronous Data Reception
- 142 Asynchronous Clock Recovery
- 143 Asynchronous Data Recovery
- 144 Asynchronous Operational Range
- 145 Multi-processor Communication Mode
- 145 Using MPCM
- 146 Accessing UBRRH/UCSRC Registers
- 146 Write Access
- 147 Read Access
- 148 USART Register Description
- 148 USART I/O Data Register – UDR
- 148 USART Control and Status Register A – UCSRA
- 149 USART Control and Status Register B – UCSRB
- 150 USART Control and Status Register C – UCSRC
- 152 USART Baud Rate Registers – UBRRL and UBRRHs
- 153 Examples of Baud Rate Setting
- 157 Two-wire Serial Interface
- 157 Features
- 157 Two-wire Serial Interface Bus Definition
- 157 TWI Terminology
- 158 Electrical Interconnection
- 158 Data Transfer and Frame Format
- 158 Transferring Bits
- 158 START and STOP Conditions
- 159 Address Packet Format
- 160 Data Packet Format
- 160 Combining Address and Data Packets into a Transmission
- 161 Multi-master Bus Systems, Arbitration and Synchronization
- 163 Overview of the TWI Module
- 163 SCL and SDA Pins
- 164 Bit Rate Generator Unit
- 164 Bus Interface Unit
- 164 Address Match Unit
- 164 Control Unit
- 165 TWI Register Description
- 165 TWI Bit Rate Register – TWBR
- 165 TWI Control Register – TWCR
- 166 TWI Status Register – TWSR
- 167 TWI Data Register – TWDR
- 167 TWI (Slave) Address Register – TWAR
- 168 Using the TWI
- 171 Transmission Modes
- 171 Master Transmitter Mode
- 175 Master Receiver Mode
- 177 Slave Receiver Mode
- 181 Slave Transmitter Mode
- 183 Miscellaneous States
- 184 Combining Several TWI Modes
- 184 Multi-master Systems and Arbitration
- 186 Analog Comparator
- 186 Special Function IO Register – SFIOR
- 186 Analog Comparator Control and Status Register – ACSR
- 188 Analog Comparator Multiplexed Input
- 189 Analog-to- Digital Converter
- 189 Features
- 191 Starting a Conversion
- 191 Prescaling and Conversion Timing
- 194 Changing Channel or Reference Selection
- 194 ADC Input Channels
- 194 ADC Voltage Reference
- 195 ADC Noise Canceler
- 195 Analog Input Circuitry
- 196 Analog Noise Canceling Techniques
- 196 ADC Accuracy Definitions
- 199 ADC Conversion Result
- 199 ADC Multiplexer Selection Register – ADMUX
- 200 ADC Control and Status Register A – ADCSRA
- 201 The ADC Data Register – ADCL and ADCH
- 202 Boot Loader Support – Read- While-Write Self- Programming
- 202 Boot Loader Features
- 202 Application and Boot Loader Flash Sections
- 202 Application Section
- 202 BLS – Boot Loader Section
- 202 Read-While-Write and No Read- While-Write Flash Sections
- 203 RWW – Read-While- Write Section
- 203 NRWW – No Read- While-Write Section
- 204 Boot Loader Lock Bits
- 205 Entering the Boot Loader Program
- 206 Store Program Memory Control Register – SPMCR
- 207 Addressing the Flash During Self- Programming
- 208 Self-Programming the Flash
- 209 Performing Page Erase by SPM
- 209 Filling the Temporary Buffer (Page Loading)
- 209 Performing a Page Write
- 209 Using the SPM Interrupt
- 209 Consideration While Updating BLS
- 209 Prevent Reading the RWW Section During Self-Programming
- 209 Setting the Boot Loader Lock Bits by SPM
- 210 EEPROM Write Prevents Writing to SPMCR
- 210 Reading the Fuse and Lock Bits from Software
- 210 Preventing Flash Corruption
- 211 Programming Time for Flash when using SPM
- 212 Simple Assembly Code Example for a Boot Loader
- 213 ATmega8 Boot Loader Parameters
- 215 Memory Programming
- 215 Program And Data Memory Lock Bits
- 216 Fuse Bits
- 217 Latching of Fuses
- 218 Signature Bytes
- 218 Calibration Byte
- 218 Page Size
- 219 Parallel Programming Parameters, Pin Mapping, and Commands
- 219 Signal Names
- 221 Parallel Programming
- 221 Enter Programming Mode
- 221 Considerations for Efficient Programming
- 221 Chip Erase
- 222 Programming the Flash
- 224 Programming the EEPROM
- 225 Reading the Flash
- 225 Reading the EEPROM
- 225 Programming the Fuse Low Bits
- 226 Programming the Fuse High Bits
- 226 Programming the Lock Bits
- 226 Reading the Fuse and Lock Bits
- 227 Reading the Signature Bytes
- 227 Reading the Calibration Byte
- 227 Parallel Programming Characteristics
- 230 Serial Downloading
- 230 Serial Programming Pin Mapping
- 231 Serial Programming Algorithm
- 231 Data Polling Flash
- 232 Data Polling EEPROM
- 234 SPI Serial Programming Characteristics
- 235 Electrical Characteristics
- 235 Absolute Maximum Ratings*
- 235 DC Characteristics
- 237 External Clock Drive Waveforms
- 237 External Clock Drive
- 238 Two-wire Serial Interface Characteristics
- 239 SPI Timing Characteristics
- 241 ADC Characteristics
- 242 ATmega8 Typical Characteristics
- 242 Active Supply Current
- 246 Idle Supply Current
- 249 Power-down Supply Current
- 250 Power-save Supply Current
- 251 Standby Supply Current
- 255 Pin Pull-up
- 257 Pin Driver Strength
- 261 Pin Thresholds and Hysteresis
- 265 Bod Thresholds and Analog Comparator Offset
- 268 Internal Oscillator Speed
- 274 Current Consumption of Peripheral Units
- 278 Current Consumption in Reset and Reset Pulsewidth
- 280 Register Summary
- 282 Instruction Set Summary
- 285 Ordering Information
- 286 Packaging Information
- 286 32A
- 287 28P3
- 288 32M1-A
- 289 Errata
- 289 ATmega8 Rev. D to I, M
- 291 Datasheet Revision History
- 291 Changes from Rev. 2486Y- 10/10 to Rev. 2486Z- 02/11
- 291 Changes from Rev. 2486X- 06/10 to Rev. 2486Y- 10/10
- 291 Changes from Rev. 2486W- 02/10 to Rev. 2486X- 06/10
- 291 Changes from Rev. 2486V- 05/09 to Rev. 2486W- 02/10
- 291 Changes from Rev. 2486U- 08/08 to Rev. 2486V- 05/09
- 291 Changes from Rev. 2486T- 05/08 to Rev. 2486U- 08/08
- 291 Changes from Rev. 2486S- 08/07 to Rev. 2486T- 05/08
- 292 Changes from Rev. 2486R- 07/07 to Rev. 2486S- 08/07
- 292 Changes from Rev. 2486Q- 10/06 to Rev. 2486R- 07/07
- 292 Changes from Rev. 2486P- 02/06 to Rev. 2486Q- 10/06
- 292 Changes from Rev. 2486O-10/04 to Rev. 2486P- 02/06
- 292 Changes from Rev. 2486N-09/04 to Rev. 2486O-10/04
- 293 Changes from Rev. 2486M-12/03 to Rev. 2486N-09/04
- 293 Changes from Rev. 2486L-10/03 to Rev. 2486M-12/03
- 293 Changes from Rev. 2486K-08/03 to Rev. 2486L-10/03
- 294 Changes from Rev. 2486J-02/03 to Rev. 2486K-08/03
- 294 Changes from Rev. 2486I-12/02 to Rev. 2486J-02/03
- 295 Changes from Rev. 2486H-09/02 to Rev. 2486I-12/02
- 295 Changes from Rev. 2486G-09/02 to Rev. 2486H-09/02
- 295 Changes from Rev. 2486F-07/02 to Rev. 2486G-09/02
- 295 Changes from Rev. 2486E-06/02 to Rev. 2486F-07/02
- 295 Changes from Rev. 2486D-03/02 to Rev. 2486E-06/02
- 295 Changes from Rev. 2486C-03/02 to Rev. 2486D-03/02
- 296 Changes from Rev. 2486B-12/01 to Rev. 2486C-03/02
- 297 Table of Contents