datasheet for ATmega8 by Atmel

Instruction Set Summary

Mnemonics Operands Description

SBR

CBR

INC

DEC

TST

CLR

SER

MUL

SBIW

AND

ANDI

OR

ORI

EOR

COM

NEG

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD Rd, Rr

ADC

ADIW

Rd, Rr

Rdl,K

Add two Registers

Add with Carry two Registers

Add Immediate to Word

SUB

SUBI

SBC

SBCI

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Subtract two Registers

Subtract Constant from Register

Subtract with Carry two Registers

Subtract with Carry Constant from Reg.

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Rd

Subtract Immediate from Word

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Two’s Complement

MULS

MULSU

FMUL

FMULS

FMULSU Rd, Rr

BRANCH INSTRUCTIONS

RJMP

IJMP k

RCALL

ICALL

RET

RETI

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

CPSE

CP

CPC

CPI

SBRC

SBRS

SBIC

SBIS

k

k

k

k s, k s, k

k

k

Rd,K

Rd,K

Rd

Rd

Rd

Rd

Rd

Rd, Rr

Rd, Rr

Rd, Rr

Rd, Rr

Rd, Rr k

Rd,Rr

Rd,Rr

Rd,Rr

Rd,K

Rr, b

Rr, b

P, b

P, b

k

k

k

k

k

k

k

k

k

k

Set Bit(s) in Register

Clear Bit(s) in Register

Increment

Decrement

Test for Zero or Minus

Clear Register

Set Register

Multiply Unsigned

Multiply Signed

Multiply Signed with Unsigned

Fractional Multiply Unsigned

Fractional Multiply Signed

Fractional Multiply Signed with Unsigned

Relative Jump

Indirect Jump to (Z)

Relative Subroutine Call

Indirect Call to (Z)

Subroutine Return

Interrupt Return

Compare, Skip if Equal

Compare

Compare with Carry

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Branch if Not Equal

Branch if Carry Set

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

Branch if Minus

Branch if Plus

Branch if Greater or Equal, Signed

Branch if Less Than Zero, Signed

Branch if Half Carry Flag Set

Branch if Half Carry Flag Cleared

Branch if T Flag Set

Branch if T Flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

282

ATmega8(L)

Operation

Rd

← Rd + Rr

Rd

← Rd + Rr + C

Rdh:Rdl

← Rdh:Rdl + K

Rd

← Rd - Rr

Rd

← Rd - K

Rd

← Rd - Rr - C

Rd

← Rd - K - C

Rdh:Rdl

← Rdh:Rdl - K

Rd

← Rd • Rr

Rd

← Rd • K

Rd

← Rd v Rr

Rd

← Rd v K

Rd

← Rd ⊕ Rr

Rd

← 0xFF − Rd

Rd

← 0x00 − Rd

Rd

← Rd v K

Rd

← Rd • (0xFF - K)

Rd

← Rd + 1

Rd

← Rd − 1

Rd

← Rd • Rd

Rd

← Rd ⊕ Rd

Rd

← 0xFF

R1:R0

← Rd x Rr

R1:R0

← Rd x Rr

R1:R0

← Rd x Rr

R1:R0

← (Rd x Rr)

<< 1

R1:R0

← (Rd x Rr)

<< 1

R1:R0

← (Rd x Rr)

<< 1

PC

← PC + k + 1

PC

← Z

PC

← PC + k + 1

PC

← Z

PC

← STACK

PC

← STACK if (Rd = Rr) PC

← PC + 2 or 3

Rd

− Rr

Rd

− Rr − C

Rd

− K if (Rr(b)=0) PC

← PC + 2 or 3 if (Rr(b)=1) PC

← PC + 2 or 3 if (P(b)=0) PC

← PC + 2 or 3 if (P(b)=1) PC

← PC + 2 or 3 if (SREG(s) = 1) then PC

←PC+k + 1 if (SREG(s) = 0) then PC

←PC+k + 1 if (Z = 1) then PC

← PC + k + 1 if (Z = 0) then PC

← PC + k + 1 if (C = 1) then PC

← PC + k + 1 if (C = 0) then PC

← PC + k + 1 if (C = 0) then PC

← PC + k + 1 if (C = 1) then PC

← PC + k + 1 if (N = 1) then PC

← PC + k + 1 if (N = 0) then PC

← PC + k + 1 if (N

⊕ V= 0) then PC ← PC + k + 1 if (N

⊕ V= 1) then PC ← PC + k + 1 if (H = 1) then PC

← PC + k + 1 if (H = 0) then PC

← PC + k + 1 if (T = 1) then PC

← PC + k + 1 if (T = 0) then PC

← PC + k + 1 if (V = 1) then PC

← PC + k + 1 if (V = 0) then PC

← PC + k + 1

#Clocks

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2 / 3

1

1

1

1 / 2 / 3

1 / 2 / 3

1 / 2 / 3

1 / 2 / 3

4

4

3

3

2

2

2

2

2

2

2

1

2

1

1

1

1

1

1

1

1

1

1

1

1

2

1

1

1

1

1

1

1

2

Flags

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

I

None

Z, N, V, C, H

Z, N, V, C, H

Z, N, V, C, H

None

None

None

None

Z, C

Z, C

Z, C

Z, C

Z, C

Z, N, V

Z, N, V

Z, N, V

Z, N, V

Z, N, V

Z, N, V

None

Z, C

Z, C, N, V, H

Z, C, N, V, H

Z, C, N, V, S

Z, C, N, V, H

Z, C, N, V, H

Z, C, N, V, H

Z, C, N ,V, H

Z, C, N, V, S

Z, N, V

Z, N, V

Z, N, V

Z, N, V

Z, N, V

Z, C, N, V

Z, C, N, V, H

2486Z–AVR–02/11

Instruction Set Summary (Continued)

Mnemonics Operands

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CBI

LSL

LSR

ROL

ROR

ASR

SWAP

BSET

CLZ

SEI

CLI

SES

CLS

SEV

CLV

SET

LD

LD

LD

LD

LDD

LD

LD

LD

BRIE

BRID

k

k

DATA TRANSFER INSTRUCTIONS

MOV Rd, Rr

MOVW

LDI

LD

LD

Rd, Rr

Rd, K

Rd, X

Rd, X+

Rd, - X

Rd, Y

Rd, Y+

Rd, - Y

Rd,Y+q

Rd, Z

Rd, Z+

Rd, -Z

ST

ST

ST

ST

LDD

LDS

ST

ST

Rd, Z+q

Rd, k

X, Rr

X+, Rr

- X, Rr

Y, Rr

Y+, Rr

- Y, Rr

STD

ST

ST

ST

STD

STS

LPM

LPM

Y+q,Rr

Z, Rr

Z+, Rr

-Z, Rr

Z+q,Rr k, Rr

LPM

SPM

IN

OUT

Rd, Z

Rd, Z+

Rd, P

P, Rr

PUSH

POP

Rr

Rd

BIT AND BIT-TEST INSTRUCTIONS

SBI P,b

Rd

Rd

Rd s

P,b

Rd

Rd

Rd s

Rr, b

Rd, b

Description

Branch if Interrupt Enabled

Branch if Interrupt Disabled

Move Between Registers

Copy Register Word

Load Immediate

Load Indirect

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Indirect

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Indirect

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Direct to SRAM

Load Program Memory

Load Program Memory

Load Program Memory and Post-Inc

Store Program Memory

In Port

Out Port

Push Register on Stack

Pop Register from Stack

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

Logical Shift Right

Rotate Left Through Carry

Rotate Right Through Carry

Arithmetic Shift Right

Swap Nibbles

Flag Set

Flag Clear

Bit Store from Register to T

Bit load from T to Register

Set Carry

Clear Carry

Set Negative Flag

Clear Negative Flag

Set Zero Flag

Clear Zero Flag

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Twos Complement Overflow.

Clear Twos Complement Overflow

Set T in SREG

2486Z–AVR–02/11

ATmega8(L)

Operation

if ( I = 1) then PC

← PC + k + 1 if ( I = 0) then PC

← PC + k + 1

Rd

← Rr

Rd+1:Rd

← Rr+1:Rr

Rd

← K

Rd

← (X)

Rd

← (X), X ← X + 1

X

← X - 1, Rd ← (X)

Rd

← (Y)

Rd

← (Y), Y ← Y + 1

Y

← Y - 1, Rd ← (Y)

Rd

← (Y + q)

Rd

← (Z)

Rd

← (Z), Z ← Z+1

Z

← Z - 1, Rd ← (Z)

Rd

← (Z + q)

Rd

← (k)

(X)

← Rr

(X)

← Rr, X ← X + 1

X

← X - 1, (X) ← Rr

(Y)

← Rr

(Y)

← Rr, Y ← Y + 1

Y

← Y - 1, (Y) ← Rr

(Y + q)

← Rr

(Z)

← Rr

(Z)

← Rr, Z ← Z + 1

Z

← Z - 1, (Z) ← Rr

(Z + q)

← Rr

(k)

← Rr

R0

← (Z)

Rd

← (Z)

Rd

← (Z), Z ← Z+1

(Z)

← R1:R0

Rd

← P

P

← Rr

STACK

← Rr

Rd

← STACK

N

← 0

Z

← 1

Z

← 0

I

← 1

I

← 0

S

← 1

S

← 0

V

← 1

V

← 0

T

← 1

I/O(P,b)

← 1

I/O(P,b)

← 0

Rd(n+1)

← Rd(n), Rd(0) ← 0

Rd(n)

← Rd(n+1), Rd(7) ← 0

Rd(0)

←C,Rd(n+1)← Rd(n),C←Rd(7)

Rd(7)

←C,Rd(n)← Rd(n+1),C←Rd(0)

Rd(n)

← Rd(n+1), n=0..6

Rd(3..0)

←Rd(7..4),Rd(7..4)←Rd(3..0)

SREG(s)

← 1

SREG(s)

← 0

T

← Rr(b)

Rd(b)

← T

C

← 1

C

← 0

N

← 1

#Clocks

1 / 2

1 / 2

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

2

1

1

2

1

3

3

2

2

2

2

2

2

2

2

2

2

2

2

2

2

1

1

3

-

2

2

2

2

2

2

2

2

2

2

1

2

2

1

1

Flags

None

None

I

S

Z

I

N

Z

C

N

V

T

S

V

None

None

Z, C, N, V

Z, C, N, V

Z, C, N, V

Z, C, N, V

Z, C, N, V

None

SREG(s)

SREG(s)

T

None

C

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

283

Instruction Set Summary (Continued)

Mnemonics Operands

CLT

SEH

CLH

MCU CONTROL INSTRUCTIONS

NOP

SLEEP

WDR

Description

Clear T in SREG

Set Half Carry Flag in SREG

Clear Half Carry Flag in SREG

No Operation

Sleep

Watchdog Reset

T

← 0

H

← 1

H

← 0

Operation

(see specific descr. for Sleep function)

(see specific descr. for WDR/timer)

Flags

T

H

H

None

None

None

#Clocks

1

1

1

1

1

1

284

ATmega8(L)

2486Z–AVR–02/11