datasheet for ATmega8 by Atmel

ATmega8(L)

Analog-to-

Digital

Converter

Features

•

10-bit Resolution

•

0.5 LSB Integral Non-linearity

•

±2 LSB Absolute Accuracy

•

13µs - 260µs Conversion Time

•

Up to 15 kSPS at Maximum Resolution

•

6 Multiplexed Single Ended Input Channels

•

2 Additional Multiplexed Single Ended Input Channels (TQFP and QFN/MLF Package only)

•

Optional Left Adjustment for ADC Result Readout

•

0 - V

CC

ADC Input Voltage Range

•

Selectable 2.56V ADC Reference Voltage

•

Free Running or Single Conversion Mode

•

Interrupt on ADC Conversion Complete

•

Sleep Mode Noise Canceler

The ATmega8 features a 10-bit successive approximation ADC. The ADC is connected to an 8channel Analog Multiplexer which allows eight single-ended voltage inputs constructed from the pins of Port C. The single-ended voltage inputs refer to 0V (GND).

The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is

held at a constant level during conversion. A block diagram of the ADC is shown in Figure 90 on page 190

.

The ADC has a separate analog supply voltage pin, AV

CC

. AV

CC

must not differ more than ±0.3V

from V

CC

. See the paragraph

“ADC Noise Canceler” on page 195

on how to connect this pin.

Internal reference voltages of nominally 2.56V or AV

CC

are provided On-chip. The voltage reference may be externally decoupled at the AREF pin by a capacitor for better noise performance.

189

2486Z–AVR–02/11

Figure 90. Analog to Digital Converter Block Schematic Operation

ADC CONVERSION

COMPLETE IRQ

8-BIT DATA BUS

ADC MULTIPLEXER

SELECT (ADMUX)

ADC CTRL. & STATUS

REGISTER (ADCSRA)

15

ADC DATA REGISTER

(ADCH/ADCL)

0

MUX DECODER

190

PRESCALER

CONVERSION LOGIC

AVCC

AREF

INTERNAL 2.56V

REFERENCE

10-BIT DAC

SAMPLE & HOLD

COMPARATOR

-

+

GND

ADC3

ADC2

ADC1

ADC0

ADC7

ADC6

ADC5

ADC4

BANDGAP

REFERENCE

INPUT

MUX

ADC MULTIPLEXER

OUTPUT

The ADC converts an analog input voltage to a 10-bit digital value through successive approximation. The minimum value represents GND and the maximum value represents the voltage on the AREF pin minus 1 LSB. Optionally, AV

CC

or an internal 2.56V reference voltage may be connected to the AREF pin by writing to the REFSn bits in the ADMUX Register. The internal voltage reference may thus be decoupled by an external capacitor at the AREF pin to improve noise immunity.

The analog input channel is selected by writing to the MUX bits in ADMUX. Any of the ADC input pins, as well as GND and a fixed bandgap voltage reference, can be selected as single ended inputs to the ADC. The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and input channel selections will not go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is recommended to switch off the ADC before entering power saving sleep modes.

The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and

ADCL. By default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the ADLAR bit in ADMUX.

ATmega8(L)

2486Z–AVR–02/11

ATmega8(L)

If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read

ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the Data

Registers belongs to the same conversion. Once ADCL is read, ADC access to Data Registers is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is read, neither register is updated and the result from the conversion is lost. When ADCH is read,

ADC access to the ADCH and ADCL Registers is re-enabled.

The ADC has its own interrupt which can be triggered when a conversion completes. When ADC access to the Data Registers is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if the result is lost.

Starting a

Conversion

A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC.

This bit stays high as long as the conversion is in progress and will be cleared by hardware when the conversion is completed. If a different data channel is selected while a conversion is in progress, the ADC will finish the current conversion before performing the channel change.

In Free Running mode, the ADC is constantly sampling and updating the ADC Data Register.

Free Running mode is selected by writing the ADFR bit in ADCSRA to one. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not.

Prescaling and

Conversion Timing

Figure 91. ADC Prescaler

ADEN

START

CK

Reset

7-BIT ADC PRESCALER

2486Z–AVR–02/11

ADPS0

ADPS1

ADPS2

ADC CLOCK SOURCE

By default, the successive approximation circuitry requires an input clock frequency between

50kHz and 200kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the input clock frequency to the ADC can be higher than 200kHz to get a higher sample rate.

The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU frequency above 100kHz. The prescaling is set by the ADPS bits in ADCSRA.

The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low.

When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle. A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched on (ADEN in ADCSRA is set) takes

25 ADC clock cycles in order to initialize the analog circuitry.

191

The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conversion and 13.5 ADC clock cycles after the start of an first conversion. When a conversion is complete, the result is written to the ADC Data Registers, and ADIF is set. In single conversion mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new conversion will be initiated on the first rising ADC clock edge.

In Free Running mode, a new conversion will be started immediately after the conversion com-

pletes, while ADSC remains high. For a summary of conversion times, see Table 73 on page

193 .

Figure 92. ADC Timing Diagram, First Conversion (Single Conversion Mode)

First Conversion

Next

Conversion

Cycle Number

ADC Clock

ADEN

ADSC

ADIF

ADCH

ADCL

1 2 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3

MSB of Result

LSB of Result

MUX and REFS

Update

MUX and REFS

Update

Sample & Hold

Conversion

Complete

Figure 93. ADC Timing Diagram, Single Conversion

One Conversion

1 2 3 4 5 6 7 8 9 10 11 12 13

Cycle Number

ADC Clock

ADSC

ADIF

ADCH

ADCL

Sample & Hold

MUX and REFS

Update

Conversion

Complete

Next Conversion

1 2 3

MSB of Result

LSB of Result

MUX and REFS

Update

192

ATmega8(L)

2486Z–AVR–02/11

2486Z–AVR–02/11

Figure 94. ADC Timing Diagram, Free Running Conversion

One Conversion Next Conversion

Cycle Number

11

ADC Clock

12 13 1

ADSC

ADIF

ADCH

ADCL

2 3

MSB of Result

LSB of Result

4

Conversion

Complete

Sample &Hold

MUX and REFS

Update

ATmega8(L)

Table 73. ADC Conversion Time

Condition

Extended conversion

Normal conversions, single ended

Sample & Hold (Cycles from Start of Conversion)

13.5

1.5

Conversion Time

(Cycles)

25

13

193

Changing Channel or Reference

Selection

The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access. This ensures that the channels and reference selection only takes place at a safe point during the conversion. The channel and reference selection is continuously updated until a conversion is started. Once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Continuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in

ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge after

ADSC is written. The user is thus advised not to write new channel or reference selection values to ADMUX until one ADC clock cycle after ADSC is written.

If both ADFR and ADEN is written to one, an interrupt event can occur at any time. If the

ADMUX Register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. ADMUX can be safely updated in the following ways:

1.

When ADFR or ADEN is cleared

2.

During conversion, minimum one ADC clock cycle after the trigger event

3.

After a conversion, before the Interrupt Flag used as trigger source is cleared

When updating ADMUX in one of these conditions, the new settings will affect the next ADC conversion.

ADC Input Channels

ADC Voltage

Reference

When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected:

In Single Conversion mode, always select the channel before starting the conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the conversion to complete before changing the channel selection.

In Free Running mode, always select the channel before starting the first conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the first conversion to complete, and then change the channel selection. Since the next conversion has already started automatically, the next result will reflect the previous channel selection. Subsequent conversions will reflect the new channel selection.

The reference voltage for the ADC (V

REF

) indicates the conversion range for the ADC. Single ended channels that exceed V

REF either AV

CC

will result in codes close to 0x3FF. V

, internal 2.56V reference, or external AREF pin.

REF

can be selected as

AV

CC

is connected to the ADC through a passive switch. The internal 2.56V reference is generated from the internal bandgap reference (V

BG

) through an internal amplifier. In either case, the external AREF pin is directly connected to the ADC, and the reference voltage can be made more immune to noise by connecting a capacitor between the AREF pin and ground. V

REF also be measured at the AREF pin with a high impedant voltmeter. Note that V

REF impedant source, and only a capacitive load should be connected in a system.

can

is a high

If the user has a fixed voltage source connected to the AREF pin, the user may not use the other reference voltage options in the application, as they will be shorted to the external voltage. If no external voltage is applied to the AREF pin, the user may switch between AV

CC

and 2.56V as reference selection. The first ADC conversion result after switching reference voltage source may be inaccurate, and the user is advised to discard this result.

194

ATmega8(L)

2486Z–AVR–02/11

ATmega8(L)

ADC Noise

Canceler

The ADC features a noise canceler that enables conversion during sleep mode to reduce noise induced from the CPU core and other I/O peripherals. The noise canceler can be used with ADC

Noise Reduction and Idle mode. To make use of this feature, the following procedure should be used:

1.

Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must be selected and the ADC conversion complete interrupt must be enabled

2.

Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion once the CPU has been halted

3.

If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake up the CPU and execute the ADC Conversion Complete interrupt routine. If another interrupt wakes up the CPU before the ADC conversion is complete, that interrupt will be executed, and an ADC Conversion Complete interrupt request will be generated when the ADC conversion completes. The CPU will remain in Active mode until a new sleep command is executed

Note that the ADC will not be automatically turned off when entering other sleep modes than Idle mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before entering such sleep modes to avoid excessive power consumption.

Analog Input Circuitry

The analog input circuitry for single ended channels is illustrated in Figure 95. An analog source

applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regardless of whether that channel is selected as input for the ADC. When the channel is selected, the source must drive the S/H capacitor through the series resistance (combined resistance in the input path).

The ADC is optimized for analog signals with an output impedance of approximately 10 kΩ or less. If such a source is used, the sampling time will be negligible. If a source with higher impedance is used, the sampling time will depend on how long time the source needs to charge the

S/H capacitor, with can vary widely. The user is recommended to only use low impedant sources with slowly varying signals, since this minimizes the required charge transfer to the S/H capacitor.

Signal components higher than the Nyquist frequency (f

ADC

/2) should not be present for either kind of channels, to avoid distortion from unpredictable signal convolution. The user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the ADC.

Figure 95. Analog Input Circuitry

ADCn

I

IH

I

IL

1..100kΩ

C

S /H

= 14pF

V

CC

/2

195

2486Z–AVR–02/11

Analog Noise

Canceling Techniques

Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques:

1.

Keep analog signal paths as short as possible. Make sure analog tracks run over the ground plane, and keep them well away from high-speed switching digital tracks.

2.

The AV

CC

pin on the device should be connected to the digital V an LC network as shown in

Figure 96 .

CC

supply voltage via

3.

Use the ADC noise canceler function to reduce induced noise from the CPU.

4.

If any ADC [3..0] port pins are used as digital outputs, it is essential that these do not switch while a conversion is in progress. However, using the Two-wire Interface

(ADC4 and ADC5) will only affect the conversion on ADC4 and ADC5 and not the other ADC channels.

Figure 96. ADC Power Connections

ADC Accuracy

Definitions

PC1 (ADC1)

PC0 (ADC0)

ADC7

GND

AREF

ADC6

AVCC

PB5

An n-bit single-ended ADC converts a voltage linearly between GND and V

REF

in 2 n

steps

(LSBs). The lowest code is read as 0, and the highest code is read as 2 n

-1.

Several parameters describe the deviation from the ideal behavior:

• Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition

(at 0.5 LSB). Ideal value: 0 LSB

196

ATmega8(L)

2486Z–AVR–02/11

2486Z–AVR–02/11

ATmega8(L)

Figure 97. Offset Error

Output Code

Ideal ADC

Actual ADC

Offset

Error

V

REF

Input Voltage

• Gain error: After adjusting for offset, the gain error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum).

Ideal value: 0 LSB

Figure 98. Gain Error

Output Code

Gain

Error

Ideal ADC

Actual ADC

V

REF

Input Voltage

197

• Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0

LSB

Figure 99. Integral Non-linearity (INL)

Output Code

Ideal ADC

Actual ADC

V

REF

Input Voltage

• Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0

LSB.

Figure 100. Differential Non-linearity (DNL)

Output Code

0x3FF

1 LSB

DNL

0x000

0

V

REF

Input Voltage

• Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ±0.5 LSB.

• Absolute accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code. This is the compound effect of offset, gain error, differential error, non-linearity, and quantization error. Ideal value: ±0.5 LSB.

198

ATmega8(L)

2486Z–AVR–02/11

ATmega8(L)

ADC Conversion

Result

After the conversion is complete (ADIF is high), the conversion result can be found in the ADC

Result Registers (ADCL, ADCH).

For single ended conversion, the result is:

ADC

=

V

IN

V

⋅

1024

REF

where V

IN

is the voltage on the selected input pin and V

REF

the selected voltage reference (see

Table 74 and Table 75 ). 0x000 represents ground, and 0x3FF represents the selected reference

voltage minus one LSB.

ADC Multiplexer

Selection Register –

ADMUX

Bit

Read/Write

Initial Value

7

REFS1

R/W

0

6

REFS0

R/W

0

5

ADLAR

R/W

0

R

0

4

–

3

MUX3

R/W

0

2

MUX2

R/W

0

1

MUX1

R/W

0

0

MUX0

R/W

0

ADMUX

• Bit 7:6 – REFS1:0: Reference Selection Bits

These bits select the voltage reference for the ADC, as shown in

Table 74 . If these bits are

changed during a conversion, the change will not go in effect until this conversion is complete

(ADIF in ADCSRA is set). The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.

Table 74. Voltage Reference Selections for ADC

REFS1 REFS0 Voltage Reference Selection

0

0

1

1

0

1

0

1

AREF, Internal V ref

turned off

AV

CC

with external capacitor at AREF pin

Reserved

Internal 2.56V Voltage Reference with external capacitor at AREF pin

• Bit 5 – ADLAR: ADC Left Adjust Result

The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.

Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the

ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conversions. For a complete description of this bit, see

“The ADC Data Register – ADCL and ADCH” on page 201

.

• Bits 3:0 – MUX3:0: Analog Channel Selection Bits

The value of these bits selects which analog inputs are connected to the ADC. See Table 75

for details.

If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set).

Table 75. Input Channel Selections

MUX3..0

0000

0001

0010

0011

0100

0101

Single Ended Input

ADC0

ADC1

ADC2

ADC3

ADC4

ADC5

199

2486Z–AVR–02/11

Table 75. Input Channel Selections (Continued)

MUX3..0

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Single Ended Input

ADC6

ADC7

1.30V (V

BG

)

0V (GND)

ADC Control and

Status Register A –

ADCSRA

Bit

Read/Write

Initial Value

7

ADEN

R/W

0

6

ADSC

R/W

0

5

ADFR

R/W

0

4

ADIF

R/W

0

3

ADIE

R/W

0

2

ADPS2

R/W

0

1

ADPS1

R/W

0

0

ADPS0

R/W

0

ADCSRA

• Bit 7 – ADEN: ADC Enable

Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the

ADC off while a conversion is in progress, will terminate this conversion.

• Bit 6 – ADSC: ADC Start Conversion

In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode, write this bit to one to start the first conversion. The first conversion after ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initialization of the ADC.

ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. Writing zero to this bit has no effect.

• Bit 5 – ADFR: ADC Free Running Select

When this bit is set (one) the ADC operates in Free Running mode. In this mode, the ADC samples and updates the Data Registers continuously. Clearing this bit (zero) will terminate Free

Running mode.

• Bit 4 – ADIF: ADC Interrupt Flag

This bit is set when an ADC conversion completes and the Data Registers are updated. The

ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set.

ADIF is cleared by hardware when executing the corresponding interrupt Handling Vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-

Write on ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used.

• Bit 3 – ADIE: ADC Interrupt Enable

When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Interrupt is activated.

200

ATmega8(L)

2486Z–AVR–02/11

ATmega8(L)

The ADC Data

Register – ADCL and

ADCH

ADLAR = 0

Bit

Read/Write

Initial Value 0

0

R

R

15

–

ADC7

7

0

0

R

R

14

–

ADC6

6

0

0

R

R

13

–

ADC5

5

0

0

R

R

12

–

ADC4

4

0

0

R

R

11

–

ADC3

3

0

0

R

R

10

–

ADC2

2

0

0

R

R

9

ADC9

ADC1

1

0

0

R

R

8

ADC8

ADC0

0

ADCH

ADCL

ADLAR = 1

• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits

These bits determine the division factor between the XTAL frequency and the input clock to the

ADC.

Table 76. ADC Prescaler Selections

ADPS2

0

0

0

1

1

0

1

1

ADPS1

0

0

1

0

1

1

0

1

ADPS0

0

1

0

1

0

1

0

1

Division Factor

2

2

4

8

16

32

64

128

Bit

Read/Write

Initial Value 0

0

R

R

15

ADC9

ADC1

7

0

0

R

R

14

ADC8

ADC0

6

0

0

R

R

13

ADC7

–

5

0

0

R

R

12

ADC6

–

4

0

0

R

R

11

ADC5

–

3

0

0

R

R

10

ADC4

–

2

0

0

R

R

9

ADC3

–

1

0

0

R

R

8

ADC2

–

0

ADCH

ADCL

When an ADC conversion is complete, the result is found in these two registers.

When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read

ADCH. Otherwise, ADCL must be read first, then ADCH.

The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted.

• ADC9:0: ADC Conversion result

These bits represent the result from the conversion, as detailed in

“ADC Conversion Result” on page 199

.

201

2486Z–AVR–02/11