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ATmega8(L)
System Control and Reset
Resetting the AVR
Reset Sources
During Reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the boot section or vice versa. The circuit diagram in
shows the Reset Logic.
Table 15 on page 38 defines the electrical parameters of the reset circuitry.
The I/O ports of the AVR are immediately reset to their initial state when a reset source goes active. This does not require any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This allows the power to reach a stable level before normal operation starts. The time-out period of the delay counter is defined by the user through the CKSEL Fuses. The different selec-
tions for the delay period are presented in “Clock Sources” on page 26
.
The ATmega8 has four sources of Reset:
• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V
POT
)
• External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length
• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the
Watchdog is enabled
• Brown-out Reset. The MCU is reset when the supply voltage V
CC
is below the Brown-out
Reset threshold (V
BOT
) and the Brown-out Detector is enabled
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2486Z–AVR–02/11
Figure 14. Reset Logic
DATA BUS
MCU Control and Status
Register (MCUCSR)
BODEN
BODLEVEL
Pull-up Resistor
Brown-Out
Reset Circuit
SPIKE
FILTER
38
Watchdog
Oscillator
Clock
Generator
CKSEL[3:0]
SUT[1:0]
CK
Delay Counters
TIMEOUT
Table 15. Reset Characteristics
Symbol Parameter
Power-on Reset Threshold
V
POT
Power-on Reset Threshold
Voltage (falling)
V
RST
RESET Pin Threshold Voltage t
RST
Minimum pulse width on
RESET Pin
Condition Min
0.2
Typ
1.4
1.3
Max
2.3
2.3
0.9
1.5
Units
V
V
CC
µs
V t
BOT
BOD
Brown-out Reset Threshold
Minimum low voltage period for
Brown-out Detection
BODLEVEL = 1 2.4
BODLEVEL = 0 3.7
BODLEVEL = 1
BODLEVEL = 0
2.6
4.0
2
2
2.9
4.5
V
µs
V
HYST
Brown-out Detector hysteresis 130 mV
Notes: 1. The Power-on Reset will not work unless the supply voltage has been below V
POT
(falling)
2. V
BOT
may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is tested down to V
CC
= V
BOT
during the production test. This guarantees that a Brown-out Reset will occur before V
CC
drops to a voltage where correct operation of the microcontroller is no longer guaranteed. The test is performed using
BODLEVEL = 1 for ATmega8L and BODLEVEL = 0 for ATmega8. BODLEVEL = 1 is not applicable for ATmega8
ATmega8(L)
2486Z–AVR–02/11
Power-on Reset
ATmega8(L)
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level
is defined in Table 15 on page 38
. The POR is activated whenever V
CC
is below the detection level. The POR circuit can be used to trigger the Start-up Reset, as well as to detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the
Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after V
CC
rise. The RESET signal is activated again, without any delay, when V
CC
decreases below the detection level.
Figure 15. MCU Start-up, RESET Tied to V
CC
V
POT
V
CC
V
RST
RESET
TIME-OUT t
TOUT
INTERNAL
RESET
Figure 16. MCU Start-up, RESET Extended Externally
V
POT
V
CC
V
RST
RESET t
TOUT
TIME-OUT
INTERNAL
RESET
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2486Z–AVR–02/11
External Reset
An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see
Table 15 on page 38 ) will generate a reset, even if the clock is not
running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – V
RST
on its positive edge, the delay counter starts the
MCU after the time-out period t
TOUT
has expired.
Figure 17. External Reset During Operation
CC
Brown-out Detection
ATmega8 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V
CC
level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the fuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed), or 4.0V (BODLEVEL programmed). The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as
V
BOT+
= V
BOT
+ V
HYST
/2 and V
BOT-
= V
BOT
- V
HYST
/2.
The BOD circuit can be enabled/disabled by the fuse BODEN. When the BOD is enabled
(BODEN programmed), and V
CC
decreases to a value below the trigger level (V
BOT-
in
), the Brown-out Reset is immediately activated. When V
CC
increases above the trigger level
(V
BOT+
in expired.
), the delay counter starts the MCU after the time-out period t
TOUT
has
The BOD circuit will only detect a drop in V
CC
if the voltage stays below the trigger level for longer than t
BOD
given in
.
Figure 18. Brown-out Reset During Operation
V
CC
V
BOT-
V
BOT+
RESET t
TOUT TIME-OUT
INTERNAL
RESET
40
ATmega8(L)
2486Z–AVR–02/11
Watchdog Reset
ATmega8(L)
When the Watchdog times out, it will generate a short reset pulse of 1 CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the time-out period t
TOUT
for details on operation of the Watchdog Timer.
. Refer to
Figure 19. Watchdog Reset During Operation
CC
CK
MCU Control and
Status Register –
MCUCSR
The MCU Control and Status Register provides information on which reset source caused an
MCU Reset.
Bit
Read/Write
Initial Value
R
0
7
–
R
0
6
–
R
0
5
–
R
0
4
–
3
WDRF
R/W
2
BORF
1
EXTRF
R/W R/W
See Bit Description
0
PORF
R/W
MCUCSR
• Bit 7..4 – Res: Reserved Bits
These bits are reserved bits in the ATmega8 and always read as zero.
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.
• Bit 2 – BORF: Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.
• Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.
• Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.
To make use of the Reset Flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags.
41
2486Z–AVR–02/11
Internal Voltage
Reference
Voltage Reference
Enable Signals and
Start-up Time
ATmega8 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. The 2.56V reference to the ADC is generated from the internal bandgap reference.
The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in
Table 16 . To save power, the reference is not always turned on. The ref-
erence is on during the following situations:
1.
When the BOD is enabled (by programming the BODEN Fuse)
2.
When the bandgap reference is connected to the Analog Comparator (by setting the
ACBG bit in ACSR)
3.
When the ADC is enabled
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user must always allow the reference to start up before the output from the Analog Comparator or
ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode.
Table 16. Internal Voltage Reference Characteristics
Symbol Parameter
V
BG t
BG
I
BG
Bandgap reference voltage
Bandgap reference start-up time
Bandgap reference current consumption
Min
1.15
Typ
1.30
40
10
Max
1.40
70
Units
V
µs
µA
42
ATmega8(L)
2486Z–AVR–02/11
ATmega8(L)
Watchdog Timer
The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1MHz. This is the typical value at V
CC
= 5V. See characterization data for typical values at other V
CC
levels. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as
. The WDR – Watchdog Reset – instruction resets the Watchdog
Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs.
Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATmega8 resets and executes from the
Reset Vector. For timing details on the Watchdog Reset, refer to page 41 .
To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be followed when the Watchdog is disabled. Refer to
“Watchdog Timer Control Register – WDTCR”
for details.
Figure 20. Watchdog Timer
WATCHDOG
OSCILLATOR
Watchdog Timer
Control Register –
WDTCR
Bit
Read/Write
Initial Value
R
0
7
–
R
0
6
–
R
0
5
–
4
WDCE
R/W
0
3
WDE
R/W
0
2
WDP2
R/W
0
1
WDP1
R/W
0
0
WDP0
R/W
0
WDTCR
• Bits 7..5 – Res: Reserved Bits
These bits are reserved bits in the ATmega8 and will always read as zero.
• Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to
3 – WDE: Watchdog Enable” on page 44
for a Watchdog disable procedure. In Safety Level 1 and 2, this bit must also be set when changing the prescaler bits. See the Code Examples on
43
2486Z–AVR–02/11
• Bit 3 – WDE: Watchdog Enable
When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the following procedure must be followed:
1.
In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE even though it is set to one before the disable operation starts
2.
Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog
• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0
The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding Timeout Periods are shown in
.
Table 17. Watchdog Timer Prescale Select
WDP2 WDP1 WDP0
0
0
0
0
0
1
1
1
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
1
Number of WDT
Oscillator Cycles
16K (16,384)
32K (32,768)
64K (65,536)
128K (131,072)
256K (262,144)
512K (524,288)
1,024K (1,048,576)
2,048K (2,097,152)
Typical Time-out at V
CC
= 3.0V
17.1ms
34.3ms
68.5ms
0.14s
0.27s
0.55s
1.1s
2.2s
Typical Time-out at V
CC
= 5.0V
16.3ms
32.5ms
65ms
0.13s
0.26s
0.52s
1.0s
2.1s
The following code example shows one assembly and one C function for turning off the WDT.
The example assumes that interrupts are controlled (for example, by disabling interrupts globally) so that no interrupts will occur during execution of these functions.
44
ATmega8(L)
2486Z–AVR–02/11
ATmega8(L)
Timed Sequences for Changing the
Configuration of the Watchdog
Timer
The sequence for changing the Watchdog Timer configuration differs slightly between the safety levels. Separate procedures are described for each level.
Assembly Code Example
WDT_off:
; reset WDT
WDR
; Write logical one to WDCE and WDE
in
r16, WDTCR
ori
r16, (1<<WDCE)|(1<<WDE)
out
WDTCR, r16
; Turn off WDT
ldi
r16, (0<<WDE)
out
WDTCR, r16
ret
C Code Example
void
WDT_off(void)
{
/* reset WDT */
_WDR();
/* Write logical one to WDCE and WDE */
WDTCR |= (1<<WDCE) | (1<<WDE);
/* Turn off WDT */
WDTCR = 0x00;
}
Safety Level 1
(WDTON Fuse
Unprogrammed)
Safety Level 2
(WDTON Fuse
Programmed)
In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit to 1 without any restriction. A timed sequence is needed when changing the Watchdog Time-out period or disabling an enabled Watchdog Timer. To disable an enabled Watchdog Timer and/or changing the Watchdog Time-out, the following procedure must be followed:
1.
In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit
2.
Within the next four clock cycles, in the same operation, write the WDE and WDP bits as desired, but with the WDCE bit cleared
In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A timed sequence is needed when changing the Watchdog Time-out period. To change the
Watchdog Time-out, the following procedure must be followed:
1.
In the same operation, write a logical one to WDCE and WDE. Even though the WDE always is set, the WDE must be written to one to start the timed sequence
Within the next four clock cycles, in the same operation, write the WDP bits as desired, but with the WDCE bit cleared. The value written to the WDE bit is irrelevant.
45
2486Z–AVR–02/11
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