The STA350Bx is an integrated solution of digital audio processing, digital amplifier control, and FFX-power output stage, thereby creating a high-power single-chip FFX

™

solution comprising high-quality, high-efficiency, and all-digital amplification.

The STA350Bx is based on an FFX (fully flexible amplification) processor, a proprietary technology from STMicroelectronics. FFX is the evolution and the enlargement of ST’s ternary technology: the new processor can be configured to work in ternary, binary, binary differential and phase-shift PWM modulation schemes.

The STA350Bx contains the ternary, binary and binary differential implementations, a subset of the full capability of the FFX processor.

The STA350Bx is part of the Sound Terminal

® family that provides full digital audio streaming to the speaker, offering cost effectiveness, low power dissipation and sound enrichment.

The STA350Bx power section consists of four independent half-bridges. These can be configured via digital control to operate in different modes. 2.1 channels can be provided by two half-bridges and a single full-bridge, providing up to 2 x 18 W + 1 x 40 W of music output power, by using standard 4 and 8 Ω speakers. Two channels can be provided by two fullbridges, providing up to 2 x 50 W of music power, by using standard 6 Ω speaker or

2 x 40 W by using 8 Ω speakers at 25 V. The IC can also be configured as 2.1 channels with

2 x 40 W provided by the device and external power for FFX power drive. If configured as mono-BTL, the latter is capable of providing up to 1 x 90 W on a standard 3 Ω load or

1 x 75 W by using a 4 Ω , setting the supply voltage at 25 V. Please refer to the package thermal characteristics and application suggestions for more details.

Also provided in the STA350Bx are a full assortment of digital processing features. This includes up to 8 programmable biquads (EQ) per channel. Special digital signal processing techniques are available in order to manage low-frequency quantization noise in case of very low frequency cutoff filter thresholds. The coefficient range -4..4 allows the easy implementation of high shelf filters. Available presets allow the advantage of earlier time-tomarket by substantially reducing the amount of software development needed for certain functions. This includes audio preset volume loudness, preset volume curves and preset EQ settings. There are also new advanced AM radio interference reduction modes. Dual-band

DRC dynamically equalizes the system to provide speaker linear frequency response regardless of output power level. This feature independently processes the two bands, controlling dynamically the output power level in each band and so providing better sound clarity.

The serial audio data input interface accepts all possible formats, including the popular I

S format. Three channels of FFX processing are provided. This high-quality conversion from

PCM audio to FFX PWM switching waveform provides over 100 dB SNR and dynamic range.

12/94 DocID018572 Rev 7

STA350B, STA350BW

S in ter fa ce

PLL

D ig ita l DSP

Figure 1. Block diagram

Pro tection cur re nt/the rm al

C han nel

Vo lu me contr ol

F F X

Pow er co ntro l

Log ic

C hann el

Ch anne l

R egulat ors

Bias

C hann el

Po wer

Description

AM045167v1

DocID018572 Rev 7 13/94

Pin connections STA350B, STA350BW

Figure 2. Pin connection PowerSSO-36 (top view for STA350BW, bottom view for

STA350B)

GND_SUB

TEST_MODE

VSS

VCC_REG

OUT2B

GND2

VCC2

OUT2A

OUT1B

VCC1

GND1

OUT1A

GND_REG

VDD

CONFIG

OUT3B/FFX3B

OUT3A/FFX3A

D05AU1638

VDD_DIG

GND_DIG

SCL

SDA

INT_LINE

RESET

SDI

LRCKI

BICKI

XTI

GND_PLL

FILTER_PLL

VDD_PLL

PWRDN

GND_DIG

VDD_DIG

TWARN/OUT4A

EAPD/OUT4B

AM045168v1

14/94

Pin

Type

GND

I/O

GND

Power

Table 1. Pin description

Name Description

GND_SUB

Substrate ground

C select address (pull-down)

TEST_MODE This pin must be connected to ground (pull-down)

VSS

VCC_REG

OUT2B

Internal reference at Vcc-3.3 V

Internal Vcc reference

Output half-bridge 2B

GND2

VCC2

OUT2A

Power negative supply

Power positive supply

Output half-bridge 2A

DocID018572 Rev 7

Pin

STA350B, STA350BW Pin connections

I/O

GND

Power

GND

Power

GND

Type

Power

GND

Power

Table 1. Pin description (continued)

Name Description

VDD_PLL

FILTER_PLL

GND_PLL

XTI

BICKI

LRCKI

SDI

RESET

INT_LINE

SDA

SCL

GND_DIG

VDD_DIG

OUT1B

VCC1

GND1

OUT1A

GND_REG

VDD

Output half-bridge 1B

Power positive supply

Power negative supply

Output half-bridge 1A

Internal ground reference

Internal 3.3 V reference voltage

CONFIG Parallel mode command

OUT3B/FFX3B PWM out CH3B / external bridge driver

OUT3A/FFX3A PWM out CH3A / external bridge driver

EAPD/OUT4B Power-down for external bridge / PWM out CH4B

TWARN/OUT4A

Thermal warning from external bridge (pull-up when input)

/ PWM out CH4A

VDD_DIG

GND_DIG

PWRDN

Digital supply voltage

Digital ground

Power down (pull-up)

Positive supply for PLL

Connection to PLL filter

Negative supply for PLL

PLL input clock

S serial clock

S left/right clock

S serial data channels 1 and 2

Reset (pull-up)

Fault interrupt

C serial data

C serial clock

Digital ground

Digital supply voltage

DocID018572 Rev 7 15/94

Electrical specifications STA350B, STA350BW

Table 2. Absolute maximum ratings

Symbol Parameter Min.

V cc

Power supply voltage (VCCxA, VCCxB)

VDD_DIG Digital supply voltage

VDD_PLL PLL supply voltage

T op

T stg

-0.3

-20

-40

Typ.

Max.

Unit

150 °C

Warning:

Stresses beyond those listed in Table 2

above may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under

“Recommended operating conditions” are not implied.

Exposure to AMR conditions for extended periods may affect device reliability. In the real application, power supplies with nominal values rated within the recommended operating conditions may rise beyond the maximum operating conditions for a short time when no or very low current is sunk (amplifier in mute state). In this case the reliability of the device is guaranteed, provided that the absolute maximum ratings are not exceeded.

16/94

Symbol

Table 3. Thermal data

Parameter Min.

Typ.

Max.

Unit

R th j-case

T th-sdj

T th-w

T th-sdh

R th j-amb

Thermal resistance junction-case (thermal pad)

Thermal shutdown junction temperature

Thermal warning temperature

Thermal shutdown hysteresis

Thermal resistance junction-ambient

(1)

150

130

1.5

°C/W

See

Section 9: PowerSSO-36 slug-down package thermal characteristics (STA350BW) on page 86

for details.

°C

DocID018572 Rev 7

STA350B, STA350BW Electrical specifications

3.4

Table 4. Recommended operating conditions

V cc

Power supply voltage (VCCxA, VCCxB)

VDD_DIG Digital supply voltage

VDD_PLL PLL supply voltage

T amb

2.7 3.3

2.7

-20

3.3

Unit

3.6

+85 °C

Electrical specifications for the digital section

Table 5. Electrical specifications - digital section

Symbol Parameter Conditions Min.

Typ.

I il

I ih

Low-level input current without pull-up/down device

High-level input current without pull-up/down device

Vi = 0 V

Vi = VDD_DIG

= 3.6 V

V il

Low-level input voltage

Max.

0.2 *

VDD_DIG

V ih

High-level input voltage

0.8 *

VDD_DIG

V ol

Low-level output voltage Iol=2 mA

0.4 *

VDD_DIG

V oh

I pu

R pu

High-level output voltage

Pull-up/down current

Equivalent pull-up/down resistance

Ioh=2 mA

0.8 *

VDD_DIG

25 66

125

Unit

µA

µA k Ω

DocID018572 Rev 7 17/94

Electrical specifications STA350B, STA350BW

3.5 Electrical specifications for the power section

The specifications given in this section are valid for the operating conditions: V

CC f = 1 kHz, f sw

= 384 kHz, T amb

= 25° C and R

= 8 Ω , unless otherwise specified.

= 24 V,

Symbol

Table 6. Electrical specifications - power section

Parameter Conditions

Idss

LDT

HDT t r t f

V cc

R dsON

I vcc

Continuous output power, BTL, ternary mode

THD = 1%

THD = 10%

Continuous output power SE, binary mode, R

= 4 Ω

THD = 1%

THD = 10%

Power P-channel/N-channel MOSFET

(total bridge)

Power P-channel/N-channel leakage

Low current dead time (static)

High current dead time (dynamic)

Rise time

Fall time l d

= 1.5 A

VCC = 20 V

Resistive load

(1)

I load

(1)

= 1.5 A

Resistive load

(1)

Resistive load

(1)

Supply voltage operating voltage

Supply current from Vcc in power-down PWRDN = 0

Supply current from Vcc in operation

PCM input signal

= -60 dBfs,

Switching frequency

= 384 kHz,

No LC filters

Ilim

Isc

UVL

OVP t min

I vdd

SNR

THD+N

Supply current FFX processing (reference only)

Internal clock =

49.152 MHz

Overcurrent limit

(2)

Hi-Z output Short-circuit protection

Undervoltage protection

Overvoltage protection

No load Output minimum pulse width

Dynamic range

Signal-to-noise ratio, ternary mode

Signal-to-noise ratio binary mode

A-Weighted

Total harmonic distortion + noise

FFX stereo mode,

Po = 1 W f = 1 kHz

3.0

4.0

180 250 m Ω

10 μ A

8 15 ns

15 30 ns

10 18 ns

26 V

μ A

52 60

3.8

5.0

100

15.5

0.09

4.0

4.3

W mA mA

V ns dB dB dB

18/94 DocID018572 Rev 7

STA350B, STA350BW Electrical specifications

Symbol

Table 6. Electrical specifications - power section (continued)

Parameter Conditions

TALK

PSRR

Crosstalk

Power Supply Rejection Ratio

FFX stereo mode,

<5 kHz

One channel driven at 1 W

Other channel measured

FFX stereo mode,

<5 kHz

VRipple01V RMS

Audio input = dither only

80 dB dB

Peak efficiency, FFX mode

Peak efficiency, binary modes

Po = 2 x 25 W into 8

Ω

Po = 2 x 10W into

Ω

+ 1 x 20W into

8 Ω

Refer to Figure 3: Test circuit .

Limit current if the register (OCRB

Section 8.3.3

) overcurrent warning detect adjustment bypass is enabled. When disabled refer to the Isc.

Figure 3. Test circuit t t

AM045169v1

DocID018572 Rev 7 19/94

Electrical specifications

Figure 4. Power-on sequence

STA350B, STA350BW

Figure 5. Power-off sequence for pop-free turn-off

20/94 DocID018572 Rev 7

STA350B, STA350BW Characterization curves

The following characterization curves have been made using the STA350Bx demonstration board with 2.0 channels (refer to the schematic in

Figure 8

) under the following test conditions:

= 25 V, f = 1 kHz, f

= 384 kHz, Tamb = 25 °C and RL = 6 Ω , unless otherwise specified.

Figure 6. Demonstration board, 2.0 channels

DocID018572 Rev 7

AM045290v1

21/94

Characterization curves

Figure 7. Mono parallel BTL schematic

STA350B, STA350BW

22/94 DocID018572 Rev 7

AM045170v1

STA350B, STA350BW Characterization curves

Figure 8. THD+N vs. output power (V

= 25 V, load = 6 Ω )

0.5

0.2

0.1

0.05

Vcc=25V , Load = 6 Ω,

Freq= 1KHz

0.02

0.01

1m 2m 5m 10m 20m 50m 100m 200m 500m 1

2 5 10 20 50 100

AM045171v1

Figure 9. THD+N vs. output power (V

= 18 V, load = 8 Ω )

0.5

0.2

0.1

0.05

0.02

0.01

1m 2m

Vcc=18V , Load = 8

Freq= 1KHz

Ω,

5m 10m 20m 50m 100m 200m

500m 1 2 5 10 20 50

AM045172v1

DocID018572 Rev 7 23/94

Characterization curves STA350B, STA350BW

Figure 10. Output power vs. V

(load = 6 Ω )

W 30

Load= 6

Ω,

Freq=1KHz

THD = 10%

THD = 1%

+6 +8 +10 +12 +14 +16

Vdc

+18 +20 +22 +24 +26

AM045173v1

Figure 11. Output power vs. V

(load = 8 Ω )

W 25

Load= 8 Ω,

Freq=1KHz

THD = 10%

THD = 1%

+6 +8 +10 +12 +14 +16

Vdc

+18 +20 +22 +24 +26

AM045174v1

24/94 DocID018572 Rev 7

STA350B, STA350BW Characterization curves

Figure 12. Efficiency vs. output power (V

= 25 V, load = 6 Ω )

+0.6

+0.5

+0.4

+0.3

+0.2

+0.1

+0.9

+0.8

+0.7

5 10 15

Vcc= 25V,

Load= 6

Ω,

Freq=1KHz

20 25

30 35 40 45 50 55

AM045175v1

Figure 13. Efficiency vs. output power (V

= 25 V, load = 8 Ω )

+0.6

η %

+0.5

+0.4

+0.3

+0.2

+0.1

+0.9

+0.8

+0.7

5 10 15

Vcc= 25V,

Load= 8

Ω,

Freq=1KHz

25 30 35 40 45

AM045176v1

DocID018572 Rev 7 25/94

Characterization curves

4.1

STA350B, STA350BW

Mono parallel BTL characteristics

Figure 14. THD+N vs. output power (V

= 25 V, load = 3 Ω )

Vcc=25V

Load= 3

Ω,

Freq=1KHz

0.5

0.2

0.1

0.05

110

100

0.02

0.01

1m 2m 5m 10m 20m 50m 100m 200m 500m 1

2 5 10 20

Figure 15. Output power vs. V

(load = 3 Ω )

Load= 3

Ω,

Freq=1KHz

THD=10%

THD=1%

50 100

AM045177v1

+6 +8 +10 +12 +14 +16

Vdc

+18 +20 +22 +24 +26

AM045178v1

26/94 DocID018572 Rev 7

STA350B, STA350BW Characterization curves

Figure 16. Efficiency vs. output power (V

= 26 V, load = 3 Ω )

+0.7

+0.6

+0.5

η % +0.4

+0.3

+0.2

+0.1

+0.9

+0.8

Vcc= 26V

Load= 3

Ω,

Freq=1KHz

10 20 30 40 50

60 70 80 90

Figure 17. Efficiency vs. output power (V

= 18 V, load = 3 Ω )

100 110

AM045179v1

η %

Vcc=18V

Load= 3

Ω,

DocID018572 Rev 7 27/94

Serial audio interface

5 Serial audio interface

STA350B, STA350BW

The STA350Bx audio serial input interface has been designed to interface with standard digital audio components and to accept a number of serial data formats. The STA350Bx always acts as the slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using three inputs: left/right clock

LRCKI, serial clock BICKI, and serial data SDI12.

The SAI bit and the SAIFB bit are used to specify the serial data format. The default serial data format is I

S, MSB-first.

5.0.1 Timings

In the STA350Bx the BICKI and LRCKI pins are configured as inputs and they must be supplied by the external peripheral.

Figure 18. Timing diagram for SAI interface t

BCH t

BCL

80%

BICKI 40% t

BCy

LRCKI

SDI12 t

LRH t

LRSU

5.0.2

5.0.3

Symbol t

BCy t

BCH t

BCL t

LRSU t

LRH t

LRJT

Table 7. Timing parameters for slave mode

Parameter

BICK cycle time

BICK pulse width high

BICK pulse width low

LRCKI setup time to BICKI strobing edge

LRCKI hold time to BICKI strobing edge

LRCKI jitter tolerance

Min.

Typ.

Max.

Unit

ns ns ns ns ns ns

Delay serial clock enable

To tolerate anomalies in some I

S master devices, a PLL clock cycle delay can be added to the BICKI signal before the SAI interface.

Channel input mapping

Each channel received via I

S can be mapped to any internal processing channel via the channel input mapping registers. This allows for flexibility in processing. The default settings of these registers map each I

S input channel to its corresponding processing channel.

28/94 DocID018572 Rev 7

STA350B, STA350BW

6 Processing data paths

Processing data paths

Figure 19

and 20

illustrate the data processing paths inside the STA350Bx.

The whole processing chain is composed of two consecutive sections. In the first one dualchannel processing is implemented, as described below, and then each channel is fed into the post-mixing block by generating either a third channel (typically used in 2.1 output configuration and with crossover filters enabled) or having the channels processed by the dual-band DRC block (2.0 output configuration with crossover filters used to define the cutoff frequency of the two bands).

The first section begins with a 2x oversampling FIR filter allowing for 2*Fs audio processing.

Then a selectable high-pass filter removes the DC level (enabled if HFB=0).

The channel 1 and 2 processing chain can include up to 8 filters, depending on the selected configuration (bits BQL, BQ5, BQ6, BQ7 and XO[3:0]).

By default 4 independent filters per channel are enabled, plus the pre-configured De-

Emphasis, Bass and Treble controls (BQL=0, BQ5=0, BQ6=0, BQ7=0).

If the coefficient sets are linked (BQL=1) it’s then possible to use De-Emphasis, Bass and

Treble filter in a user-defined configuration (provided the relevant BQx bits are set). In other words both channels use the same processing coefficients and can have up to 7 filters each.

Note that if BQL=0 the BQx bits are ignored and the 5 th

, 6 th

and 7 th

filters are configured as, respectively, De-Emphasis, Bass and Treble controls.

Moreover the common 8 th

filter, from the subsequent processing section, can be available on both channels (provided the pre-defined crossover frequencies are not used, XO[3:0]=0, and the dual-band DRC is not used).

In the second section mixing and crossover filters are available. If B

DRC is not enabled

(

Figure 20

), they are fully user-programmable and allow generating a third channel (2.1 outputs). Alternatively, in B

DRC mode, those blocks are used to split the sub-band and define the cutoff frequencies of the two bands. A prescaler and a final post scaler allow full control over the signal dynamic respectively before and after the filtering stages. A mixer function is also available.

x2 x2

FIR

Figure 19. Left and right processing - part 1

If BQ5=1 and BQL=1

Biquad

If BQ6=1 and BQL=1

Biquad

IF BQ7=1 and BQL=1

Biquad

De-Emph.

Bass Treble

If HPB=0 x2 x2

FIR

User Defined Filters

If DSPB=0 and C1EQBP=0

If DEMP=0

If C1TCB=0

BTC: Bass Boost/Cut

TTC: Treble Boost/Cut

If BQ5=1 and BQL=1

Biquad

If BQ6=1 and BQL=1

Biquad

IF BQ7=1 and BQL=1

Biquad

De-Emph.

Bass Treble

If HPB=0

User Defined Filters

If DSPB=0 and C2EQBP=0

If DEMP=0

If C2TCB=0

BTC: Bass Boost/Cut

TTC: Treble Boost/Cut

AM045181v1

DocID018572 Rev 7 29/94

Processing data paths

Figure 20. Processing - part 2

Dual-band DRC enabled

CH3

Volume

DRC2

0x7fffff filter

0x00000

0x000000

Hi-Pass XO

B DRC

Hi-pass filter

0x7fffff

CH1

Volume

CH2

Volume

Vol

Limiter

DRC1

STA350B, STA350BW

0x40000

0x400000

CH3

Volume

DRC2

Crossover Frequency determined by XO Setting

Dual-band DRC disabled

Channel ½

Hi-Pass XO

Hi-pass XO filter

--------------

Hi-pass XO filter

Low-pass XO filter

Crossover Frequency determined by XO Setting

B 2 DRC Disabled

AM045182v1

30/94 DocID018572 Rev 7

STA350B, STA350BW

7 I

C bus specification

C bus specification

The STA350Bx supports the I

C protocol via the input ports SCL and SDA_IN (master to slave) and the output port SDA_OUT (slave to master). This protocol defines any device that sends data to the bus as a transmitter and any device that reads the data as a receiver.

The device that controls the data transfer is known as the master and the other as the slave.

The master always starts the transfer and provides data to the serial clock for synchronization. The STA350Bx is always a slave device in all of its communications. It supports up to 400 kb/s rate (fast-mode bit rate). The STA350Bx I

C is a slave-only interface. The I

C interface works properly only in the case that the master clock generated by the PLL has a frequency 10 times higher compared to the frequency of the applied SCL signal.

7.1.1 Data transition or change

Data changes on the SDA line must only occur when the SCL clock is low. An SDA transition while the clock is high is used to identify a START or STOP condition.

START is identified by a high-to-low transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A START condition must precede any command for data transfer.

STOP is identified by a low-to-high transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A STOP condition terminates communication between the STA350Bx and the bus master.

During data input the STA350Bx samples the SDA signal on the rising edge of clock SCL.

For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low.

To start communication between the master and the STA350Bx, the master must initiate a start condition. Following this, the master sends 8 bits (MSB first) corresponding to the device select address and read or write mode to the SDA line.

The seven most significant bits are the device address identifiers, corresponding to the I

C bus definition. In the STA350Bx the I

C interface has two device addresses depending on the SA port configuration, 0x38 when SA = 0, and 0x3A when SA = 1.

The eighth bit (LSB) identifies the read or write operation RW, this bit is set to 1 in read mode and to 0 for write mode. After a START condition the STA350Bx identifies on the bus

DocID018572 Rev 7 31/94

C bus specification STA350B, STA350BW the device address and if a match is found, it acknowledges the identification on the SDA bus during the 9 th

bit time. The byte following the device identification byte is the internal space address.

Following the START condition the master sends a device select code with the RW bit set to 0. The STA350Bx acknowledges this and then writes the byte of the internal address.

After receiving the internal byte address the STA350Bx again responds with an acknowledgment.

In the byte write mode the master sends one data byte, which is acknowledged by the

STA350Bx. The master then terminates the transfer by generating a STOP condition.

The multi-byte write modes can start from any internal address. The master generating a

STOP condition terminates the transfer.

7.4.1

7.4.2

7.4.3

7.4.4

Current address byte read

Following the START condition the master sends a device select code with the RW bit set to 1. The STA350Bx acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition.

Current address multi-byte read

The multi-byte read modes can start from any internal address. Sequential data bytes are read from sequential addresses within the STA350Bx. The master acknowledges each data byte read and then generates a STOP condition, terminating the transfer.

Random address byte read

Following the START condition the master sends a device select code with the RW bit set to 0. The STA350Bx acknowledges this and then the master writes the internal address byte. After receiving the internal byte address, the STA350Bx again responds with an acknowledgement. The master then initiates another START condition and sends the device select code with the RW bit set to 1. The STA350Bx acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition.

Random address multi-byte read

32/94 DocID018572 Rev 7

STA350B, STA350BW

Figure 21. Write mode sequence

C bus specification

AM045183v1

Figure 22. Read mode sequence

S T A R T R W

AM045184v1

DocID018572 Rev 7 33/94

Register description STA350B, STA350BW

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0x21

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

Addr Name D7 D6

Table 8. Register summary

D5 D4 D3

B2CF1

B2CF2

B2CF3

A1CF1

A1CF2

A1CF3

A2CF1

A2CF2

L1AR

L1ATRT

L2AR

L2ATRT

CFADDR

B1CF1

B1CF2

B1CF3

CONFA

CONFB

AUTO2

AUTO3

FDRB

C2IM

XO3

Reserved

TWAB

C1IM

TWRB

DSCKE

CONFC

CONFD

CONFE

CONFF

MUTE/LOC LOC1

MVOL

C1VOL

C2VOL

C3VOL

AUTO1

OCRB

SME

SVE

EAPD

MV7

C1V7

C2V7

C3V7

ZDE

ZCE

PWDN

LOC0

MV6

C1V6

C2V6

C3V6

CSZ3

DRC

DCCV

ECLE

Reserved

MV5

C1V5

C2V5

C3V5

Reserved Reserved AMGC1

XO2 XO1

C1CFG

C2CFG

C3CFG

TONE

C1OM1

C2OM1

C3OM1

TTC3

C1OM0

C2OM0

C3OM0

TTC2

C1LS1

C2LS1

C3LS1

TTC1

L1A3

L1AT3

L2A3

L2AT3

C1B23

C1B15

C1B7

L1A2

L1AT2

L2A2

L2AT2

Reserved Reserved CFA5

C1B22

C1B14

C1B6

L1A1

L1AT1

L2A1

L2AT1

C1B21

C1B13

C1B5

C2B23

C2B15

C2B7

C3B23

C3B15

C3B7

C4B23

C4B15

C2B22

C2B14

C2B6

C3B22

C3B14

C3B6

C4B22

C4B14

C2B21

C2B13

C2B5

C3B21

C3B13

C3B5

C4B21

C4B13

IR1

SAIFB

CSZ2

BQL

PWMS

LDTE

Reserved

MV4

C1V4

C2V4

C3V4

AMGC0

XO0

IR0

SAI3

CSZ1

PSL

AME

BCLE

C3M

MV3

C1V3

C2V3

C3V3

Reserved

AMAM2

CFA4

C1B20

C1B12

C1B4

C2B20

C2B12

C2B4

C3B20

C1LS0 C1BO C1VBP

C2LS0 C2BO C2VBP

C3LS0

TTC0

C3BO

BTC3

C3VBP

BTC2

L1A0

L1AT0

L2A0

L2AT0

L1R3

L1RT3

L2R3

L2RT3

L1R2

L1RT2

L2R2

L2RT2

C3B12

C3B4

C4B20

C4B12

CFA3

C1B19

C1B11

C1B3

C2B19

C2B11

C2B3

C3B19

C3B11

C3B3

C4B19

C4B11

C3B10

C3B2

C4B18

C4B10

CFA2

C1B18

C1B10

C1B2

C2B18

C2B10

C2B2

C3B18

D2 D1 D0

MCS2

SAI2

CSZ0

DSPB

MCS1

SAI1

OM1

DEMP

MCS0

SAI0

OM0

HPB

NSBW MPC MPCV

IDE OCFG1 OCFG0

C2M

MV2

C1M

MV1

MMUTE

MV0

C1V2

C2V2

C3V2

Reserved

AMAM1

C1V1

C2V1

C1V0

C2V0

C3V1 C3V0

Reserved Reserved

AMAM0 AMAME

CFA1

C1B17

C1B9

C1B1

C2B17

C2B9

C2B1

C3B17

C1EQBP C1TCB

C2EQBP C2TCB

Reserved Reserved

BTC1 BTC0

L1R1

L1RT1

L2R1

L2RT1

L1R0

L1RT0

L2R0

L2RT0

C3B9

C3B1

C4B17

C4B9

C3B8

C3B0

C4B16

C4B8

CFA0

C1B16

C1B8

C1B0

C2B16

C2B8

C2B0

C3B16

34/94 DocID018572 Rev 7

STA350B, STA350BW Register description

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

0x40

0x41

0x42

0x43

0x44

0x45

0x46

0x32

0x33

0x34

0x35

0x36

0x37

0x38

0x39

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x30

0x31

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x29

Addr Name D7

Table 8. Register summary (continued)

D6 D5 D4

A2CF3

B0CF1

B0CF2

B0CF3

C4B7

C5B23

C5B15

C5B7

C4B6

C5B22

C5B14

C5B6

C4B5

C5B21

C5B13

C5B5

C4B4

C5B20

C5B12

C5B4

CFUD

MPCC1

MPCC2

DCC1

DCC2

FDRC1

FDRC2

STATUS

Reserved

MPCC15

MPCC7

DCC15

DCC7

FDRC15

FDRC7

PLLUL

Reserved

MPCC14

MPCC6

DCC14

DCC6

FDRC14

FDRC6

FAULT

MPCC13

MPCC5

DCC13

DCC5

FDRC13

FDRC5

UVFAULT

MPCC12

MPCC4

DCC12

DCC4

FDRC12

FDRC4

OVFAULT

RO1BACT R5BACT Reserved

Reserved

EQCFG

EATH1

ERTH1

EATH2

ERTH2

CONFX

SVCA

SVCB

RMS0A

RMS0B

RMS0C

RMS1A

RMS1B

RMS1C

Reserved

XOB

EATHEN1

R01BEND

Reserved Reserved

EATH1[6] EATH1[5]

ERTHEN1 ERTH1[6] ERTH1[5]

EATHEN2 EATH2[6] EATH2[5]

ERTHEN2 ERTH2[6] ERTH2[5]

MDRC[1] MDRC[0] PS48DB

Reserved Reserved SVUPE

Reserved Reserved SVDWE

R_C0[23] R_C0[22] R_C0[21]

R_C0[15]

R_C0[7]

R_C1[23]

R_C0[14]

R_C0[6]

R_C1[22]

R_C0[13]

R_C0[5]

R_C1[21]

R_C1[15] R_C1[14] R_C1[13]

R_C1[7] R_C1[6] R_C1[5]

EVOLRES VRESEN VRESTG C3VR[1]

R5BEND

R5BBAD

AMGC3

EATH1[4]

ERTH1[4]

EATH2[4]

ERTH2[4]

XAR1

SVUP[4]

SVDW[4]

R_C0[20]

R_C0[12]

R_C0[4]

R_C1[20]

R_C1[12]

R_C1[4]

C3VR[0]

Reserved

D3 D2 D1 D0

EATH1[3]

ERTH1[3]

EATH2[3]

ERTH2[3]

XAR2

SVUP[3]

SVDW[3]

R_C0[19]

R_C0[11]

R_C0[3]

R_C1[19]

R_C1[11]

R_C1[3]

C2VR[1]

C4B3

C5B19

C5B11

C5B3

MPCC11

MPCC3

DCC11

C4B2

C5B18

C5B10

C5B2

MPCC10

MPCC2

DCC10

C4B1

C5B17

C5B9

C5B1

MPCC9

MPCC1

DCC9

DCC3

FDRC11

DCC2

FDRC10

DCC1

FDRC9

FDRC3 FDRC2 FDRC1

OCFAULT OCWARN TFAULT

R4BACT

R4BEND

R4BBAD

AMGC2

R3BACT

R3BEND

R3BBAD

Reserved

R2BACT

DCC0

FDRC8

FDRC0

TWARN

R1BACT

R2BEND R1BEND

R2BBAD R1BBAD

SEL1 SEL0

C4B0

C5B16

C5B8

C5B0

MPCC8

MPCC0

DCC8

EATH1[2] EATH1[1] EATH1[0]

ERTH1[2] ERTH1[1] ERTH1[0]

EATH2[2] EATH2[1] EATH2[0]

ERTH2[2] ERTH2[1] ERTH2[0]

BQ5

SVUP[2]

SVDW[2]

R_C0[18]

R_C0[10]

R_C0[2]

R_C1[18]

R_C1[10]

R_C1[2]

C2VR[0]

BQ6

SVUP[1]

SVDW[1]

R_C0[17]

R_C0[9]

R_C0[1]

R_C1[17]

R_C1[9]

R_C1[1]

C1VR[1]

BQ7

SVUP[0]

SVDW[0]

R_C0[16]

R_C0[8]

R_C0[0]

R_C1[16]

R_C1[8]

R_C1[0]

C1VR[0]

DocID018572 Rev 7 35/94

Register description STA350B, STA350BW

Addr

0x47

0x48

0x51

0x52

0x53

0x54

0x55

0x56

0x49

0x4A

0x4B

0x4C

0x4D

0x4E

0x4F

0x50

Name D7

Table 8. Register summary (continued)

D6 D5 D4 D3 D2 D1 D0

Reserved

NSHAPE

MISC1

MISC2

NSHXEN

RPDNEN

Reserved

NSHB7EN

Reserved

NSHB6EN

CXT[B4B1] CXTB4[1] CXTB4[0] CXTB3[1]

CXT[B7B5] Reserved Reserved CXTB7[1]

NSHHPEN BRIDGOFF

Reserved

NSHB5EN

CXTB3[0]

CXTB7[0]

Reserved

PNDLSL[2]

NSHB4EN NSHB3EN NSHB2EN

NSHB1E

CXTB2[1]

CXTB6[1]

Reserved

PNDLSL[1]

CXTB2[0]

CXTB6[0]

CPWMEN

PNDLSL[0]

CXTB1[1]

CXTB5[1]

Reserved

CXTB1[0]

CXTB5[0]

Reserved

36/94 DocID018572 Rev 7

STA350B, STA350BW

8.1

8.1.1

Register description

Configuration register A (addr 0x00)

FDRB

TWAB

TWRB

IR1

IR0

Master clock select

Bit

R/W

R/W

RST

MCS2

MCS1

MCS0

Table 9. Master clock select

Name Description

MCS0

MCS1

MCS2

Selects the ratio between the input I

S sample frequency and the input clock.

The STA350Bx supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,

176.4 kHz, and 192 kHz. Therefore the internal clock is:

• 32.768 MHz for 32 kHz

•

45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz

• 49.152 MHz for 48 kHz, 96 kHz, and 192 kHz

The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency (f s

The relationship between the input clock and the input sample rate is determined by both the MCSx and the IR (input rate) register bits. The MCSx bits determine the PLL factor generating the internal clock and the IR bit determines the oversampling ratio used internally.

Table 10. Input sampling rates

Input sample rate

fs (kHz)

IR MCS[2:0]

32, 44.1, 48

88.2, 96

176.4, 192

101 100 011 010 001 000

576 * fs 128 * fs 256 * fs 384 * fs 512 * fs 768 * fs

NA 64 * fs 128 * fs 192 * fs 256 * fs 384 * fs

NA 32 * fs 64 * fs 96 * fs 128 * fs 192 * fs

DocID018572 Rev 7 37/94

Register description STA350B, STA350BW

8.1.3

8.1.4

Bit

4:3

R/W

R/W

RST

Table 11. Internal interpolation ratio

Name

IR [1:0]

Description

Selects internal interpolation ratio based on input I

S sample frequency

The STA350Bx has variable interpolation (oversampling) settings such that internal processing and FFX output rates remain consistent. The first processing block interpolates by either 2-times or 1-time (pass-through) or provides a 2-times downsample. The oversampling ratio of this interpolation is determined by the IR bits.

Table 12. IR bit settings as a function of input sample rate

Input sample rate fs (kHz) IR 1 st

stage interpolation ratio

44.1

88.2

176.4

192

2 times oversampling

Pass-through

2 times downsampling

Thermal warning recovery bypass

Bit

R/W

R/W

RST

Table 13. Thermal warning recovery bypass

Name Description

1 TWRB

0: Thermal warning recovery enabled

1: Thermal warning recovery disabled

If the thermal warning adjustment is enabled (TWAB = 0), then the thermal warning recovery determines if the -3 dB output limit is removed when thermal warning is negative.

If TWRB = 0 and TWAB = 0, then when a thermal warning disappears the -3 dB output limit is removed and the gain is added back to the system. If TWRB = 1 and TWAB = 0, then when a thermal warning disappears the -3 dB output limit remains until TWRB is changed to zero or the device is reset.

Thermal warning adjustment bypass

Bit

R/W

R/W

Table 14. Thermal warning adjustment bypass

RST Name Description

1 TWAB

0: Thermal warning adjustment enabled

1: Thermal warning adjustment disabled

38/94 DocID018572 Rev 7

STA350B, STA350BW

8.1.5

Register description

The on-chip STA350Bx power output block provides feedback to the digital controller using inputs to the power control block. Input TWARN is used to indicate a thermal warning condition. When TWARN is asserted (set to 0) for a period of time greater than 400 ms, the power control block forces a -3 dB output limit (determined by TWOCL in the coefficient

RAM) to the modulation limit in an attempt to eliminate the thermal warning condition. Once the thermal warning output limit adjustment is applied, it remains in this state until reset, unless FDRB = 0.

Fault detect recovery bypass

Bit

R/W

R/W

RST

Table 15. Fault detect recovery bypass

Name Description

FDRB

0: fault detect recovery enabled

1: fault detect recovery disabled

The on-chip STA350Bx power output block provides feedback to the digital controller using inputs to the power control block. The FAULT input is used to indicate a fault condition

(either over-current or thermal). When FAULT is asserted (set to 0), the power control block attempts a recovery from the fault by asserting the tri-state output (setting it to 0 which directs the power output block to begin recovery), holds it at 0 for period of time in the range of 0.1 ms to 1 second as defined by the fault-detect recovery constant register (FDRC registers 0x29-0x2A), then toggles it back to 1. This sequence is repeated as long as the fault indication exists. This feature is enabled by default but can be bypassed by setting the

FDRB control bit to 1.

8.2

8.2.1

Configuration register B (addr 0x01)

C2IM

C1IM

DSCKE

SAIFB

SAI3

SAI2

SAI1

SAI0

Serial audio input interface format

Bit

R/W

R/W

RST

Table 16. Serial audio input interface

Name Description

SAI0

SAI1

SAI2

SAI3

Determines the interface format of the input serial digital audio interface.

DocID018572 Rev 7 39/94

Register description STA350B, STA350BW

8.2.3

The STA350Bx audio serial input was designed to interface with standard digital audio components and to accept a number of serial data formats. The STA350Bx always acts as the slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using three inputs: left/right clock LRCKI, serial clock BICKI, and serial data 1 and 2 SDI12.

The SAI bits (D3 to D0) and the SAIFB bit (D4) are used to specify the serial data format.

The default serial data format is I

S, MSB-first. Available formats are shown in the tables that follow.

Serial data first bit

SAIFB

Table 17. Serial data first bit

Format

MSB-first

LSB-first

Table 18. Support serial audio input formats for MSB-first (SAIFB = 0)

BICKI SAI [3:0] SAIFB

32 * fs

48 * fs

64 * fs

1010

1110

0000

0001

0010

0110

1010

1110

0000

0001

0000

0001

0010

0110

Interface format

S 15-bit data

Left/right-justified 16-bit data

S 16 to 23-bit data

Left-justified 16 to 24-bit data

Right-justified 24-bit data

Right-justified 20-bit data

Right-justified 18-bit data

Right-justified 16-bit data

S 16 to 24-bit data

Left-justified 16 to 24-bit data

Right-justified 24-bit data

Right-justified 20-bit data

Right-justified 18-bit data

Right-justified 16-bit data

40/94 DocID018572 Rev 7

STA350B, STA350BW Register description

Table 19. Supported serial audio input formats for LSB-first (SAIFB = 1)

BICKI

32 * fs

SAI [3:0]

1100

1110

0100

1000

1100

SAIFB

Interface format

S 15-bit data

Left/right-justified 16-bit data

S 23-bit data

S 20-bit data

S 18-bit data

LSB first I

S 16-bit data

48 * fs

64 * fs

1100

0001

0101

1001

1101

0010

0110

1010

1110

0110

1010

1110

0000

0100

1000

0001

0101

1001

1101

0010

Left-justified 24-bit data

Left-justified 20-bit data

Left-justified 18-bit data

Left-justified 16-bit data

Right-justified 24-bit data

Right-justified 20-bit data

Right-justified 18-bit data

Right-justified 16-bit data

S 24-bit data

S 20-bit data

S 18-bit data

LSB first I

S 16-bit data

Left-justified 24-bit data

Left-justified 20-bit data

Left-justified 18-bit data

Left-justified 16-bit data

Right-justified 24-bit data

Right-justified 20-bit data

Right-justified 18-bit data

Right-justified 16-bit data

To make the STA350Bx work properly, the serial audio interface LRCKI clock must be synchronous to the PLL output clock. It means that:

• the frequency of PLL clock / frequency of LRCKI = N ±4 cycles,

where N depends on the settings in Table 12 on page 38

• the PLL must be locked.

If these two conditions are not met, and the IDE bit (reg 0x05 bit 2) is set to 1, the STA350Bx will immediately mute the I

S PCM data out (provided to the processing block) and it freezes any active processing task.

DocID018572 Rev 7 41/94

Register description

Note:

8.2.4

STA350B, STA350BW

To avoid any audio side effects (like pop noise), it is strongly recommended to soft-mute any audio streams flowing into the STA350Bx data path before the desynchronize event happens. At the same time any processing related to the I

C configuration should be issued only after the serial audio interface and the internal PLL are synchronous again.

Any mute or volume change causes some delay in the completion of the I

C operation due to the soft-volume feature. The soft-volume phase change must be finished before any clock desynchronization.

Delay serial clock enable

Bit

R/W

R/W

RST

Table 20. Delay serial clock enable

Name Description

DSCKE

0: No serial clock delay

1: Serial clock delay by 1 core clock cycle to tolerate anomalies in some I

S master devices

8.2.5 Channel input mapping

Bit

R/W

R/W

RST

Table 21. Channel input mapping

Name

C1IM

C2IM

Description

0: Processing channel 1 receives Left I

S Input

1: Processing channel 1 receives Right I

S Input

0: Processing channel 2 receives Left I

S Input

1: Processing channel 2 receives Right I

S Input

Each channel received via I

S can be mapped to any internal processing channel via the

Channel Input Mapping registers. This allows for flexibility in processing. The default settings of these registers map each I

S input channel to its corresponding processing channel.

42/94 DocID018572 Rev 7

STA350B, STA350BW

8.3

8.3.1

Register description

Configuration register C (addr 0x02)

OCRB

D6 D5

CSZ3

CSZ2

CSZ1

CSZ0

OM1

FFX power output mode

Bit

R/W

R/W

RST

Table 22. FFX power output mode

Name Description

OM0

OM1

Selects configuration of FFX output

OM0

The FFX power output mode selects how the FFX output timing is configured.

Different power devices use different output modes.

OM[1,0]

Table 23. Output modes

Output stage mode

Drop compensation

Discrete output stage - tapered compensation

Full power mode

Variable drop compensation (CSZx bits)

8.3.2 FFX compensating pulse size register

Bit

R/W

R/W

RST

Table 24. FFX compensating pulse size bits

Name Description

CSZ0

CSZ1

CSZ2

CSZ3

When OM[1,0] = 11, this register determines the size of the FFX compensating pulse from 0 clock ticks to

15 clock ticks

Table 6:

CSZ[3:0]

0000

0001

…

1111

Table 25. Compensating pulse size

Compensating pulse size

0 ns (0 tick) compensating pulse size

20 ns (1 tick) clock period compensating pulse size

…

300 ns (15 tick) clock period compensating pulse size

DocID018572 Rev 7 43/94

Register description

8.3.3

STA350B, STA350BW

Overcurrent warning detect adjustment bypass

Bit

R/W

R/W

RST

Table 26. Overcurrent warning bypass

Name Description

OCRB

0: Overcurrent warning adjustment enabled

1: Overcurrent warning adjustment disabled

The OCWARN input is used to indicate an overcurrent warning condition. When OCWARN is asserted (set to 0), the power control block forces an adjustment to the modulation limit

(default is -3 dB) in an attempt to eliminate the overcurrent warning condition. Once the overcurrent warning volume adjustment is applied, it remains in this state until a reset occurs. The level of adjustment can be changed via the TWOCL (thermal warning/over current limit) setting which is address 0x37 of the user-defined coefficient RAM.

8.4 Configuration register D (addr 0x03)

SME

ZDE

DRC

BQL

PSL

DSPB

DEMP

HPB

Bit

R/W

R/W

RST

Table 27. High-pass filter bypass

Name Description

HPB

Setting of one bypasses internal AC coupling digital high-pass filter

The STA350Bx features an internal digital high-pass filter for the purpose of AC coupling.

The purpose of this filter is to prevent DC signals from passing through an FFX amplifier. DC signals can cause speaker damage. When HPB = 0, this filter is enabled.

8.4.2 De-emphasis

Bit

R/W

R/W

RST

Table 28. De-emphasis

Name

DEMP

Description

0: No de-emphasis

1: Enable de-emphasis on all channels

44/94 DocID018572 Rev 7

STA350B, STA350BW Register description

Bit

R/W

R/W

RST

Table 29. DSP bypass

Name

DSPB

Description

0: Normal operation

1: Bypass of biquad and bass/treble functions

Setting the DSPB bit to 1 bypasses the EQ function of the STA350Bx.

Bit

R/W

R/W

RST

Table 30. Post-scale link

Name

PSL

Description

0: Each channel uses individual post-scale value

1: Each channel uses channel 1 post-scale value

Post-scale functionality can be used for power-supply error correction. For multi-channel applications running off the same power-supply, the post-scale values can be linked to the value of channel 1 for ease of use and to update the values faster.

8.4.6

Bit

R/W

R/W

RST

Table 31. Biquad coefficient link

Name Description

BQL

0: Each channel uses coefficient values

1: Each channel uses channel 1 coefficient values

For ease of use, all channels can use the biquad coefficients loaded into the channel-1 coefficient RAM space by setting the BQL bit to 1. Therefore, any EQ updates have to be performed only once.

Dynamic range compression/anti-clipping bit

Bit

R/W

R/W

Table 32. Dynamic range compression/anti-clipping bit

RST Name Description

0 DRC

0: Limiters act in anti-clipping mode

1: Limiters act in dynamic range compression mode

Both limiters can be used in one of two ways, anti-clipping or dynamic range compression.

When used in anti-clipping mode the limiter threshold values are constant and dependent on the limiter settings. In dynamic range compression mode the limiter threshold values vary with the volume settings allowing a nighttime listening mode that provides a reduction in the dynamic range regardless of the volume level.

DocID018572 Rev 7 45/94

Register description

8.4.7

STA350B, STA350BW

Zero-detect mute enable

Bit

R/W

R/W

RST

Table 33. Zero-detect mute enable

Name Description

ZDE Setting of 1 enables the automatic zero-detect mute

Setting the ZDE bit enables the zero-detect automatic mute. The zero-detect circuit looks at the data for each processing channel at the output of the crossover (bass management) filter. If any channel receives 2048 consecutive zero value samples (regardless of f s

) then that individual channel is muted if this function is enabled.

Bit

R/W

R/W

RST

Table 34. Sub-mix mode enable

Name Description

SME

0: Sub-mix into left/right disabled

1: Sub-mix into left/right enabled

8.5

8.5.1

Configuration register E (addr 0x04)

SVE

ZCE

DCCV

PWMS

AME

NSBW

MPC

Max. power correction variable

Bit

R/W

R/W

RST

Table 35. Max. power correction variable

Name Description

0 MPCV

0: Use standard MPC coefficient

1: Use MPCC bits for MPC coefficient

MPCV

46/94

Bit

R/W

R/W

RST

Table 36. Max. power correction

Name Description

MPC

Setting of 1 enables power bridge correction for THD reduction near maximum power output

Setting the MPC bit turns on special processing that corrects the STA350Bx power device at high power. This mode should lower the THD+N of a full FFX system at maximum power output and slightly below. If enabled, MPC is operational in all output modes except tapered

(OM[1,0] = 01) and binary. When OCFG = 00, MPC does not effect channels 3 and 4, the line-out channels.

DocID018572 Rev 7

STA350B, STA350BW

8.5.3

Register description

Noise-shaper bandwidth selection

Bit

R/W

R/W

RST

Table 37. Noise-shaper bandwidth selection

Name Description

0 NSBW

1: Third order NS

0: Fourth order NS

Bit

R/W RST

R/W 0

Table 38. AM mode enable

Name Description

AME

0: Normal FFX operation

1: AM reduction mode FFX operation

The STA350Bx features an FFX processing mode that minimizes the amount of noise generated in the frequency range of AM radio. This mode is intended to be used when FFX operates in a device with an AM tuner active. The SNR of the FFX processing is reduced to approximately 83 dB in this mode, which is still greater than the SNR of AM radio.

8.5.6

8.5.7

Bit

R/W RST

R/W 0

Table 39. PWM speed mode

Name Description

PWMS

0: Normal speed (384 kHz) all channels

1: Odd speed (341.3 kHz) all channels

Distortion compensation variable enable

Bit

R/W

R/W

Table 40. Distortion compensation variable enable

RST Name Description

0 DCCV

0: Use preset DC coefficient

1: Use DCC coefficient

Zero-crossing volume enable

Bit

R/W

R/W

RST

Table 41. Zero-crossing volume enable

Name Description

ZCE

1: Volume adjustments only occur at digital zero-crossings

0: Volume adjustments occur immediately

The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on digital zero-crossings, no clicks are audible.

DocID018572 Rev 7 47/94

Register description STA350B, STA350BW

8.6

Bit

R/W RST

R/W 1

Table 42. Soft-volume update enable

Name Description

SVE

1: Volume adjustments ramp according to SVR settings

0: Volume adjustments occur immediately

Configuration register F (addr 0x05)

EAPD

PWDN

ECLE

LDTE

BCLE

IDE

OCFG1

OCFG0

Bit

R/W

R/W

RST

Table 43. Output configuration

Name Description

OCFG0

OCFG1

Selects the output configuration

OCFG[1:0]

Table 44. Output configuration engine selection

Output configuration

2-channel (full-bridge) power, 2-channel data-out:

1A/1B

→

1A/1B

2A/2B → 2A/2B

LineOut1 → 3A/3B

LineOut2 → 4A/4B

Line out configuration determined by LOC register

2(half-bridge).1(full-bridge) on-board power:

→

1A Binary 0 °

2A → 1B Binary 90 °

3A/3B

→

2A/2B Binary 45 °

1A/B → 3A/B Binary 0 °

2A/B → 4A/B Binary 90 °

2 Channel (full-bridge) power, 1 channel FFX:

1A/1B

→

1A/1B

2A/2B → 2A/2B

3A/3B

→

3A/3B

EAPDEXT and TWARNEXT Active

1 Channel mono-parallel:

3A → 1A/1B w/ C3BO 45 °

→

2A/2B w/ C3BO 45 °

1A/1B → 3A/3B

2A/2B

→

4A/4B

Config pin

48/94 DocID018572 Rev 7

STA350B, STA350BW

Note:

Register description

To the left of the arrow, the processing channel is shown. When using channel output mapping, any of the three processing channel outputs can be used for any of the three inputs.

Figure 23. OCFG = 00 (default value)

Figure 24. OCFG = 01

AM045185v1

Figure 25. OCFG = 10

AM045186v1

DocID018572 Rev 7

AM045187v1

49/94

Register description

Figure 26. OCFG = 11

STA350B, STA350BW

50/94

AM045188v1

The STA350Bx can be configured to support different output configurations. For each PWM output channel a PWM slot is defined. A PWM slot is always 1 / (8 * fs) second length. The

PWM slot defines the maximum extension for the PWM rising and falling edge, that is, the rising edge as well as the falling edge cannot range outside the PWM slot boundaries.

Figure 27. Output mapping scheme

FFX1A

FFX1 B

FFX2 A

FFX 2B

FFX3 A

FFX3B

FFX4 A

FFX 4B

OUT1A

OUT1B

OUT2A

OUT2B

OUT1A

OUT1B

OUT2A

OUT2B

OUT3A

OUT3B

OUT4A

OUT4B

AM045189v1

For each configuration the PWM signals from the digital driver are mapped in different ways to the power stage.

DocID018572 Rev 7

STA350B, STA350BW Register description

2.0 channels, two full-bridges (OCFG = 00)

• FFX1A -> OUT1A

•

FFX1B -> OUT1B

• FFX2A -> OUT2A

•

FFX2B -> OUT2B

• FFX3A -> OUT3A

•

FFX3B -> OUT3B

• FFX4A -> OUT4A

•

FFX4B -> OUT4B

• FFX1A/1B configured as ternary

•

FFX2A/2B configured as ternary

• FFX3A/3B configured as lineout ternary

•

FFX4A/4B configured as lineout ternary

On channel 3 line out (LOC bits = 00) the same data as channel 1 processing is sent. On channel 4 line out (LOC bits = 00) the same data as channel 2 processing is sent. In this configuration, neither volume control nor EQ has any effect on channels 3 and 4.

In this configuration the PWM slot phase is the following as shown in Figure 28

Figure 28. 2.0 channels (OCFG = 00) PWM slots

DocID018572 Rev 7

AM045190v1

51/94

Register description STA350B, STA350BW

2.1 channels, two half-bridges + one full-bridge (OCFG = 01)

• FFX1A -> OUT1A

•

FFX2A -> OUT1B

• FFX3A -> OUT2A

•

FFX3B -> OUT2B

• FFX1A -> OUT3A

•

FFX1B -> OUT3B

• FFX2A -> OUT4A

•

FFX2B -> OUT4B

• FFX1A/1B configured as binary

•

FFX2A/2B configured as binary

• FFX3A/3B configured as binary

•

FFX4A/4B is not used

In this configuration, channel 3 has full control (volume, EQ, etc…). On OUT3/OUT4 channels the channel 1 and channel 2 PWM are replicated.

In this configuration the PWM slot phase is the following as shown in Figure 29

Figure 29. 2.1 channels (OCFG = 01) PWM slots

AM045191v1

52/94 DocID018572 Rev 7

STA350B, STA350BW Register description

2.1 channels, two full-bridge + one external full-bridge (OCFG = 10)

• FFX1A -> OUT1A

•

FFX1B -> OUT1B

• FFX2A -> OUT2A

•

FFX2B -> OUT2B

• FFX3A -> OUT3A

•

FFX3B -> OUT3B

• EAPD -> OUT4A

•

TWARN -> OUT4B

• FFX1A/1B configured as ternary

•

FFX2A/2B configured as ternary

• FFX3A/3B configured as ternary

•

FFX4A/4B is not used

In this configuration, channel 3 has full control (volume, EQ, etc…). On OUT4 channel the external bridge control signals are muxed.

In this configuration the PWM slot phase is shown in

Figure 30 .

Figure 30. 2.1 channels (OCFG = 10) PWM slots

AM045192v1

DocID018572 Rev 7 53/94

Register description

8.6.2

8.6.3

STA350B, STA350BW

Invalid input detect mute enable

Bit

R/W

R/W

RST

Table 45. Invalid input detect mute enable

Name Description

1 IDE Setting of 1 enables the automatic invalid input detect mute

Setting the IDE bit enables this function, which looks at the input I

S data and automatically mutes if the signals are perceived as invalid.

Binary output mode clock loss detection

Bit

R/W

R/W

Table 46. Binary output mode clock loss detection

RST Name Description

1 BCLE Binary output mode clock loss detection enable

8.6.4

The BCLE bit detects loss of input MCLK in binary mode and outputs 50% duty cycle.

LRCK double trigger protection

Bit

R/W

R/W

RST

Table 47. LRCK double trigger protection

Name Description

1 LDTE LRCLK double trigger protection enable

8.6.5

The LDTE bit actively prevents double triggering of the LRCLK.

Auto EAPD on clock loss

Bit

R/W

R/W

RST

Table 48. Auto EAPD on clock loss

Name Description

ECLE Auto EAPD on clock loss

When active, the ECLE bit issues a power device power-down signal (EAPD) on clock loss detection.

54/94

Bit

R/W

R/W

RST

Table 49. IC power-down

Name

PWDN

Description

0: IC power-down low-power condition

1: IC normal operation

The PWDN register is used to place the IC in a low-power state. When PWDN is written as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted

DocID018572 Rev 7

STA350B, STA350BW Register description

I to power down the power-stage, then the master clock to all internal hardware except the

C block is gated. This places the IC in a very low power consumption state.

8.7

8.7.1

8.7.2

Bit

R/W

R/W

RST

Table 50. External amplifier power-down

Name Description

0 EAPD

0: External power stage power down active

1: Normal operation

The EAPD register directly disables/enables the internal power circuitry.

When EAPD = 0, the internal power section is placed in a low-power state (disabled). This register also controls the FFX4B/EAPD output pin when OCFG = 10.

Volume control registers (addr 0x06 - 0x0A)

Mute/line output configuration register

LOC1

LOC[1:0]

LOC0

Reserved

C3M

C2M

Table 51. Line output configuration

Line output configuration

Line output fixed - no volume, no EQ

Line output variable - CH3 volume effects line output, no EQ

Line output variable with EQ - CH3 volume effects line output

C1M

MMUTE

Line output is active when OCFG = 00 only. In this case LOC determines the line output configuration. The source of the line output is always the channel 1 and 2 inputs.

Master volume register

MV7

MV6

MV5

MV4

MV3

MV2

MV1

MV0

C1V7

C1V6

C1V5

C1V4

C1V3

C1V2

C1V1

C1V0

DocID018572 Rev 7 55/94

Register description STA350B, STA350BW

8.7.5

C2V7

C2V6

C2V5

C2V4

C2V3

C2V2

C2V1

C2V0

Channel 3 / line output volume

C3V7

C3V6

C3V5

C3V4

C3V3

C3V2

C3V1

C3V0

The volume structure of the STA350Bx consists of individual volume registers for each channel and a master volume register that provides an offset to each channel volume setting. The individual channel volumes are adjustable in 0.5 dB steps from +48 dB to -80 dB.

As an example if C3V = 0x00 or +48 dB and MV = 0x18 or -12 dB, then the total gain for channel 3 = +36 dB.

The master mute, when set to 1, mutes all channels at once, whereas the individual channel mute (CxM) mutes only that channel. Both the master mute and the channel mutes provide a “soft mute” with the volume ramping down to mute in 4096 samples from the maximum volume setting at the internal processing rate (approximately 96 kHz).

A “hard (instantaneous) mute” can be obtained by programming a value of 0xFF (255) to any channel volume register or the master volume register. When volume offsets are provided via the master volume register, any channel whose total volume is less than -80 dB is muted.

All changes in volume take place at zero-crossings when ZCE = 1 ( Configuration register E

(addr 0x04)

) on a per channel basis as this creates the smoothest possible volume transitions. When ZCE = 0, volume updates occur immediately.

Table 52. Master volume offset as a function of MV[7:0]

MV[7:0] Volume offset from channel value

00000000 (0x00)

00000001 (0x01)

00000010 (0x02)

…

01001100 (0x4C)

…

11111110 (0xFE)

11111111 (0xFF)

0 dB

-0.5 dB

-1 dB

…

-38 dB

…

-127.5 dB

Hard master mute

56/94 DocID018572 Rev 7

STA350B, STA350BW Register description

Table 53. Channel volume as a function of CxV[7:0]

CxV[7:0] Volume

00000000 (0x00)

00000001 (0x01)

00000010 (0x02)

…

01011111 (0x5F)

01100000 (0x60)

01100001 (0x61)

…

11010111 (0xD7)

11011000 (0xD8)

11011001 (0xD9)

11011010 (0xDA)

…

11101100 (0xEC)

11101101 (0xED)

…

11111111 (0xFF)

+48 dB

+47.5 dB

+47 dB

…

+0.5 dB

0 dB

-0.5 dB

…

-59.5 dB

-60 dB

-61 dB

-62 dB

…

-80 dB

Hard channel mute

…

Hard channel mute

8.8

8.8.1

Audio preset registers (addr 0x0B and 0x0C)

Audio preset register 1 (addr 0x0B)

Reserved

AMGC[1]

AMGC[0]

Reserved

Using AMGC[3:0] bits, attack and release thresholds and rates are automatically configured

to properly fit application specific configurations. AMGC[3:2] is defined in register EQ coefficients and DRC configuration register (addr 0x31) on page 75

The AMGC[1:0] bits behave in two different ways depending on the value of AMGC[3:2].

When this value is 00, then bits AMGC[1:0] are defined in

Table 54

Table 54. Audio preset gain compression/limiters selection for AMGC[3:2] = 00

AMGC[1:0] Mode

User-programmable GC

AC no clipping 2.1

AC limited clipping (10%) 2.1

DRC nighttime listening mode 2.1

DocID018572 Rev 7 57/94

Register description

8.8.2

8.8.3

STA350B, STA350BW

Audio preset register 2 (addr 0x0C)

XO3

XO2

XO1

XO0

AMAM2

AMAM1

AMAM0

AMAME

AM interference frequency switching

Bit

R/W

R/W

Table 55. AM interference frequency switching bits

RST Name Description

0 AMAME

Audio preset AM enable

0: switching frequency determined by PWMS setting

1: switching frequency determined by AMAM settings

AMAM[2:0]

000

Table 56. Audio preset AM switching frequency selection

48 kHz/96 kHz input f s

0.535 MHz - 0.720 MHz

44.1 kHz/88.2 kHz input f s

0.535 MHz - 0.670 MHz

001

010

011

100

101

110

0.721 MHz - 0.900 MHz

0.901 MHz - 1.100 MHz

1.101 MHz - 1.300 MHz

1.301 MHz - 1.480 MHz

1.481 MHz - 1.600 MHz

1.601 MHz - 1.700 MHz

0.671 MHz - 0.800 MHz

0.801 MHz - 1.000 MHz

1.001 MHz - 1.180 MHz

1.181 MHz - 1.340 MHz

1.341 MHz - 1.500 MHz

1.501 MHz - 1.700 MHz

8.8.4 Bass management crossover

Bit

R/W

R/W

RST

Table 57. Bass management crossover

Name Description

XO0

XO1

XO2

XO3

Selects the bass-management cross-over frequency. A 1 st

-order hign-pass filter (channels 1 and 2) or a 2 nd

-order low-pass filter (channel 3) at the selected frequency is performed.

XO[3:0]

0000

0001

0010

0011

Table 58. Bass management crossover frequency

Crossover frequency

User-defined

80 Hz

100 Hz

120 Hz

58/94 DocID018572 Rev 7

STA350B, STA350BW Register description

Table 58. Bass management crossover frequency (continued)

XO[3:0] Crossover frequency

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

140 Hz

160 Hz

180 Hz

200 Hz

220 Hz

240 Hz

260 Hz

280 Hz

300 Hz

320 Hz

340 Hz

360 Hz

8.9 Channel configuration registers (addr 0x0E - 0x10)

C1OM1

C2OM1

C3OM1

C1OM0

C2OM0

C3OM0

C1LS1

C2LS1

C3LS1

C1LS0

C2LS0

C3LS0

C1BO

C2BO

C3BO

C1VPB

C2VPB

C3VPB

C1EQBP

C2EQBP

Reserved

C1TCB

C2TCB

Reserved

Tone control (bass/treble) can be bypassed on a per-channel basis for channels 1 and 2.

CxTCB

Table 59. Tone control bypass

Mode

Perform tone control on channel x - normal operation

Bypass tone control on channel x

EQ control can be bypassed on a per-channel basis for channels 1 and 2. If EQ control is bypassed on a given channel, the prescale and all filters (high-pass, biquads, de-emphasis, bass, treble in any combination) are bypassed for that channel.

DocID018572 Rev 7 59/94

Register description

CxEQBP

Table 60. EQ bypass

Mode

Perform EQ on channel x - normal operation

Bypass EQ on channel x

STA350B, STA350BW

8.9.4

Each channel contains an individual channel volume bypass. If a particular channel has volume bypassed via the CxVBP = 1 register then only the channel volume setting for that particular channel affects the volume setting, the master volume setting does not affect that channel.

Binary output enable registers

Each individual channel output can be set to output a binary PWM stream. In this mode output A of a channel is considered the positive output and output B is the negative inverse.

CxBO

Table 61. Binary output enable registers

Mode

FFX 3-state output - normal operation

Binary output

Limiter selection can be made on a per-channel basis according to the channel limiter select bits.

Table 62. Channel limiter mapping as a function of CxLS bits

CxLS[1:0] Channel limiter mapping

Channel has limiting disabled

Channel is mapped to limiter #1

Channel is mapped to limiter #2

60/94

Output mapping can be performed on a per channel basis according to the CxOM channel output mapping bits. Each input into the output configuration engine can receive data from any of the three processing channel outputs.

Table 63. Channel output mapping as a function of CxOM bits

CxOM[1:0] Channel x output source from

Channel1

Channel 2

Channel 3

DocID018572 Rev 7

STA350B, STA350BW

8.10 Tone control register (addr 0x11)

TTC3

TTC2

TTC1

TTC0

BTC3

Register description

BTC2

BTC1

BTC0

Table 64. Tone control boost/cut as a function of BTC and TTC bits

BTC[3:0]/TTC[3:0] Boost/cut

0000

0001

…

0111

0110

0111

1000

1001

…

1101

1110

1111

-12 dB

…

-4 dB

-2 dB

0 dB

+2 dB

+4 dB

…

+12 dB

8.11 Dynamic control registers (addr 0x12 - 0x15)

8.11.1 Limiter 1 attack/release rate

L1A3

L1A2

L1A1

L1A0

L1R3

L1R2

8.11.2 Limiter 1 attack/release threshold

L1AT3

L1AT2

L1AT1

L1AT0

8.11.3 Limiter 2 attack/release rate

L2A3

L2A2

L2A1

L2A0

L1RT3

L2R3

L1RT2

L2R2

L1R1

L1RT1

L2R1

DocID018572 Rev 7

L1R0

L1RT0

L2R0

61/94

Register description STA350B, STA350BW

8.11.4 Limiter 2 attack/release threshold

L2AT3

L2AT2

L2AT1

L2AT0

L2RT3

L2RT2

L2RT1

L2RT0

The STA350Bx includes two independent limiter blocks. The purpose of the limiters is to automatically reduce the dynamic range of a recording to prevent the outputs from clipping in anti-clipping mode or to actively reduce the dynamic range for a better listening environment such as a night-time listening mode which is often needed for DVDs. The two modes are selected via the DRC bit in

Configuration register E (addr 0x04) on page 46 .

Each channel can be mapped to either limiter or not mapped, meaning that the channel clips when 0 dBfs is exceeded. Each limiter looks at the present value of each channel that is mapped to it, selects the maximum absolute value of all these channels, performs the limiting algorithm on that value, and then if needed adjusts the gain of the mapped channels in unison.

The limiter attack thresholds are determined by the LxAT registers if EATHx[7] bits are set to 0 else the thresholds are determined by EATHx[6:0]. It is recommended in anti-clipping mode to set this to 0 dBfs, which corresponds to the maximum unclipped output power of an

FFX amplifier. Since gain can be added digitally within the STA350Bx, it is possible to exceed 0 dBfs or any other LxAT setting. When this occurs, the limiter, when active, automatically starts reducing the gain. The rate at which the gain is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for that limiter. Gain reduction occurs on a peak-detect algorithm. Setting the EATHx[7] bits to 1 selects the anti-clipping mode.

The limiter release thresholds are determined by the LxRT registers if ERTHx[7] bits are set to 0, else the thresholds are determined by ERTHx[6:0]. Setting the ERTHx[7] bits to 1 automatically selects the anti-clipping mode. The release of the limiter, when the gain is again increased, is dependent on an RMS-detect algorithm. The output of the volume/limiter block is passed through an RMS filter. The output of this filter is compared to the release threshold, determined by the Release Threshold register. When the RMS filter output falls below the release threshold, the gain is again increased at a rate dependent upon the

Release rate register. The gain can never be increased past its set value and, therefore, the release only occurs if the limiter has already reduced the gain. The release threshold value can be used to set what is effectively a minimum dynamic range, this is helpful as overlimiting can reduce the dynamic range to virtually zero and cause program material to sound “lifeless”.

In AC mode, the attack and release thresholds are set relative to full-scale. In DRC mode, the attack threshold is set relative to the maximum volume setting of the channels mapped to that limiter and the release threshold is set relative to the maximum volume setting plus the attack threshold.

62/94 DocID018572 Rev 7

STA350B, STA350BW Register description

Figure 31. Basic limiter and volume flow diagram

GAIN / VOLUME

Table 65. Limiter attack rate as a function of

LxA bits

LxA[3:0]

0111

1000

1001

1010

1011

1100

1101

1110

1111

0000

0001

0010

0011

0100

0101

0110

Attack rate dB/ms

0.2256

0.1504

0.1123

0.0902

0.0752

0.0645

0.0564

0.0501

0.0451

3.1584

2.7072

2.2560

1.8048

1.3536

0.9024

0.4512

Fast

Slow

AM045193v1

Table 66. Limiter release rate as a function of LxR bits

LxR[3:0]

0111

1000

1001

1010

1011

1100

1101

1110

1111

0000

0001

0010

0011

0100

0101

0110

Release rate dB/ms

0.0208

0.0198

0.0172

0.0147

0.0137

0.0134

0.0117

0.0110

0.0104

0.5116

0.1370

0.0744

0.0499

0.0360

0.0299

0.0264

Fast

Slow

DocID018572 Rev 7 63/94

Register description STA350B, STA350BW

Anti-clipping mode

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

LxAT[3:0]

Table 67. Limiter attack threshold as a function of LxAT bits (AC-mode)

AC (dB relative to fs)

-12

-10

-8

0000

0001

0010

-6

-4

0011

0100

-2 0101

0 0110

+2 0111

1000

1001

1010

1011

1100

1101

+9 1110

+10 1111

Table 68. Limiter release threshold as a function of LxRT bits (AC-mode)

LxRT[3:0] AC (dB relative to fs)

∞

-29 dB

-20 dB

-16 dB

-14 dB

-12 dB

-10 dB

-8 dB

-7 dB

-6 dB

-5 dB

-4 dB

-3 dB

-2 dB

-1 dB

-0 dB

64/94 DocID018572 Rev 7

STA350B, STA350BW Register description

Dynamic range compression mode

Table 69. Limiter attack threshold as a function of LxAT bits (DRC -mode)

LxAT[3:0]

0111

1000

1001

1010

1011

1100

1101

1110

1111

0000

0001

0010

0011

0100

0101

0110

DRC (dB relative to Volume)

-17

-16

-15

-14

-13

-12

-10

-7

-4

-31

-29

-27

-25

-23

-21

-19

0111

1000

1001

1010

1011

1100

1101

1110

1111

0000

0001

0010

0011

0100

0101

0110

Table 70. Limiter release threshold as a as a function of LxRT bits (DRC-mode)

LxRT[3:0]

DRC (db relative to Volume +

LxAT)

∞

-38 dB

-36 dB

-33 dB

-31 dB

-30 dB

-28 dB

-26 dB

-24 dB

-22 dB

-20 dB

-18 dB

-15 dB

-12 dB

-9 dB

-6 dB

8.11.5 Limiter 1 extended attack threshold (addr 0x32)

EATHEN1

TBD

EATH1[6]

TBD

EATH1[5]

TBD

EATH1[4]

TBD

EATH1[3]

TBD

EATH1[2]

TBD

The extended attack threshold value is determined as follows: attack threshold = -12 + EATH1 / 4

8.11.6 Limiter 1 extended release threshold (addr 0x33)

ERTHEN1

TBD

ERTH1[6]

TBD

ERTH1[5]

TBD

ERTH1[4]

TBD

ERTH1[3]

TBD

ERTH1[2]

TBD

The extended release threshold value is determined as follows: release threshold = -12 + ERTH1 / 4

EATH1[1]

TBD

EATH1[0]

TBD

ERTH1[1]

TBD

ERTH1[0]

TBD

DocID018572 Rev 7 65/94

Register description STA350B, STA350BW

8.11.7 Limiter 2 extended attack threshold (addr 0x34)

EATHEN2

TBD

EATH2[6]

TBD

EATH2[5]

TBD

EATH2[4]

TBD

EATH2[3]

TBD

EATH2[2]

TBD

The extended attack threshold value is determined as follows: attack threshold = -12 + EATH2 / 4

EATH2[1]

TBD

8.11.8 Limiter 2 extended release threshold (addr 0x35)

Note:

ERTHEN2

TBD

ERTH2[6]

TBD

ERTH2[5]

TBD

ERTH2[4]

TBD

ERTH2[3]

TBD

ERTH2[2]

TBD

The extended release threshold value is determined as follows: release threshold = -12 + ERTH2 / 4

Attack/release threshold step is 0.125 dB in the range -12 dB to 0 dB.

ERTH2[1]

TBD

EATH2[0]

TBD

ERTH2[0]

TBD

8.12 User-defined coefficient control registers (addr 0x16 - 0x26)

D7 D6 D5

CFA5

CFA4

CFA3

8.12.2 Coefficient b1 data register bits 23:16

C1B23

C1B22

C1B21

C1B20

C1B19

8.12.3 Coefficient b1 data register bits 15:8

C1B15

C1B14

C1B13

C1B12

C1B11

8.12.4 Coefficient b1 data register bits 7:0

C1B7

C1B6

C1B5

C1B4

C1B3

CFA2

C1B18

C1B10

C1B2

CFA1

CFA0

C1B17

C1B16

C1B9

C1B1

C1B8

C1B0

66/94 DocID018572 Rev 7

STA350B, STA350BW

8.12.5 Coefficient b2 data register bits 23:16

C2B23

C2B22

C2B21

C2B20

C2B19

8.12.6 Coefficient b2 data register bits 15:8

C2B15

C2B14

C2B13

C2B12

C2B11

8.12.7 Coefficient b2 data register bits 7:0

C2B7

C2B6

C2B5

C2B4

C2B3

8.12.8 Coefficient a1 data register bits 23:16

C1B23

C1B22

C1B21

C1B20

C1B19

8.12.9 Coefficient a1 data register bits 15:8

C3B15

C3B14

C3B13

C3B12

C3B11

8.12.10 Coefficient a1 data register bits 7:0

C3B7

C3B6

C3B5

C3B4

C3B3

8.12.11 Coefficient a2 data register bits 23:16

C4B23

C4B22

C4B21

C4B20

C4B19

C2B18

C2B10

C2B2

C1B18

C3B10

C3B2

C4B18

Register description

C2B17

C2B9

C2B1

C1B17

C3B9

C3B1

C4B17

C2B16

C2B8

C2B0

C1B16

C3B8

C3B0

C4B16

DocID018572 Rev 7 67/94

Register description STA350B, STA350BW

8.12.12 Coefficient a2 data register bits 15:8

C4B15

C4B14

C4B13

C4B12

C4B11

8.12.13 Coefficient a2 data register bits 7:0

C4B7

C4B6

C4B5

C4B4

C4B3

C4B10

C4B2

C4B9

C4B1

C4B8

C4B0

8.12.14 Coefficient b0 data register bits 23:16

C5B23

C5B22

C5B21

C5B20

C5B19

8.12.15 Coefficient b0 data register bits 15:8

C5B15

C5B14

C5B13

C5B12

C5B11

C5B18

C5B17

C5B16

C5B10

C5B9

C5B8

8.12.16 Coefficient b0 data register bits 7:0

C5B7

C5B6

C5B5

C5B4

C5B3

C5B2

C5B1

C5B0

8.12.17 Coefficient write/read control register

D7 D6

Reserved

D5 D4 D3

Coefficients for user-defined EQ, mixing, scaling, and bass management are handled internally in the STA350Bx via RAM. Access to this RAM is available to the user via an I

C register interface. A collection of I

C registers are dedicated to this function. One contains a coefficient base address, five sets of three store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the write/read of the coefficient(s) to/from RAM.

Three different RAM banks are embedded in the STA350Bx. The three banks are managed in paging mode using EQCFG register bits. They can be used to store different EQ settings.

For speaker frequency compensation, a sampling frequency independent EQ must be implemented. Computing three different coefficients set for 32 kHz, 44.1kHz, 48 kHz and downloading them into the three RAM banks, it is possible to select the suitable RAM block depending on the incoming frequency with a simple I

C write operation in register 0x31.

68/94 DocID018572 Rev 7

STA350B, STA350BW

Note:

Register description

For example, in case of different input sources (different sampling rates), the three different sets of coefficients can be downloaded once at startup, and during normal play it is possible to switch among the three RAM blocks allowing faster operation, without any additional download from the microcontroller.

To write the coefficients in a particular RAM bank, this bank must be selected first, writing bit 0 and bit 1 in register 0x31. Then the write procedure below can be used.

Note that as soon as a RAM bank is selected, the EQ settings are automatically switched to the coefficients stored in the active RAM block.

The read write operation on RAM coefficients works only if RLCKI (pin29) is switching and stable (ref.

Table 7

, tLRJT timing) and PLL must be locked (ref bit D7 reg 0x2D).

Reading a coefficient from RAM

Select the RAM block with register 0x31 bit 1, bit 0.

2. Write 6 bits of address to I

C register 0x16.

3. Write 1 to R1 bit in I

C address 0x26.

4. Read top 8 bits of coefficient in I

C address 0x17.

5. Read middle 8 bits of coefficient in I

C address 0x18.

6. Read bottom 8 bits of coefficient in I

C address 0x19.

Reading a set of coefficients from RAM

Select the RAM block with register 0x31 bit1, bit0.

2. Write 6 bits of address to I

C register 0x16.

3. Write 1 to RA bit in I

C address 0x26.

4. Read top 8 bits of coefficient in I

C address 0x17.

5. Read middle 8 bits of coefficient in I

C address 0x18.

6. Read bottom 8 bits of coefficient in I

C address 0x19.

7. Read top 8 bits of coefficient b2 in I

C address 0x1A.

8. Read middle 8 bits of coefficient b2 in I

C address 0x1B.

9. Read bottom 8 bits of coefficient b2 in I

C address 0x1C.

10. Read top 8 bits of coefficient a1 in I

C address 0x1D.

11. Read middle 8 bits of coefficient a1 in I

C address 0x1E.

12. Read bottom 8 bits of coefficient a1 in I

C address 0x1F.

13. Read top 8 bits of coefficient a2 in I

C address 0x20.

14. Read middle 8 bits of coefficient a2 in I

C address 0x21.

15. Read bottom 8 bits of coefficient a2 in I

C address 0x22.

16. Read top 8 bits of coefficient b0 in I

C address 0x23.

17. Read middle 8 bits of coefficient b0 in I

C address 0x24.

18. Read bottom 8 bits of coefficient b0 in I

C address 0x25.

DocID018572 Rev 7 69/94

Register description STA350B, STA350BW

Writing a single coefficient to RAM

Select the RAM block with register 0x31 bit1, bit0.

2. Write 6 bits of address to I

C register 0x16.

3. Write top 8 bits of coefficient in I

C address 0x17.

4. Write middle 8 bits of coefficient in I

C address 0x18.

5. Write bottom 8 bits of coefficient in I

C address 0x19.

6. Write 1 to the W1 bit in I

C address 0x26.

Writing a set of coefficients to RAM

Select the RAM block with register 0x31 bit1, bit0.

2. Write 6 bits of starting address to I

C register 0x16.

3. Write top 8 bits of coefficient b1 in I

C address 0x17.

4. Write middle 8 bits of coefficient b1 in I

C address 0x18.

5. Write bottom 8 bits of coefficient b1 in I

C address 0x19.

6. Write top 8 bits of coefficient b2 in I

C address 0x1A.

7. Write middle 8 bits of coefficient b2 in I

C address 0x1B.

8. Write bottom 8 bits of coefficient b2 in I

C address 0x1C.

9. Write top 8 bits of coefficient a1 in I

C address 0x1D.

10. Write middle 8 bits of coefficient a1 in I

C address 0x1E.

11. Write bottom 8 bits of coefficient a1 in I

C address 0x1F.

12. Write top 8 bits of coefficient a2 in I

C address 0x20.

13. Write middle 8 bits of coefficient a2 in I

C address 0x21.

14. Write bottom 8 bits of coefficient a2 in I

C address 0x22.

15. Write top 8 bits of coefficient b0 in I

C address 0x23.

16. Write middle 8 bits of coefficient b0 in I

C address 0x24.

17. Write bottom 8 bits of coefficient b0 in I

C address 0x25.

18. Write 1 to the WA bit in I

C address 0x26.

The mechanism for writing a set of coefficients to RAM provides a method of updating the five coefficients corresponding to a given biquad (filter) simultaneously to avoid possible unpleasant acoustic side-effects. When using this technique, the 6-bit address specifies the address of the biquad b1 coefficient (for example, 0, 5, 10, 20, 35 decimal), and the

STA350Bx generates the RAM addresses as offsets from this base value to write the complete set of coefficient data.

70/94 DocID018572 Rev 7

STA350B, STA350BW Register description

The STA350Bx can be programmed for four EQ filters (biquads) per each of the two input channels. The biquads use the following equation:

Y[n] = 2 * (b

/ 2) * X[n] + 2 * (b

/ 2) * X[n-1] + b

* X[n-2] - 2 * (a

/ 2) * Y[n-1] - a

* Y[n-2]

= b

* X[n] + b

* X[n-1] + b

* X[n-2] - a

* Y[n-1] - a

* Y[n-2] where Y[n] represents the output and X[n] represents the input. Multipliers are 24-bit signed fractional multipliers, with coefficient values in the range of 0x800000 (-1) to 0x7FFFFF

(0.9999998808).

Coefficients stored in the user-defined coefficient RAM are referenced in the following manner:

CxHy0 = b

/ 2

CxHy1 = b

CxHy2 = -a

/ 2

CxHy3 = -a

CxHy4 = b

/ 2 where x represents the channel and the y the biquad number. For example, C2H41 is the b

2 coefficient in the fourth biquad for channel 2.

Additionally, the STA350Bx can be programmed for a high-pass filter (processing channels 1 and 2) and a low-pass filter (processing channel 3) to be used for bassmanagement crossover when the XO setting is 000 (user-defined). Both of these filters when defined by the user (rather than using the preset crossover filters) are second order filters that use the biquad equation given above. They are loaded into the C12H0-4 and

C3Hy0-4 areas of RAM noted in Table 71

By default, all user-defined filters are pass-through where all coefficients are set to 0, except the b

/2 coefficient which is set to 0x400000 (representing 0.5).

8.12.19 Pre-scale

The STA350Bx provides a multiplication for each input channel for the purpose of scaling the input prior to EQ. This pre-EQ scaling is accomplished by using a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. The scale factor for this multiplication is loaded into RAM using the same I

C registers as the biquad coefficients and the bass-management. All channels can use the channel-1 pre-scale factor by setting the Biquad link bit. By default, all pre-scale factors are set to 0x7FFFFF.

8.12.20 Post-scale

The STA350Bx provides one additional multiplication after the last interpolation stage and the distortion compensation on each channel. This post-scaling is accomplished by using a

24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. The scale factor for this multiplication is loaded into RAM using the same I

C registers as the biquad coefficients and the bass-management. This post-scale factor can be used in conjunction with an ADC equipped microcontroller to perform power-supply error correction.

All channels can use the channel-1 post-scale factor by setting the post-scale link bit. By default, all post-scale factors are set to 0x7FFFFF. When line output is being used, channel-3 post-scale will affect both channels 3 and 4.

DocID018572 Rev 7 71/94

Register description STA350B, STA350BW

The STA350Bx provides a simple mechanism for reacting to overcurrent detection in the power block. When the ocwarn input is asserted, the overcurrent post-scale value is used in place of the normal post-scale value to provide output attenuation on all channels. The default setting provides 3 dB of output attenuation when ocwarn is asserted.

The amount of attenuation to be applied in this situation can be adjusted by modifying the overcurrent post-scale value. As with the normal post-scale, this scaling value is a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. By default, the overcurrent post-scale factor is set to 0x5A9DF7 . Once the overcurrent attenuation is applied, it remains until the device is reset.

Table 71. RAM block for biquads, mixing, scaling and bass management

Index (decimal) Index (hex) Coefficient Default

…

0x2E

0x2F

0x30

0x31

0x32

0x33

0x34

0x35

0x28

0x29

0x2A

0x2B

0x2C

0x2D

…

0x13

0x14

0x15

…

0x27

0x00

0x01

0x02

0x03

0x04

0x05

Channel 1 - biquad 1

Channel 1 - biquad 2

…

Channel 1 - biquad 4

Channel 2 - biquad 1

…

Channel 2 - biquad 4

Channel 1/2 - biquad 5 for XO = 000

Hi-pass 2 nd

Order filter for XO ≠ 000

Channel 3 - biquad for XO = 000

Low-pass 2 nd

-order filter for XO ≠ 000

Channel 1 - pre-scale

Channel 2 - pre-scale

Channel 1 - pre-scale

Channel 2 - pre-scale

C12H0(b1/2)

C12H1(b2)

C12H2(a1/2)

C12H3(a2)

C12H4(b0/2)

C3H0(b1/2)

C3H1(b2)

C3H2(a1/2)

C3H3(a2)

C3H4(b0/2)

C1PreS

C2PreS

C1PstS

C2PstS

C1H10(b1/2)

C1H11(b2)

C1H12(a1/2)

C1H13(a2)

C1H14(b0/2)

C1H20

…

C1H44

C2H10

C2H11

…

C2H44

0x000000

0x400000

0x000000

0x400000

0x7FFFFF

0x000000

0x400000

0x000000

…

0x400000

0x000000

…

0x400000

72/94 DocID018572 Rev 7

STA350B, STA350BW Register description

Table 71. RAM block for biquads, mixing, scaling and bass management (continued)

Index (decimal) Index (hex) Coefficient Default

0x36

0x37

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

Channel 3 - post-scale

TWARN/OC - Limit

Channel 1 - Mix 1

Channel 1 - Mix 2

Channel 2 - Mix 1

Channel 2 - Mix 2

Channel 3 - Mix 1

Channel 3 - Mix 2

UNUSED

C3PstS

TWOCL

C1MX1

C1MX2

C2MX1

C2MX2

C3MX1

C3MX2

0x7FFFFF

0x5A9DF7

0x7FFFFF

0x000000

0x7FFFFF

0x400000

8.13 Variable max. power correction registers (addr 0x27 - 0x28)

MPCC15

MPCC7

MPCC14

MPCC13

MPCC12

MPCC11

MPCC10

MPCC9

MPCC8

MPCC6

MPCC5

MPCC4

MPCC3

MPCC2

MPCC1

The MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is used in place of the default coefficient when MPCV = 1.

MPCC0

8.14 Variable distortion compensation registers (addr 0x29 -

0x2A)

DCC15

DCC7

DCC14

DCC13

DCC12

DCC11

DCC10

DCC9

DCC8

DCC6

DCC5

DCC4

DCC3

DCC2

DCC1

DCC0

The DCC bits determine the 16 MSBs of the distortion compensation coefficient. This coefficient is used in place of the default coefficient when DCCV = 1.

DocID018572 Rev 7 73/94

Register description STA350B, STA350BW

8.15 Fault detect recovery constant registers (addr 0x2B - 0x2C)

FDRC15

FDRC14

FDRC13

FDRC12

FDRC11

FDRC10

FDRC9

FDRC8

FDRC7

FDRC6

FDRC5

FDRC4

FDRC3

FDRC2

FDRC1

FDRC0

The FDRC bits specify the 16-bit fault detect recovery time delay. When FAULT is asserted, the TRISTATE output is immediately asserted low and held low for the time period specified by this constant. A constant value of 0x0001 in this register is approximately 0.083 ms. The default value of 0x000C gives approximately 0.1 ms.

8.16 Device status register (addr 0x2D)

PLLUL

FAULT

UVFAULT

OVFAULT

OCFAULT

OCWARN

TFAULT

TWARN

This read-only register provides fault and thermal-warning status information from the power control block. Logic value 1 for faults or warning means normal state. Logic 0 means a fault or warning detected on power bridge. The PLLUL = 1 means that the PLL is not locked.

Bit

R/W

RST

Table 72. Status register bits

Name Description

PLLUL

FAULT

UVFAULT

OVFAULT

OCFAULT

OCWARN

TFAULT

TWARN

0: PLL locked

1: PLL not locked

0: fault detected on power bridge

1: normal operation

0: VCCxX internally detected

< undervoltage threshold

0: VCCxX internally detected

> overvoltage threshold

0: overcurrent fault detected

0: overcurrent warning

0: thermal fault, junction temperature over limit detection

0: thermal warning, junction temperature is close to the fault condition

74/94 DocID018572 Rev 7

STA350B, STA350BW Register description

8.17 EQ coefficients and DRC configuration register (addr 0x31)

XOB

Reserved

SEL[1:0]

00/11

Reserved

AMGC[3]

AMGC[2]

Reserved

Table 73. EQ RAM select

EQ RAM bank selected

Bank 0 activated

Bank 1 activated

Bank 2 activated

SEL[1]

SEL[0]

Bits AMGC[3:2] change the behavior of the bits AMGC[1:0] as given in Table 74

below.

AMGC[3:2]

10/11

Table 74. Anti-clipping and DRC preset

Anti clipping and DRC preset selected

DRC/Anti-clipping behavior described in

Table 54 on page 57

(default).

DRC/Anti-clipping behavior is described Table 75 on page 75

Reserved, do not use

When AMGC[3:2] = 01 then the bits 1:0 are defined as given here in Table 75

AMGC[1:0]

Table 75. Anti-clipping selection for AMGC[3:2] = 01

Mode

AC0, stereo anticlipping 0 dB limiter

AC1, stereo anticlipping +1.25 dB limiter

AC2, stereo anticlipping +2 dB limiter

Reserved do not use

The AC0, AC1, AC2 settings are designed for the loudspeaker protection function, limiting at the minimum any audio artifacts introduced by typical anti-clipping/DRC algorithms. More detailed information is available in the applications notes “Configurable output power rate using STA335BW” and “STA335BWS vs STA335BW”.

The XOB bit can be used to bypass the crossover filters. Logic 1 means that the function is not active. In this case, the high-pass crossover filter works as a pass-through on the data path (b0 = 1, all the other coefficients at logic 0) while the low-pass filter is configured to have zero signal on channel-3 data processing (all the coefficients are at logic 0).

DocID018572 Rev 7 75/94

Register description STA350B, STA350BW

8.18 Extended configuration register (addr 0x36)

Mdrc[1]

Mdrc[0]

PS48DB

XAR1

XAR2

BQ5

BQ6

The extended configuration register provides access to B

DRC and biquad 5, 6 and 7.

BQ7

The STA350Bx device provides a dual-band DRC (B

DRC) on the left and right channels

data path, as depicted in Figure 32 . Dual-band DRC is activated by setting MDRC[1:0] = 1x.

Figure 32. B

DRC scheme

Pass XO

Filter

Hi-pass

76/94

AM045194v1

The low frequency information (LFE) is extracted from left and right channels, removing the high frequencies using a programmable biquad filter, and then computing the difference with the original signal. Limiter 1 (DRC1) is then used to control left/right high-frequency amplitude of the components, while limiter 2 (DRC2) is used to control the low-frequency components (see

Chapter 8.11

The cutoff frequency of the high-pass filters can be user-defined, XO[3:0] = 0, or selected from the pre-defined values.

DRC1 and DRC2 are then used to independently limit L/R high frequencies and LFE

channels amplitude (see Chapter 8.11

) as well as their volume control. To be noted that, in

this configuration, the dedicated channel 3 volume control can actually act as a bass boost enhancer as well (0.5 dB/step resolution).

The processed LFE channel is then recombined with the L and R channels in order to reconstruct the 2.0 output signal.

Sub-band decomposition

The sub-band decomposition for B

DRC can be configured specifying the cutoff frequency.

The cutoff frequency can be programmed in two ways, using XO bits in register 0x0C, or using the “user programmable” mode (coefficients stored in RAM addresses 0x28 to 0x31).

DocID018572 Rev 7

STA350B, STA350BW Register description

For the user programmable mode, use the formulas below to compute the high-pass filters: b0 = (1 + alpha) / 2 b1 = -(1 + alpha) / 2 a0 = 1 a1 = -alpha b2 = 0 a2 = 0 where alpha = (1-sin( ω

))/cos( ω

), and ω

is the cutoff frequency.

A first-order filter is suggested to guarantee that for every ω

the corresponding low-pass

filter obtained as the difference (as shown in Figure 32

) will have a symmetric (relative to HP filter) frequency response, and the corresponding recombination after the DRC has low ripple. Second-order filters can be used as well, but in this case the filter shape must be carefully chosen to provide good low-pass response and minimum ripple recombination. For second-order filters it is not possible to give a closed formula to get the best coefficients, but empirical adjustment should be done.

DRC settings

The DRC blocks used by B

DRC are the same as those described in

Chapter 8.11

. B

DRC configure automatically the DRC blocks in anticlipping mode. Attack and release thresholds can be selected using registers 0x32, 0x33, 0x34, 0x35, while attack and release rates are configured by registers 0x12 and 0x14.

Band down-mixing

The low-frequency band is down-mixed to the left and right channels at the B

DRC output.

Channel volume can be used to weight the bands recombination to fine-tune the overall frequency response.

Note:

Setting MDRC = 01, it is possible to add a programmable biquad (the XO biquad at RAM addresses 0x28 to 0x2C is used for this purpose) to the Limiter/compressor measure path

(side chain). Using EQDRC the peak detector input can be shaped in frequency using the programmable biquad. For example if a +2 dB bass boost is applied (using a low shelf filter for example), the effect is that the EQDRC output will limit bass frequencies to -2 dB below the selected attack threshold.

Generally speaking, if the biquad boosts frequency f with an amount of X dB, the level of a compressed sine wave at the output will be TH - X, where TH is the selected attack threshold.

EQDRC works only if the biquad frequency response magnitude is ≥ 0 dB for every frequency.

DocID018572 Rev 7 77/94

Register description

Figure 33. EQDRC scheme

STA350B, STA350BW

AM045195v1

8.18.3 Extended post-scale range

PS48DB

Mode

Post-scale value is applied as defined in coefficient RAM

Post-scale value is applied with +48 dB offset with respect to the coefficient RAM value

Post-scale is an attenuation by default. When PS48DB is set to 1, a 48-dB offset is applied to the coefficient RAM value, so post-scale can act as a gain too.

8.18.4 Extended attack rate

The attack rate shown in

Table 65

can be extended to provide up to an 8 dB/ms attack rate on both limiters.

XAR1

Mode

Limiter1 attack rate is configured using

Table 65

Limiter1 attack rate is 8 dB/ms

XAR2

Mode

Limiter2 attack rate is configured using

Table 65

Limiter2 attack rate is 8 dB/ms

78/94 DocID018572 Rev 7

STA350B, STA350BW Register description

Note:

De-emphasis filter as well as bass and treble controls can be configured as user-defined filters when the equalization coefficients link is activated (BQL = 1) and the corresponding

BQx bit is set to 1.

BQ5

Mode

Pre-set de-emphasis filter selected

User-defined biquad 5 coefficients are selected

BQ6

Mode

Pre-set bass filter selected as per Table 64

User-defined biquad 6 coefficients are selected

BQ7

Mode

Pre-set treble filter selected as per

Table 64

User-defined biquad 7 coefficients are selected

When filters from 5th to 7th are configured as user-programmable, the corresponding coefficients are stored respectively in addresses 0x20-0x24 (BQ5), 0x25-0x29 (BQ6), 0x2A-

0x2E (BQ7) as in Table 71

BQx bits are ignored if BQL = 0 or if DEMP = 1 (relevant for BQ5) or CxTCB = 1 (relevant for

BQ6 and BQ7).

8.19 EQ soft-volume configuration registers (addr 0x37 - 0x38)

SVUPE

SVUP[4]

SVUP[3]

SVUP[2]

SVUP[1]

SVUP[0]

SVDWE

SVDW4]

SVDW[3]

SVDW[2]

SVDW[1]

SVDW[0]

The soft-volume update has a fixed rate by default. Using register 0x37 and 0x38 it is possible to override the default behavior allowing different volume change rates.

It is also possible to independently define the fade-in (volume is increased) and fade-out

(volume is decreased) rates according to the desired behavior.

DocID018572 Rev 7 79/94

Register description

Note:

STA350B, STA350BW

SVUPE

Mode

When volume is increased, use the default rate

When volume is increased, use the rates defined by SVUP[4:0]

When SVUPE = 1 the fade-in rate is defined by the SVUP[4:0] bits according to the following formula:

Fade-in rate = 48 / (N + 1) dB/ms where N is the SVUP[4:0] value.

SVDWE

Mode

When volume is decreased, use the default rate

When volume is decreased, use the rates defined by SVDW[4:0]

When SVDWE = 1 the fade-out rate is defined by the SVDW[4:0] bits according to the following formula:

Fade-in rate = 48 / (N + 1) dB/ms where N is the SVDW[4:0] value.

For fade-out rates greater than 6 dB/msec it is suggested to disable the CPWMEN bit

(

Section 8.24.4

) and ZCE bit ( Section 8.5.7

) in order to avoid any audible pop noise.

8.20 DRC RMS filter coefficients (addr 0x39-0x3E)

R_C0[23]

R_C0[15]

R_C0[7]

R_C1[23]

R_C1[15]

R_C0[22]

R_C0[14]

R_C0[6]

R_C1[22]

R_C1[14]

R_C0[21]

R_C0[13]

R_C0[5]

R_C1[21]

R_C1[13]

R_C0[20]

R_C0[12]

R_C0[4]

R_C1[20]

R_C1[12]

R_C0[19]

R_C0[11]

R_C0[3]

R_C1[19]

R_C1[11]

R_C0[18]

R_C0[10]

R_C0[2]

R_C1[18]

R_C1[10]

R_C0[17]

R_C0[9]

R_C0[1]

R_C1[17]

R_C1[9]

R_C0[16]

R_C0[8]

R_C0[0]

R_C1[16]

R_C1[8]

80/94 DocID018572 Rev 7

STA350B, STA350BW Register description

R_C1[7]

R_C1[6]

R_C1[5]

R_C1[4]

R_C1[3]

R_C1[2]

R_C1[1]

R_C1[0]

Signal level detection in DRC algorithm is computed using the following formula: y(t) = c0 * abs(x(t)) + c1 * y(t-1) where x(t) represents the audio signal applied to the limiter, and y(t) the measured level.

8.21 Extra volume resolution configuration registers (address

0x3F)

VRESEN

D6 D5 D4 D3 D2 D1 D0

VRESTG C3VR[1] C3VR[0] C2VR[1] C2VR[0] C1VR[1] C1VR[0]

0 0 0 0 0 0 0

The extra volume resolution allows fine volume tuning by steps of 0.125dB.

The feature is enabled when VRESEN=1 , as depicted in Figure 34

. The overall channel volume in this case will be CxVol+CxVR (in dB). On top of the total volume range from

-80 dB to +48 dB, this extra volume resolution works in a volume range from -80 dB to +42 dB. For volumes greater than +42 dB, this function must not be selected.

Figure 34. Extra resolution volume scheme

If VRESEN = 0 the channel volume is defined only by the CxVol registers.

Fine-tuning steps can be set according to the following table for channels 1, 2, 3:

AM045196v1

DocID018572 Rev 7 81/94

Register description STA350B, STA350BW

CxVR

0 dB

-0.125 dB

-0.25 dB

-0.375 dB

Mode

Two different behaviors can be configured by the VRESTG bit:

•

If VRESTG=’0’ the CxVR contribution is applied immediately after the corresponding

C bits are written.

• If VRESTG=’1’ the CxVR bits are effective on channel volume only after the corresponding CxVol register or master volume register is written (even to the previous values).

VRESEN

VRESTG

Mode

Extra volume resolution disabled

Volume fine-tuning enabled and applied immediately

Volume fine-tuning enabled and applied when master or channel volume is updated

8.22 Quantization error noise correction (address 0x48)

D7 D6 D5 D4 D3 D2 D1 D0

NSHXEN NSHB7EN NSHB6EN NSHB5EN NSHB4EN NSHB3EN NSHB2EN NSHB1EN

0 0 0 0 0 0 0 0

A special feature inside the digital processing block is available. In case of poles positioned at very low frequencies, biquad filters can generate some audible quantization noise or unwanted DC level. In order to avoid this kind of effect, a quantization noise-shaping capability can be used. The filter structure including this special feature, relative to each biquad, is shown in

Figure 35 .

By default, this capability is not activated to maintain backward compatibility with all the previous Sound Terminal products. The new feature can be enabled independently for each biquad using the I

C registers. The D7 bit, when set, is responsible for activating this function on the crossover filter while the other bits address any specific biquads according to the previous table. Channels 1 and 2 share the same settings. Bit D7 is effective also for channel 3 if the relative OCFG is used.

82/94 DocID018572 Rev 7

STA350B, STA350BW Register description

Figure 35. Biquad filter structure with quantization error noise-shaping

0 b

1 a

1 b

2 a

AM045197v1

8.23 Extended coefficient range up to -4...4 (address 0x49, 0x4A)

D7 D6 D5 D4 D3 D2 D1 D0

CXTB4[1] CXTB4[0] CXTB3[1] CXTB3[0] CX_B2[1] CXTB2[0] CXTB1[1] CXTB1[0]

0 0 0 0 0 0 0 0

D7 D6 D5 D4 D3 D2 D1 D0

Reserved Reserved CXTB7[1] CXTB7[0] CXTB6[1] CXTB6[0] CXTB5[1] CXTB5[0]

0 0 0 0 0 0 0 0

Biquads from 1 to 7 have in the STA350Bx the possibility to extend the coefficient range from [-1,1) to [-4..4). This allows the realization of high shelf filters that may require a coefficients dynamic greater in absolute value than 1.

Three ranges are available, [-1;1) [-2;2) [-4;4). By default the extended range is not activated to maintain backward compatibility with all the previous Sound Terminal products.

Each biquad has its independent setting according to the following table:

CEXT_Bx[1]

Table 76. Biquad filter settings

CEXT_Bx[0]

[-1;1)

[-2;2)

[-4;4)

Reserved

DocID018572 Rev 7 83/94

Register description STA350B, STA350BW

In this case the user can decide, for each filter stage, the right coefficients range. Note that for a given biquad the same range will be applied to Left and Right (Channel 1 and Channel

2).

The crossover biquad does not have the availability of this feature, maintaining the [-1;1) range unchanged.

8.24 Miscellaneous registers (address 0x4B, 0x4C)

RPDNEN

NSHHPEN

D5 D4

BRIDGOFF Reserved

0 0

Reserved

D2 D1

CPWMEN Reserved

1 0

Reserved

D4 D3 D2 D1

PNDLSL[2] PNDLSL[1] PNDLSL[0] Reserved

0 0 0 0

Reserved

8.24.1 Rate powerdown enable (RPDNEN) bit (address 0x4B, bit D7)

In the STA350Bx, by default, the power-down pin and I

C power-down act on mute commands to perform the fadeout. This default can be changed so that the fadeout can be started using the master volume. The RPDNEN bit, when set, activates this feature.

8.24.2 Noise-shaping on DC cut filter enable (NSHHPEN) bit (address 0x4B, bit D6)

Following the description in

Section 8.22

, this bit, when set, enables the noise-shaping technique on the DC cutoff filter. Channels 1 and 2 share the same settings.

8.24.3 Bridge immediate off (BRIDGOFF) bit (address 0x4B, bit D5)

A fadeout procedure is started in the STA350Bx once the PWDN function is enabled.

Independently from the fadeout time, after 13 million clock cycles (PLL internal frequency) the bridge is put in powerdown (tri-state mode). There is also the possibility to change this behavior so that the power bridge will be switched off immediately after the PWDN pin is tied to ground, without therefore waiting for the 13 million clock cycles. The BRIDGOFF bit, when set, activates this function. Obviously the immediate power-down will generate a pop noise at the output. therefore this procedure must be used only in case pop noise is not relevant in the application. Note that this feature works only for hardware PWDN assertion and not for a powerdown applied through the I

C interface. Refer to

Section 8.24.5

in order to program a different number of clock cycles.

84/94 DocID018572 Rev 7

STA350B, STA350BW Register description

8.24.4 Channel PWM enable (CPWMEN) bit (address 0x4B, bit D2)

This bit, when set, activates a mute output in case the volume will reach a value lower than

-76 dBFS.

8.24.5 Power-down delay selector (PNDLSL[2:0]) bits (address 0x4C, bit D4,

D3, D2)

As per Section 8.24.3

, the assertion of PWDN activates a counter that, by default, after 13 million clock cycles puts the power bridge in tri-state mode, independently from the fadeout time. Using these registers it is possible to program this counter according to the following table:

PNDLSL[2]

PNDLSL[1]

PNDLSL[2]

Fade out time

Default time (13 M clock cycles)

Default time divided by 2

Default time divided by 4

Default time divided by 8

Default time divided by 16

Default time divided by 32

Default time divided by 64

Default time divided by 128

DocID018572 Rev 7 85/94

PowerSSO-36 slug-down package thermal characteristics (STA350BW)

9

STA350B, STA350BW

PowerSSO-36 slug-down package thermal characteristics (STA350BW)

Using a four-layer PCB the thermal resistance junction-to-ambient with 2 copper ground areas of 6 x 4 cm

and with 24 via holes (see Figure 36

) is 17 °C/W in natural air convection.

The dissipated power within the device depends primarily on the supply voltage, load impedance and output modulation level.

Thus, the maximum estimated dissipated power for the STA350BW is:

2 x 40 W @ 8 Ω , 25.5 V Pd max ~ 8 W

2 x 17 W + 1 x 35 W @ 4 Ω , 8 Ω , 25 V Pd max < 7 W

Figure 36. Double-layer PCB with 2 copper ground areas and 24 via holes

86/94

AM045200v1

Figure 37

shows the power derating curve for the PowerSSO-36 slug-down package on

PCBs with copper areas of 5 x 4 cm

and 6 x 4 cm

Figure 37. PowerSSO-36 power derating curve

Pd (W)

0 20 40 60 80

Tamb ( °C)

100 120 140 160

AM045201v1

DocID018572 Rev 7

STA350B, STA350BW Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com.

ECOPACK is an ST trademark.

DocID018572 Rev 7 87/94

Package information STA350B, STA350BW

Figure 38. PowerSSO-36 EPD package outline h x 45°

88/94

Symbol

H h k e e3

E b c

A2 a1

Min.

10.10

2.15

0.00

0.18

0.23

10.10

7.40

Table 77. PowerSSO-36 EPD mechanical data

Dimensions in mm Dimensions in inches

Typ.

0.5

8.5

2.3

Max.

0.10

10.50

0.40

8 degrees

2.47

2.40

0.10

0.36

0.32

10.50

7.60

Min.

0.398

0.085

0.00

0.007

0.009

0.398

0.291

Typ.

0.020

0.335

0.091

Max.

0.004

0.413

0.016

8 degrees

0.097

0.094

0.004

0.014

0.013

0.413

0.299

DocID018572 Rev 7

STA350B, STA350BW

Symbol

Package information

Min.

0.60

4.10

6.50

Table 77. PowerSSO-36 EPD mechanical data

Dimensions in mm Dimensions in inches

Typ.

4.30

1.20

0.80

2.90

3.65

1.00

Max.

1.00

10 degrees

4.70

7.10

Min.

0.024

0.161

0.256

Typ.

0.169

0.047

0.031

0.114

0.144

0.039

Max.

0.039

10 degrees

0.185

0.280

DocID018572 Rev 7 89/94

Package information STA350B, STA350BW

Figure 39. PowerSSO36 (slug-up) package outline

90/94

7618147_F

Symbol e3

H h k

E e c

A2 a1 b

Table 78. PowerSSO36 exposed pad up mechanical data

Dimensions in mm Dimensions in inch

Min.

10.1

0 deg

2.15

0.18

0.23

10.10

7.4

Typ.

8.5

2.3

0.5

Max.

0.1

10.5

0.4

8 deg

2.45

2.35

0.1

0.36

0.32

10.50

7.6

Min.

0 deg

0.085

0.00

0.007

0.009

0.398

0.291

Typ.

0.335

0.091

0.020

Max.

0.004

0.413

0.016

8 deg

0.096

0.092

0.004

0.014

0.013

0.413

0.299

DocID018572 Rev 7

STA350B, STA350BW Package information

Symbol

Table 78. PowerSSO36 exposed pad up mechanical data (continued)

Dimensions in mm Dimensions in inch

Min.

Typ.

Max.

Min.

Typ.

Max.

0.55

4.3

1.2

0.8

2.9

3.65

1.0

0.85

10 deg

0.022

0.169

0.047

0.031

0.114

0.039

0.033

10 deg

DocID018572 Rev 7 91/94

Ordering information STA350B, STA350BW

Order code

STA350BTR

STA350BWTR

Table 79. Order code

Temperature range °C Package

-20 to 85

PowerSSO36 (slug-up)

PowerSSO-36 (slug-down)

Packing

Tape and reel

92/94 DocID018572 Rev 7

STA350B, STA350BW Revision history

Date

11-Mar-2011

20-Apr-2011

13-Apr-2012

20-Sep-2013

18-Jul-2017

11-Apr-2018

07-Jun-2019

Revision

Table 80. Document revision history

Changes

Initial release.

Updated Figure 4: Demonstration board, 2.0 channels

Added Figure 5: Mono parallel BTL schematic

Updated min. and typ. values for Isc in Table 6: Electrical specifications - power section

Added Section 5 on page 25

Modified Note:: The read write operation on RAM coefficients works only if RLCKI (pin29) is switching and stable (ref. Table 7, tLRJT timing) and PLL must be locked (ref bit D7 reg 0x2D).

Updated Company information appearing on last page of document

Added STA350B device, related package information and

Section 11: Ordering information. Minor changes throughout the document.

Added Section 3.6: Power-on/off sequence.

Minor text changes throughout the document.

Updated cover image and

Figure 2

DocID018572 Rev 7 93/94

STA350B, STA350BW

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on

ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks . All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

94/94 DocID018572 Rev 7

பதிவிறக்கு

ஒரு நட்பு நினைவூட்டல். நீங்கள் ஆவணத்தை இங்கே பார்க்கலாம். ஆனால் மிக முக்கியமாக, எங்கள் AI ஏற்கனவே அதைப் படித்துவிட்டது. இது சிக்கலான விஷயங்களை எளிய சொற்களில் விளக்கலாம், உங்கள் கேள்விகளுக்கு எந்த மொழியிலும் பதிலளிக்கலாம், மேலும் மிக நீளமான அல்லது சிக்கலான ஆவணங்களை விரைவாக செல்லவும் உதவும்.

இல்லை, இன்னும் நானே பார்க்க விரும்புகிறேன்

வணக்கம்! STMicroelectronics STA350BW Datasheet உடன் உங்களுக்கு உதவ சிறப்பாகப் பயிற்றுவிக்கப்பட்ட AI சாட்போட் நான். நான் ஆவணத்தை முழுமையாக மதிப்பாய்வு செய்துள்ளேன், மேலும் உங்களுக்குத் தேவையான சரியான தகவலைக் கண்டறிய அல்லது உள்ளடக்கத்தை தெளிவான மற்றும் எளிமையான சொற்களில் விளக்க உதவ முடியும். குறிப்பிட்ட அம்சங்கள், சரிசெய்தல் படிகள் அல்லது பொதுவான பயன்பாடு குறித்த வழிகாட்டுதலை நீங்கள் தேடுகிறீர்களானால், உங்கள் கேள்விகளைக் கேட்க தயங்கவும். உங்கள் கவலைகள் அல்லது தேவைகள் பற்றி நீங்கள் எவ்வளவு அதிகமாக விவரங்களை வழங்குகிறீர்களோ, அவ்வளவு துல்லியமாகவும் эффективноவும் நான் உங்களுக்கு உதவ முடியும்!