STA381BW Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
Figure 51. VQFN48 (7 x 7 x 0.9 mm) package outline
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Package information STA381BW
Table 183. VQFN48 (7 x 7 x 0.9 mm) package dimensions mm
Reference
Min.
Typ.
0.90
b1 e (pad pitch)
L1 aaa bbb ddd eee fff ccc
D2
E
E2 b
A
A1
D
0.80
0
6.90
5.65
6.90
5.65
0.25
0.20
0.05
0.15
0.10
0.05
0.08
0.10
0.10
7.00
5.70
7.00
5.70
0.30
0.25
0.50
Max
1.00
0.05
7.10
5.75
7.10
5.75
0.35
0.30
0.15
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STA381BW Revision history
Date
08-Jun-2011
28-Jun-2011
Revision
1
2
02-Sep-2011 3
Table 184. Document revision history
Changes
Initial release
Removed TQFP64 package option
Added note to
Figure 46 ,
47
,
48 , 49
,
50 , and
Section 8.2: Headphone and 2 Vrms line out , referencing AN3959
20-Dec-2011
17-Jan-2012
20-Jun-2012
03-Aug-2012
17-May-2013
4
5
6
7
8
Updated names of pin 32 and 33 in
Figure 1: Block diagram ,
Figure 2: Pin connections
VQFN48 (top view) and
Table 2: Pin list
Document promoted from preliminary to full datasheet
Added “VDD3V3CHP” to
Table 3 and
Table 5
Updated footnotes in
Table 7
Updated register names to “SVUP” and “SVDN” for addresses 37 and 38 in
Table 100
Updated text in Table 46
and
Table 121: PWM speed mode
Updated 2.0 channels, two full-bridges (OCFG = 00) on page 121
Updated 2.1 channels, two full-bridges + one external full-bridge (OCFG = 10) on page 123
Updated high-pass filter in Table 152
Textual changes to formulas in
Section 7.17: EQ soft volume configuration registers (addr
0x37 - 0x38)
Added overvoltage protection threshold (V
OV
section
) to Table 7: Electrical specifications - power
Removed ECLE bit and sections concerning “Auto EAPD on clock loss” from datasheet
Updated
Table 14: Default register map table: NEW MAP on page 45
Updated
Table 100: I
2
C registers summary on page 106
Updated
Section 6.32: Enhanced zero-detect mute and input level measurement
(address 0x61-0x65, 0x3F, 0x40, 0x6F) on page 97
Added
Table 90: Manual threshold register 0x3F, 0x40 and 0x6F on page 98
Added
Section 6.36: Charge pump synchronization (address 0x70) on page 101
Added
Table 98: Charge pump sync configuration bits on page 101
Updated
Section 7.24: Enhanced zero-detect mute and input level measurement
(address 0x50-0x54, 0x2E, 0x2F and 0x5E) on page 158
Added
Table 174: Manual threshold register 0x2E, 0x2F and 0x5E on page 160
Added
Section 7.28: Charge pump synchronization (address 0x5F) on page 163
Added
Table 180: Charge pump sync configuration bits on page 163
Added
Section 3.6: Power-on/off sequence
(added
Figure 4 and Figure 5 )
Updated description of CHPRD bit in
Table 98 and
Table 180
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STA381BW
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