STA382BWS Register description: New Map
Note:
To avoid any audio side effects (like pop noise), it is strongly recommended to soft mute any audio streams flowing into the STA382BWS data path before the desynchronization event happens. At the same time any processing related to the I
2
C configuration should be issued only after the serial audio interface and the internal PLL are synchronous again.
Any mute or volume change causes some delay in the completion of the I
2
C operation due to the soft volume feature. The soft volume phase change must be finished before any clock desynchronization.
6.14.3 Delay serial clock enable
Table 35.
Delay serial clock enable
Bit R/W RST Name
5 R/W 0 DSCKE
Description
0: No serial clock delay
1: Serial clock delay by 1 core clock cycle to tolerate anomalies in some I
2
S master devices
6.14.4 Channel input mapping
Table 36.
Channel input mapping
Bit R/W RST Name
6
7
R/W
R/W
0
1
C1IM
C2IM
Description
0: Processing channel 1 receives left I
2
S input
1: Processing channel 1 receives right I
2
S input
0: Processing channel 2 receives left I
2
S input
1: Processing channel 2 receives right I
2
S input
Each channel received via I
2
S can be mapped to any internal processing channel via the channel input mapping registers. This allows for flexibility in processing. The default settings of these registers map each I
2
S input channel to its corresponding processing channel.
6.15 Configuration register C (addr 0x13)
D7
Reserved
1
D6
Reserved
0
D5
CSZ3
0
D4
CSZ2
1
D3
CSZ1
0
D2
CSZ0
1
D1
Reserved
1
D0
Reserved
1
Table 37.
FFX compensating pulse size bits
Bit R/W RST Name
2
3
4
5
R/W
R/W
R/W
R/W
1
1
1
0
CSZ0
CSZ1
CSZ2
CSZ3
Description
When OM[1,0] = 11, this register determines the size of the FFX compensating pulse from 0 clock ticks to 15 clock periods.
Doc ID 022784 Rev 1 63/172
