STMicroelectronics VND5012AK-E Datasheet
Oglas
Oglas
VND5012AK-E
Double channel high side driver with analog current sense for automotive applications
Features
Max supply voltage
Operating voltage range
V
CC
V
CC
Max on-state resistance (per ch.) R
ON
Current limitation (typ) I
LIMH
Off-state supply current (typ.) I
S
1.
Typical value with all loads connected.
41 V
4.5 to 36 V
12 m Ω
60 A
2 µA
(1)
■
■
■
General features
– Inrush current active management by power limitation
– Very low standby current
– 3.0 V CMOS compatible input
– Optimized electromagnetic emission
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/EC european directive
Diagnostic functions
– Proportional load current sense
– High current sense precision for wide range currents
– Current sense disable
– Thermal shutdown indication
– Very low current sense leakage
Protections
– Undervoltage shutdown
– Overvoltage clamp
– Output stuck to Vcc detection
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss of V
CC
– Thermal shutdown
Table 1. Device summary
Package
PowerSSO-24
Application
■ All types of resistive, inductive and capacitive loads
Description
The VND5012AK-E a monolithic device made using STMicroelectronics VIPower M0-5 technology. It is intended for driving resistive or inductive loads with one side connected to ground. Active V
CC
pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). This device integrates an analog current sense which delivers a current proportional to the load current
(according to a known ratio) when CS_DIS is driven low or left open. When CS_DIS is driven high, the CURRENT SENSE pin is in a high impedance condition. Output current limitation protects the device in overload condition. In case of long overload duration, the device limits the dissipated power to safe level up to thermal shutdown intervention. Thermal shutdown with automatic restart allows the device to recover normal operation as soon as fault condition disappears.
Tube
VND5012AK-E
PowerSSO-24
– Reverse battery protection (see
)
– Electrostatic discharge protection
Order codes
Tape and reel
VND5012AKTR-E
September 2013 Doc ID 12285 Rev 8 1/31 www.st.com
1
2/31
Contents
Contents
VND5012AK-E
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
GND Protection network against reverse battery . . . . . . . . . . . . . . . . . . . 21
Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 21
Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 22
Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 23
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
®
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PowerSSO-24 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . 27
PowerSSO-24 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Doc ID 12285 Rev 8
VND5012AK-E
List of tables
List of tables
CC
<16V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Doc ID 12285 Rev 8 3/31
4/31
List of figures
List of figures
VND5012AK-E
/I
SENSE
vs I
OUT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
vs T case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Rthj-amb vs PCB copper area in open box free air condition (one channel on) . . . . . . . . . 24
PowerSSO-24 thermal impedance junction ambient single pulse (one channel on) . . . . . 25
Doc ID 12285 Rev 8
VND5012AK-E
1
Block diagram and pin description
Block diagram and pin description
Figure 1.
Block diagram
V
CC
GND
INPUT1
INPUT2
V
CC
CLAMP
UNDERVOLTAGE
LOGIC
PwCLAMP 1
DRIVER 1
Pwr
LIM
1
I
LIM
1
V
DSLIM
1
OVERTEMP. 1
I
OUT1
K 1
Pwr
LIM
2
CS_DIS
PwCLAMP 2
DRIVER 2
I
OUT2
I
LIM
2
V
DSLIM
2
OVERTEMP. 2
K 2
OUTPUT1
CURRENT
SENSE1
OUTPUT2
CURRENT
SENSE2
Table 2.
Name
Pin function
Function
V
CC
OUTPUT
1,2
Battery connection.
Power output.
GND
INPUT
1,2
Ground connection. Must be reverse battery protected by an external diode/resistor network.
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state.
CURRENT
SENSE
1,2
CS_DIS
Analog current sense pin, delivers a current proportional to the load current.
Active high CMOS compatible pin, to disable the current sense pin.
Doc ID 12285 Rev 8 5/31
Block diagram and pin description
Figure 2.
Configuration diagram (top view)
V
CC
GND
N.C.
INPUT2
N.C.
INPUT1
N.C.
CURRENT SENSE1
N.C.
CURRENT SENSE2
CS_DIS
V
CC
1
4
5
2
3
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
TAB = V
CC
VND5012AK-E
Table 3.
Suggested connections for unused and not connected pins
Connection / pin Current Sense N.C.
Output Input
Floating
To ground
Not allowed
Through 1 K Ω resistor
X
X
X
Not allowed
CS_DIS
X
Through 10 K Ω resistor
X
Through 10 K Ω resistor
6/31 Doc ID 12285 Rev 8
VND5012AK-E Electrical specifications
Figure 3.
Current and voltage conventions
V
CSD
I
CSD
I
IN1
V
IN1
I
IN2
V
IN2
V
CC
CS_DIS
OUTPUT1
CURRENT
SENSE1
INPUT1
INPUT2
OUTPUT2
GND
CURRENT
SENSE2
I
S
V
F
(*)
I
OUT1
I
SENSE1
V
SENSE1
I
OUT2
I
SENSE2
V
SENSE2
V
OUT2
V
OUT1
I
GND
V
CC
Note: V
Fn
= V
OUTn
- V
CC
during reverse battery condition.
Stressing the device above the rating listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to the conditions in table below for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality document.
Table 4.
Symbol
Absolute maximum ratings
Parameter
V
CC
-V
CC
-I
GND
I
OUT
DC supply voltage
Reverse DC supply voltage
DC reverse ground pin current
DC output current
-I
OUT
I
IN
I
CSD
Reverse DC output current
DC Input current
DC current sense disable input current
-I
CSENSE
DC reverse CS pin current
V
CSENSE
Current sense maximum voltage
Value
41
0.3
200
Internally limited
-30
-1 to 10
-1 to 10
200
V
CC
-41
+V
CC
Unit
V
V mA
A
A mA mA mA
V
V
Doc ID 12285 Rev 8 7/31
Electrical specifications
Table 4.
Symbol
E
MAX
V
ESD
V
ESD
Absolute maximum ratings (continued)
Parameter
Maximum switching energy
(L=1.25 mH; R
L
=0 Ω ; V bat
=13.5 V; T jstart
=150 °C;
I
OUT
= I limL
(Typ.))
Electrostatic discharge
(Human body model: R= 1.5 K Ω; C= 100 pF)
– INPUT
– CURRENT SENSE
– CS_DIS
– OUTPUT
– V
CC
Charge device model (CDM-AEC-Q100-011)
Junction operating temperature T j
T stg
Storage temperature
Value
508
VND5012AK-E
Unit mJ
4000
2000
4000
5000
5000
750
-40 to 150
-55 to 150
°C
°C
V
V
V
V
V
V
8/31
Table 5.
Symbol
Thermal data
Parameter
R thj-case
Thermal resistance junction-case (max) (With one channel on)
R thj-amb
Thermal resistance junction-ambient (max)
Doc ID 12285 Rev 8
Max value
0.4
Unit
°C/W
°C/W
VND5012AK-E Electrical specifications
8V<V
CC
<36V; -40°C<T j
<150°C, unless otherwise specified.
Table 6.
Symbol
Power section
Parameter Test conditions
V
CC
Operating supply voltage
V
USD
Undervoltage shutdown
V
USDhyst
Undervoltage shutdown hysteresis
R
ON
V clamp
I
S
I
L(off)
On-state resistance
(2)
Clamp voltage
Supply current
Off-state output current
(2)
I
OUT
=5A; T j
=25°C
I
OUT
=5A; T j
=150°C
I
OUT
=5A; V
CC
=5V; T j
=25°C
I
S
=20mA
Off-state; V
CC
=13V; T j
=25°C;
V
IN
=V
OUT
=V
SENSE
=V
CSD
=0V
On-state; V
CC
=13V; V
IN
=5V;
I
OUT
=0A
V
IN
=V
OUT
=0V; V
CC
=13V; T j
=25°C
V
IN
=V
OUT
=0V; V
CC
=13V;
T j
=125°C
41
0
0
Min.
Typ.
Max.
Unit
4.5
13 36
3.5
4.5
V
V
0.5
46
2
(1)
3
0.01
12
24
16
52
5
(1)
6
3
5
µA mA
µA
V m
Ω m Ω m Ω
V
V
F
Output V voltage
(2)
CC
diode
1.
PowerMOS leakage included.
2.
For each channel.
-I
OUT
= 8A; T j
=150°C 0.7
V
Table 7.
Symbol
Switching (V
CC
=13V; T j
=25°C)
Parameter Test conditions Min.
Typ.
Max.
Unit t t d(on) d(off)
Turn-on delay time
Turn-off delay time dV
OUT
/dt
(on)
Turn-on voltage slope
R
L
= 2.6
Ω
R
L
= 2.6 Ω
20
35
µs
µs
R
L
= 2.6 Ω V / µs dV
OUT
/dt
(off)
Turn-off voltage slope
W
W
ON
OFF
R
L
= 2.6 Ω V / µs
Switching energy losses during t won
R
L
= 2.6
Ω
Switching energy losses during t woff
R
L
= 2.6 Ω
1.1
0.7
mJ mJ
Doc ID 12285 Rev 8 9/31
Electrical specifications VND5012AK-E
Table 8.
Symbol
Logic inputs
Parameter Test conditions
V
IL
I
IL
V
IH
I
IH
V
I(hyst)
Input low level voltage
Low level input current
Input high level voltage
High level input current
Input hysteresis voltage
V
V
IN
IN
=0.9 V
=2.1 V
V
ICL
Input clamp voltage
I
IN
=1 mA
I
IN
=-1 mA
V
CSDL
I
CSDL
V
CSDH
CS_DIS low level voltage
Low level CS_DIS current V
CS_DIS high level voltage
CSD
=0.9 V
I
CSDH
High level CS_DIS current V
CSD
=2.1 V
V
CSD(hyst)
CS_DIS hysteresis voltage
V
CSCL
CS_DIS clamp voltage
I
CSD
=1 mA
I
CSD
=-1 mA
Min.
1
2.1
0.25
5.5
1
2.1
0.25
5.5
Typ.
-0.7
-0.7
Max.
0.9
10
7
0.9
10
7
Unit
µA
V
µA
V
V
V
V
µA
V
µA
V
V
V
V
Table 9.
Symbol
Protections and diagnostics
(1)
Parameter Test conditions Min.
Typ.
Max.
Unit
I limH
DC short circuit current
V
CC
=13 V
5 V<V
CC
<36 V
42 60 84
84
T
I
T limL
T
T
TSD
R
RS
HYST
Short circuit current during thermal cycling
Shutdown temperature
Reset temperature
Thermal reset of
STATUS
Thermal hysteresis
(T
TSD
-T
R
)
Turn-off output voltage clamp
V
CC
=13 V T
R
<T j
<T
TSD
150
T
RS
135
24
175
+ 1 T
RS
7
+ 5
200
V
DEMAG
V
ON
Output voltage drop limitation
I
OUT
=2 A; V
IN
=0;
L=6 mH
I
OUT
= 0.4 A;
T j
= -40 °C...+150 °C
)
V
CC
-41 V
CC
-46 V
25
CC
-52
1.
To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles.
A
A
A
°C
°C
°C
°C
V mV
10/31 Doc ID 12285 Rev 8
VND5012AK-E Electrical specifications
Table 10.
Current sense (8V<V
CC
<16V)
Symbol Parameter Test conditions Min.
Typ.
Max.
Unit dK dK
I
1
3
SENSE0
I
K
K
K
K
0
1
/K
2
3
/K
1
(1) dK
2
/K
2
(1)
3
(1)
OL
I
I
I
I
OUT
OUT
Current sense ratio drift
OUT
Current sense ratio drift
OUT
Current sense ratio drift
/I
/I
/I
/I
SENSE
SENSE
SENSE
SENSE
Analog sense leakage current
I
OUT
= 0.25 A; V
SENSE
=0.5 V;
V
CSD
=0 V;
T j
= -40 °C...150 °C
I
OUT
= 5 A; V
SENSE
=0.5 V; V
CSD
=0 V;
T j
= -40 °C...150 °C
I
OUT
=5 A; V
SENSE
=0.5 V; V
CSD
=0 V;
T j
= 25 °C...150 °C
I
OUT
= 5 A; V
SENSE
= 0.5 V; V
CSD
=0 V;
T
J
= -40 °C to 150 °C
I
OUT
= 10 A; V
SENSE
=4 V; V
CSD
=0 V;
T j
= -40 °C...150 °C
I
OUT
= 10 A; V
SENSE
=4 V; V
CSD
=0 V;
T j
= 25 °C...150 °C
I
OUT
= 10 A; V
SENSE
= 4 V; V
CSD
=0 V;
T
J
= -40 °C to 150 °C
I
OUT
= 25 A; V
SENSE
=4 V; V
CSD
=0 V;
T j
= -40 °C...150 °C
I
OUT
= 25 A; V
SENSE
=4 V; V
CSD
=0 V;
T j
= 25 °C...150 °C
I
OUT
= 25 A; V
SENSE
= 4 V; V
CSD
=0 V;
T
J
= -40 °C to 150 °C
I
OUT
=0 A; V
SENSE
=0 V;
V
CSD
=5 V; V
IN
=0 V; T j
=-40 °C...150 °C
V
CSD
=0 V; V
IN
=5 V; T j
=-40 °C...150 °C
I
OUT
=2 A; V
SENSE
=0 V;
V
CSD
=5 V; V
IN
=5 V; T j
=-40 °C...150 °C
Open-load on-state current detection threshold
V
IN
= 5 V, I
SENSE
= 5 µA
V
SENSE
Max analog sense output voltage
I
OUT
=15 A; V
CSD
=0 V
V
SENSEH
Analog sense output voltage in over temperature condition
I
SENSEH
Analog sense output current in over temperature condition
V
V
CC
CC
= 13 V; R
= 13 V; V
SENSE
SENSE
= 3.9 K
= 5 V
Ω t
DSENSE1H
Delay response time from falling edge of CS_DIS pin
V
SENSE
<4 V, 1.5 A<Iout<25 A
I
SENSE
= 90 % of I
SENSE max
2780 5580 8390
3590 5100 6630
4110
-8
5100 6090
+8
4400 5090 5930
4600 5090 5590
-5 +5
4820 5060 5420
4860 5060 5250
-4
0
0
0
10
5
9
8
50
+4
1
2
1
45
100
%
%
%
µA
µA
µA mA
V
V mA
µs
Doc ID 12285 Rev 8 11/31
Electrical specifications
Table 10.
Current sense (8V<V
CC
<16V) (continued)
Symbol Parameter Test conditions t t
DSENSE1L
Delay response time from rising edge of CS_DIS pin
V
SENSE
<4V, 1.5A<Iout<25A
I
SENSE
= 10% of I
SENSE max
DSENSE2H
Delay response time from rising edge of INPUT pin
V
SENSE
<4 V, 1.5 A<Iout<25 A
I
SENSE
= 90 % of I
SENSE max
t
Δ t
DSENSE2H
Delay response time between rising edge of output current and rising edge of current sense
V
SENSE
<4 V,
I
SENSE
= 90 % of I
SENSEMAX,
I
OUT
= 90 % of I
OUTMAX
I
OUTMAX
= 5 A (see
)
DSENSE2L
Delay response time from falling edge of INPUT pin
V
SENSE
<4 V, 1.5 A<Iout<25 A
I
SENSE
=10 % of I
SENSE max
1.
Parameter guaranteed by design, it is not tested.
Figure 4.
Current sense delay characteristics
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT t
DSENSE2H t
DSENSE1L
VND5012AK-E
Min.
Typ.
Max.
Unit
5 20 µs
270 400 µs
100 250 µs t
DSENSE1H t
DSENSE2L
300 µs
12/31 Doc ID 12285 Rev 8
VND5012AK-E Electrical specifications
Figure 5.
Delay response time between rising edge of output current and rising edge of current sense (CS enabled)
V
IN
Δ t
DSENSE2H t
I
OUT
90% I
OUTMAX
I
OUTMAX t
I
SENSE I
SENSEMAX
90% I
SENSEMAX t
Doc ID 12285 Rev 8 13/31
Electrical specifications
Figure 6.
I
OUT
/I
SENSE
vs I
OUT
7000
6500
6000 max Tj = -40°C to 150°C
5500 max Tj= 25°C to 150°C
5000 min Tj= 25°C to 150°C
4500
4000 typical value min Tj= -40°C to 150°C
3500
3000
5 10 15 20
Note:
Figure 7.
Maximum current sense ratio drift vs load current dk/k(%)
15
10
5
0
-5
-10
-15
5 10 15
I
OUT
(A)
Parameter guaranteed by design; it is not tested.
20 25
25
VND5012AK-E
14/31 Doc ID 12285 Rev 8
VND5012AK-E Electrical specifications
Table 11.
Truth table
Conditions
Normal operation
Over temperature
Undervoltage
Short circuit to GND
(R sc
≤ 10 m Ω )
Short circuit to V
CC
Input
L
H
L
H
H
L
H
L
H
L
H
Output
L
H
L
L
L
L
L
L
L
H
H
Sense (V
CSD
=0V)
(1)
Nominal
V
0
0
SENSEH
0
0
0
0 if T j
< T
TSD
V
SENSEH
if T j
> T
TSD
0
< Nominal
Negative output voltage clamp
L L 0
1.
If the V
CSD
is high, the SENSE output is at a high impedance, its potential depends on leakage currents and external circuit.
Figure 8.
Switching characteristics
V
OUT t
Won
80% dV
OUT
/dt
(on) t r
10% t
Woff
90% t f dV
OUT
/dt
(off) t
INPUT t d(on) t d(off) t
Doc ID 12285 Rev 8 15/31
Electrical specifications
Figure 9.
Output voltage drop limitation
V cc
-V out
T j
=150 o
C
T j
=25 o
C
T j
=-40 o
C
VND5012AK-E
V on
I out
V on
/R on(T)
Table 12.
Electrical transient requirements (part 1/3)
ISO 7637-2:
2004(E) test pulse
III
Test levels
(1)
IV
Number of pulses or test times
Burst cycle/pulse repetition time
Min.
Max.
1
2a
3a
-75V
+37V
-100V
-100V
+50V
-150V
5000 pulses
5000 pulses
1h
0.5 s
0.2 s
90 ms
5 s
5 s
100 ms
3b +75V +100V 1h 90 ms 100 ms
4
5b
(2)
-6V
+65V
-7V
+87V
1 pulse
1 pulse
Delays and impedance
2 ms, 10 Ω
50 µs, 2 Ω
0.1 µs, 50 Ω
0.1 µs, 50 Ω
100 ms, 0.01
Ω
400 ms, 2 Ω
Table 13.
Electrical transient requirements (part 2/3)
ISO 7637-2:
2004(E) test pulse
III
Test level results
(1)
IV
1
2
C
C
3a C C
3b C
C 4
5
(2)
C C
1.
The above test levels must be considered referred to V
CC
= 13.5 V except for pulse 5 b.
2.
Valid in case of external load dump clamp: 40 V maximum referred to ground.
C
C
C
C
16/31 Doc ID 12285 Rev 8
VND5012AK-E Electrical specifications
Table 14.
Electrical transient requirements (part 3/3)
Class Contents
C
E
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
Figure 10.
Waveforms
NORMAL OPERATION
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
UNDERVOLTAGE
V
USDhyst
V
CC
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
V
USD
INPUT
CS_DIS
LOAD VOLTAGE
LOAD CURRENT
SENSE CURRENT
<Nominal
SHORT TO V
CC
<Nominal
OVERLOAD OPERATION
T j
T
R
T
TSD
T
RS
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT current limitation power limitation thermal cycling
SHORTED LOAD
I
LIMH
I
LIML
V
SENSEH
NORMAL LOAD
Doc ID 12285 Rev 8 17/31
Electrical specifications
Figure 11.
Off-state output current
VND5012AK-E
Figure 12.
High level input current
Figure 13.
Input clamp voltage Figure 14.
Input high level
Figure 15.
Input low level Figure 16.
Input hysteresis voltage
18/31 Doc ID 12285 Rev 8
VND5012AK-E
Figure 17.
On-state resistance vs T case
Electrical specifications
Figure 18.
On-state resistance vs V
CC
Figure 19.
Undervoltage shutdown Figure 20.
I
LIMH
vs T case
Figure 21.
Turn-on voltage slope Figure 22.
Turn-off voltage slope
Doc ID 12285 Rev 8 19/31
Electrical specifications
Figure 23.
CS_DIS high level voltage Figure 24.
CS_DIS clamp voltage
VND5012AK-E
Figure 25.
CS_DIS low level voltage
20/31 Doc ID 12285 Rev 8
VND5012AK-E Application information
Figure 26.
Application schematic
+5V
μ C
V
CC
R prot CS_DIS
C ext
R prot
R prot
R
SENSE
INPUT
CURRENT SENSE
GND
V
GND
R
GND
D
GND
OUTPUT
D ld
Note:
3.1
3.1.1
Channel 2 has the same internal circuit as channel 1.
GND Protection network against reverse battery
Solution 1: resistor in the ground line (R
GND
only)
This can be used with any type of load.
The following is an indication on how to dimension the R
GND resistor.
1.
R
GND
≤
600 mV / (I
S(on)max
).
2. R
GND
≥ (− V
CC
) / (-I
GND
) where -I
GND
is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet.
Power Dissipation in R
GND
(when V
CC
<0: during reverse battery situations) is:
P
D
= (-V
CC
)
2
/R
GND
This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where I
S(on)max
becomes the sum of the maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the
R
GND will produce a shift (I
S(on)max
* R
GND
) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same R
GND
.
Doc ID 12285 Rev 8 21/31
22/31
Application information
3.1.2
VND5012AK-E
If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize Solution 2 (see below).
Solution 2: diode (D
GND
) in the ground line
A resistor (R
GND
=1 k
Ω) should be inserted in parallel to D
GND
if the device drives an inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift (
≈
600mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network.
3.2 Load dump protection
D ld
is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
V
CC
max DC rating. The same applies if the device is subject to transients on the V
CC
line that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
3.3 MCU I/Os protection
If a ground protection network is used and negative transient are present on the V
CC
line, the control pins will be pulled negative. ST suggests to insert a resistor (R prot
) in line to prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between the leakage current of µC and the current required by the HSD I/Os (input levels compatibility) with the latch-up limit of µC
I/Os.
-V
CCpeak
/I latchup
≤
R prot
≤
(V
OHµC
-V
IH
-V
GND
) / I
IHmax
Calculation example:
For V
CCpeak
= - 100 V and I latchup
≥
20 mA; V
OHµC
≥
4.5 V
5 k
Ω ≤
R prot
≤
180 k
Ω
.
Recommended values: R prot
=10 k
Ω
, C
EXT
=10 nF.
Doc ID 12285 Rev 8
VND5012AK-E
3.4
Application information
Maximum demagnetization energy (V
CC
= 13.5V)
Figure 27.
Maximum turn-off current versus inductance (for each channel)
100
B
C
A
10
1
0,1 1 L (mH) 10
V
IN
, I
L
A: T jstart
= 150°C single pulse
B: T jstart
= 100°C repetitive pulse
C: T jstart
= 125°C repetitive pulse
Demagnetization Demagnetization
100
Demagnetization
Note: t
Values are generated with R
L
=0
Ω.
In case of repetitive pulses, T jstart
(at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B.
Doc ID 12285 Rev 8 23/31
Package and PCB thermal data
4 Package and PCB thermal data
4.1 PowerSSO-24 thermal data
Figure 28.
PowerSSO-24 PC board
VND5012AK-E
Note: Layout condition of R th
and Z th
measurements (PCB: Double layer, Thermal Vias, FR4 area= 77 mm x 86 mm,PCB thickness=1.6 mm, Cu thickness=70 µm (front and back side),
Copper areas: from minimum pad layout to 8 cm
2
).
Figure 29.
R thj-amb
vs PCB copper area in open box free air condition (one channel on)
RTHj_amb(°C/W)
55
50
45
40
35
30
0 2 4 6
PCB Cu heatsink area (cm^2)
8 10
24/31 Doc ID 12285 Rev 8
VND5012AK-E Package and PCB thermal data
Figure 30.
PowerSSO-24 thermal impedance junction ambient single pulse (one channel on)
ZTH ( ° C/ W)
100 foot print
2 cm
2
8 cm
2
10
1
0,1
0,0001 0,001 0,01 0,1
Time ( s)
1 10 100 1000
Equation 1: pulse calculation formula
Z
TH
δ = R
TH where δ = t
P
/T
⋅ δ
+ Z
THtp
( 1 –
δ )
Figure 31.
Thermal fitting model of a single channel HSD in PowerSSO-24
(a) a.
The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
Doc ID 12285 Rev 8 25/31
Package and PCB thermal data
Table 15.
Thermal parameter
Area/island (cm
2
)
R1 (°C/W)
R2 (°C/W)
R3 (°C/W)
R4 (°C/W)
R5 (°C/W)
R6 (°C/W)
R7 (°C/W)
R8 (°C/W)
C1 (W.s/°C)
C2 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
C7 (W.s/°C)
C8 (W.s/°C)
Footprint
0.3
0.0025
0.0024
0.025
0.75
1
2.2
0.0025
0.0024
0.1
0.3
6
7.7
9
28
0.1
2
4
5
VND5012AK-E
8
9
17
8
10
9
17
26/31 Doc ID 12285 Rev 8
VND5012AK-E
5
Package and packing information
Package and packing information
5.1 ECOPACK
®
packages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK® is an ST trademark.
5.2 PowerSSO-24 package mechanical data
Figure 32.
PowerSSO-24 package dimensions
Table 16.
PowerSSO-24 mechanical data
Symbol
A
A2 a1 b
Min.
2.15
2.15
0
0.33
Millimeters
Typ.
Doc ID 12285 Rev 8
Max.
2.47
2.40
0.1
0.51
27/31
28/31
Package and packing information
Table 16.
PowerSSO-24 mechanical data (continued)
Millimeters
Symbol
Min.
Typ.
e e3
G
G1 c
D
E
L
N
X
Y
H h
0.23
10.10
7.4
10.1
0.55
4.1
6.5
0.8
8.8
5.3 PowerSSO-24 packing information
Figure 33.
PowerSSO-24 tube shipment (no suffix)
C
B
Base Q.ty
Bulk Q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
All dimensions are in mm.
A
49
1225
532
3.5
13.8
0.6
VND5012AK-E
Max.
0.32
10.50
7.6
0.1
0.06
10.5
0.4
0.85
10deg
4.7
7.1
Doc ID 12285 Rev 8
VND5012AK-E Package and packing information
Figure 34.
PowerSSO-24 tape and reel shipment (suffix “TR”)
Reel dimensions
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
1000
1000
330
1.5
13
20.2
24.4
100
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width W
Tape Hole Spacing P0 (± 0.1)
Component Spacing
Hole Diameter
P
24
4
12
D (± 0.05) 1.55
Hole Diameter
Hole Position
D1 (min) 1.5
F (± 0.1) 11.5
Compartment Depth K (max) 2.85
Hole Spacing P1 (± 0.1) 2
All dimensions are in mm.
End
Top cover tape
No components
500mm min
Components No components
Empty components pockets saled with cover tape.
500mm min
User direction of feed
Start
Doc ID 12285 Rev 8 29/31
30/31
Revision history VND5012AK-E
Table 17.
Document revision history
Date Revision
10-Apr-2006
02-Jul-2007
12-Feb-2008
18-Jul-2008
01-Aug-2008
26-May-2009
02-Dec-2009
23-Sep-2013
1
2
3
4
5
6
7
8
Changes
Initial release.
Document reformatted and restructured.
Added lists of tables and figures.
information.
Table 4: Absolute maximum ratings
: updated EMAX entries.
: added dk1/k1, dk2/k2, dk3/k3, tDSENSE2H.
.
Added Figure 7: Maximum current sense ratio drift vs load current
.
Table 12: Electrical transient requirements (part 1/3) : updated Test
level values III and IV for test pulse 5b and notes.
Added Section 3.4: Maximum demagnetization energy (VCC = 13.5V) .
Updated Table 10: Current sense (8V<V
:
– changed dk3/k3 values from ± 3 to ± 4%
– changed tDSENSE2H max value from 250 µs to 300 µs
– added IOL parameter
Updated Figure 7: Maximum current sense ratio drift vs load current
with new dk3/k3 value.
Updated Table 4: Absolute maximum ratings
: corrected typing error in
V
ESD parameter.
Updated Table 16: PowerSSO-24 mechanical data : changed a1 max.
value from 0.075 mm to 0.1 mm.
.
,
,
,
.
.
Updated Disclaimer.
Doc ID 12285 Rev 8
VND5012AK-E
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
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PURCHASER’S SOLE RISK, EVEN IF ST HAS BEEN INFORMED IN WRITING OF SUCH USAGE, UNLESS A PRODUCT IS
EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR “AUTOMOTIVE, AUTOMOTIVE SAFETY OR MEDICAL” INDUSTRY
DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS. PRODUCTS FORMALLY ESCC, QML OR JAN QUALIFIED ARE
DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST.
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Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
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Doc ID 12285 Rev 8 31/31
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