STMicroelectronics RVND5E006A Datasheet

RVND5E006A

Double channel high-side driver with analog current sense

Features

*$3*36

Order code

RVND5E006ASPTR

3RZHU62

Max transient supply voltage V

CC

Operating voltage range V

CC

Typ on-state resistance (per ch.) R

ON

Current limitation (typ) I

LIMH

Off-state supply current I

S

1. Typical value with all loads connected.

5 m Ω

100 A

2 μ A (1)

 General

– Very low standby current

– 3.0

V CMOS compatible inputs

– Optimized electromagnetic emissions

– Very low electromagnetic susceptibility

– Compliant with European directive

2002/95/EC

– Very low current sense leakage

 Diagnostic functions

– Proportional load current sense

– High current sense precision for wide currents range

– Current sense disable

– Off-state openload detection

– Output short to V

CC

detection

– Overload and short to ground (power limitation) indication

– Thermal shutdown indication

Datasheet

-

production data

 Protection

– Undervoltage shutdown

– Overvoltage clamp

– Load current limitation

– Self limiting of fast thermal transients

– Protection against loss of ground and loss of V

CC

– Overtemperature shutdown with auto restart (thermal shutdown)

– Inrush current active management by power limitation

– Reverse battery protected with self switch of the PowerMOS

– Electrostatic discharge protection

 Aerospace and Defense features

– Dedicated traceability and part marking

– Production parts approval documents available

– Adapted Extended life time and obsolescence management

– Extended Product Change Notification process

– Designed and manufactured to meet sub ppm quality goals

– Advanced mold and frame designs for

Superior resilience to harsh environment

(acceleration, EMI, thermal, humidity)

– Single Fabrication, Assembly and Test site

– Dual internal production source capability

Applications

All types of resistive, inductive and capacitive loads in Aerospace and Defense applications.

Table 1. Device summary

Package

PowerSO-16

Packing

Tape and reel

September 2014

This is information on a product in full production.

DocID026961 Rev 1

1/37

www.st.com

1

2

3

Contents

Contents

4

5

6

7

RVND5E006A

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.1

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.2

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.3

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.4

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.5

Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.1

Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.2

MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.3

Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.3.1

Short to VCC and off-state open-load detection . . . . . . . . . . . . . . . . . . 27

4.4

Maximum demagnetization energy (VCC = V) . . . . . . . . . . . . . . . . . 28

Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.1

PowerSO-16 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.1

ECOPACK

®

packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.2

PowerSO-16 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.3

Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2/37

DocID026961 Rev 1

RVND5E006A

List of tables

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 7

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 5.

Table 6.

Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 7.

Table 8.

Table 9.

Switching (V

CC

V; =

Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 10.

Current sense (8

Table 11.

Open-load detection (8

CC

V

CC

Table 12.

Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 13.

Electrical transient requirements (part 1/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 14.

Electrical transient requirements (part 2/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 15.

Electrical transient requirements (part 3/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 16.

Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 17.

PowerSO-16 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 18.

Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

DocID026961 Rev 1

3/37

3

List of figures

List of figures

RVND5E006A

Figure 1.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2.

Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3.

Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4.

Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 5.

Open-load off-state delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 6.

Switching characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 7.

Delay response time between rising edge of output current and rising edge of current sense (CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 8.

Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 9.

I

OUT

/I

SENSE

vs I

OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 10.

Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 11.

Normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 12.

Overload or short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 13.

Intermittent overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 14.

Off-state open-load with external circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 15.

Short to V

CC

Figure 16.

T

j

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

evolution in overload or short to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 17.

Off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 18.

High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 19.

Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 20.

Input high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 21.

Input low level voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 22.

Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 23.

On-state resistance vs T

case

Figure 24.

On-state resistance vs V

CC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 25.

Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 26.

I

LIMH

vs T case

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 27.

Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 28.

Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 29.

CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 30.

Low level CS_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 31.

High level CS_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 32.

Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 33.

Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 34.

Maximum turn-off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 35.

PowerSO-16 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 36.

Rthj-amb vs PCB copper area in open box free air condition (one channel ON) . . . . . . . . 29

Figure 37.

PowerSO-16 thermal impedance junction ambient single pulse (one channel ON) . . . . . . 30

Figure 38.

Thermal fitting model of a double channel HSD in PowerSO-16 . . . . . . . . . . . . . . . . . . . . 30

Figure 39.

PowerSO-16 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 40.

PowerSO-16 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 41.

PowerSO-16 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 42.

PowerSO-16 suggested pad layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4/37

DocID026961 Rev 1

RVND5E006A

1 Description

Description

The RVND5E006A is a double channel high-side driver manufactured using ST proprietary

VIPower™ M0-5 technology and housed in PowerSO-16 package. The device is designed to drive 12 V grounded loads, and to provide protection and diagnostics. They also implement a 3 V and 5 V CMOS compatible interface for the use with any microcontroller.

The device integrates advanced protective functions such as load current limitation, inrush and overload active management by power limitation, overtemperature shut-off with auto restart and overvoltage active clamp. A dedicated analog current sense pin is associated with every output channel providing enhanced diagnostic functions including fast detection of overload and short-circuit to ground through power limitation indication, overtemperature indication, short-circuit to V

CC

diagnosis and on-state and off-state open-load detection. The current sensing and diagnostic feedback of the whole device can be disabled by pulling the

CS_DIS pin high to share the external sense resistor with similar devices.

DocID026961 Rev 1

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36

Block diagram and pin description

2 Block diagram and pin description

RVND5E006A

&6B

',6

&6

&6

,1

,1

6LJQDO&ODPS

8QGHUYROWDJH

Figure 1. Block diagram

5HYHUVH

%DWWHU\

3URWHFWLRQ

&RQWURO 'LDJQRVWLF

&RQWURO 'LDJQRVWLF

3RZHU

&ODPS

'5,9(5

9

21

/L PLWDWLRQ

2YHU

WHPS

&XUUHQW

/LPLWDWLRQ

&+

9

&&

/2*,&

9

6(16(+

)DXOW

29(5/2$'3527(&7,21

$&7,9(32:(5/,0,7$7,21

&XUUHQW

6HQVH

*1'

&+

287

287

$*9

Name

V

CC

OUTn

GND

INn

CSn

CS_DIS

Table 2. Pin function

Function

Battery connection.

Power output.

Ground connection.

Voltage controlled input pin with hysteresis, CMOS compatible. It controls output switch state.

Analog current sense pin, it delivers a current proportional to the load current.

Active high CMOS compatible pin, to disable the current sense pin.

6/37

DocID026961 Rev 1

RVND5E006A Block diagram and pin description

Figure 2. Configuration diagram (top view)

,1B

&6B

1&

&6B',6

*1'

1&

&6B

,1B

9

&&

287B

287B

287B

287B

287B

287B

287B

287B

$*9

Table 3. Suggested connections for unused and not connected pins

Connection / pin

Current sense N.C.

Output Input CS_DIS

Floating

To ground

Not allowed

Through 1 k Ω  resistor

X

X

X

Not allowed

X

Through 10 k Ω  resistor

X

Through 10 k Ω  resistor

DocID026961 Rev 1

7/37

36

Electrical specifications RVND5E006A

9

&6'

Figure 3. Current and voltage conventions

,

6

9

&&

,

&6'

,

287

&6B',6 287

9

287

,

6(16(

9

,1

,

,1

,1 &6

*1'

9

6(16(

,

*1'

9

&&

$*9

3.1 Absolute maximum ratings

Stressing the device above the ratings listed in

Table 4

may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to the conditions in this section for extended periods may affect device reliability.

Symbol

V

CC

V

CCPK

-V

CC

I

OUT

-I

OUT

I

IN

I

CSD

Table 4. Absolute maximum ratings

Parameter

DC supply voltage

Transient supply voltage (T

Reverse DC supply voltage

DC output current

Reverse DC output current

DC input current

DC current sense disable input current

> 0.5

 Ω )

V

CSENSE

Current sense maximum voltage

Value

28

41

16

Internally limited

60

-1 to 10

-1 to 10

V

CC

-41

+V

CC

E

MAX

Maximum switching energy (single pulse)

mH; =  Ω ; V bat

I

OUT

= I limL

(Typ.) ) jstart

600 mJ

Unit

A mA mA

V

V

V

A

V

V

8/37

DocID026961 Rev 1

RVND5E006A Electrical specifications

Symbol

Table 4. Absolute maximum ratings (continued)

Parameter Value

Electrostatic discharge (Human Body Model: R 1.5

k Ω 

V

ESD

V

ESD

T j

T stg

– Input

– Current sense

– CS_DIS

– Output

– V

CC

Charge device model (CDM-AEC-Q100-011)

Junction operating temperature

Storage temperature

4000

2000

4000

5000

5000

750

-40 to 150

-55 to 150

Unit

V

V

°C

°C

Symbol

Table 5. Thermal data

Parameter

R thj-case

R thj-amb

Thermal resistance junction-case (with one channel ON)

Thermal resistance junction-ambient

Maximum value Unit

0.4

°C/W

See

Figure °C/W

DocID026961 Rev 1

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36

Electrical specifications RVND5E006A

10/37

V

CC

150 °C, unless otherwise specified.

Symbol Parameter

Table 6. Power section

Test conditions Min.

Typ. Max. Unit

V

CC

V

USD

Operating supply voltage

Undervoltage shutdown

V

USDhyst

Undervoltage shutdown hysteresis

4.5

R

ON REV

V

I

R

I

ON clamp

S

L(off1)

On-state resistance

Reverse battery on-state resistance

Clamp voltage

Supply current

Off-state output current

(2)

I

OUT

A; °C

I

OUT

A; °C

I

OUT CC

T j

V

CC

T j

V; A;

I

S

= 20 mA

Off-state; V

CC

V

IN

V

OUT

V;

V

SENSE

=

V

CSD

On-state; V

CC

I

OUT

IN

V

IN

=V

OUT

=0V; V

CC

=13V; T j

=25°C

41

0

V

IN

=V

OUT

=0V; V

CC

=13V; T j

=125°C 0

1. PowerMOS leakage included.

2. For each channel.

2

13

3.5

0.5

5

46

(1)

3.5

0.01

28

4.5

m Ω

10 m Ω

8 m Ω

52

5

6

(1)

6.5

3

5 m

μ mA

μ

μ

V

V

V

V

Ω

A

A

A

Symbol t d(on) t d(off)

Table 7. Switching (V

CC

Parameter

Turn-on delay time

Turn-off delay time

Test conditions

R

L

1.3

Ω (see

Figure 6

)

R

L

1.3

Ω (see

Figure 6

)

(dV

OUT

/dt) on

Turn-on voltage slope R

L

1.3

Ω

V; 25

Min.

—

—

—

(dV

OUT

/dt) off

Turn-off voltage slope R

L

1.3

Ω

W

W

ON

OFF

Switching energy losses during t won

Switching energy losses during t woff

R

R

L

L

1.3

1.3

Ω

Ω

(see

(see

Figure

Figure

6

)

6

)

—

—

—

Typ.

35

20

See

Max. Unit

—

—

μ

μ s s

— V  μ s

See

— V  μ s

— mJ 2.5

1.2

— mJ

DocID026961 Rev 1

RVND5E006A Electrical specifications

Symbol Parameter

Table 8. Logic inputs

Test conditions

V

V

I

I

V

IL

IL

IH

IH

I(hyst)

V

CSDL

I

CSDL

V

CSDH

I

CSDH

V

CSD(hyst)

V

V

ICL

CSCL

Input low level voltage

Low level input current V

IN

= 0.9

V

Input high level voltage

High level input current V

IN

= 2.1

V

Input hysteresis voltage

Input clamp voltage

I

IN

I

IN

CS_DIS low level voltage

Low level CS_DIS current V

CSD

= 0.9

V

CS_DIS high level voltage

High level CS_DIS current V

CSD

= 2.1

V

CS_DIS hysteresis voltage

CS_DIS clamp voltage

I

CSD

I

CSD

Min.

Typ.

Max.

Unit

0.9

1

2.1

0.25

5.5

1

2.1

0.25

5.5

-0.7

-0.7

10

7

0.9

10

7

μ A

V

μ A

V

V

V

V

V

V

V

V

μ A

V

μ A

Symbol Parameter

Table 9. Protections and diagnostics

Test conditions

(1)

Min.

Typ.

Max.

Unit

I limH

DC short circuit current

V

CC

V

CC

70 100 140

140

A

A

V

T

T

I

T

T limL

TSD

R

RS

HYST

DEMAG

Short circuit current during thermal cycling

Shutdown temperature

Reset temperature

Thermal reset of status

Thermal hysteresis

(T

TSD

-T

R

)

Turn-off output voltage clamp

I

V

CC

OUT

R

IN

T j

T

0;

TSD

V

150 175

T

RS

+ 1 T

RS

+ 5

135

CC

-28 V

25

7

CC

-31 V

200

CC

-35

V

ON

Output voltage drop limitation

I

OUT

=1 A;

T j

Figure 8 )

25

1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles.

A

°C

V mV

°C

°C

°C

DocID026961 Rev 1

11/37

36

Electrical specifications

Symbol

Table 10. Current sense (8

Parameter

V

CC

Test conditions dK dK dK

I

1

2

3

K

K

/K

K

/K

K

0

1

2

3

/K

1

(1)

2

(1)

3

(1)

SENSE0

V

SENSE

V

SENSEH

(2) t t

I t

SENSEH

(2)

DSENSE1H

DSENSE1L

DSENSE2H

I

I

I

I

OUT

OUT

OUT

OUT

/I

/I

/I

/I

SENSE

SENSE

Current sense ratio drift

SENSE

Current sense ratio drift

SENSE

Current sense ratio drift

Analog sense leakage current

I

OUT

T j

I

OUT

T j

T j

SENSE

SENSE

0.5

V

I

OUT

V

CSD

T j

I

OUT

T j

T j

I

OUT

V

CSD

T j

SENSE

SENSE

SENSE

I

OUT

T j

T j

=

I

OUT

V

T j

CSD

=

SENSE

SENSE

I

OUT

V

CSD

T j

V

CSD

T j

I

OUT

V

CSD

V

IN

SENSE

V

IN

V

IN

SENSE

=

Max analog sense output voltage

Analog sense output voltage in fault conditions

Analog sense output current in fault conditions

I

OUT

V

V

CC

CC

=

CSD

SENSE

SENSE

10 Ω

Delay response time from falling edge of CS_DIS pin

Delay response time from rising edge of CS_DIS pin

Delay response time from rising edge of INPUT pin

I

V

SENSE

I

SENSE

% of I

(see

Figure 4 )

I out

SENSE max

V

SENSE

SENSE

(see

Figure 4 )

V

SENSE

I

SENSE

(see

Figure 4 )

out

<

SENSE max out

SENSE max

RVND5E006A

Min.

Typ.

Max.

Unit

8300 12640 17600

9200

9602

13220

13220

17300

16703

-13 13 %

9500

10408

13120

13120

16900

15907

-10 10 %

0

0

0

5

10600

11278

12920

12920

15600

14644

-7 7 %

8

7

50

1 μ A

2

1

V

V

μ A

μ A mA

100 μ s

5 20 μ s

110 600 μ s

12/37

DocID026961 Rev 1

RVND5E006A Electrical specifications

Symbol

Table 10. Current sense (8

Parameter

CC

Test conditions Min.

 t t

DSENSE2H

DSENSE2L

Delay response time between rising edge of output current and rising edge of current sense

I

I

V

SENSE

SENSEMAX;

OUTMAX

I

OUT

Delay response time from falling edge of INPUT pin

V

SENSE

I

SENSE

(see

Figure 4 )

I

SENSE

% I

7 )

OUTMAX

; out

SENSE max

1. Parameter guaranteed by design; it is not tested.

2. Fault conditions includes: power limitation, overtemperature and open-load off-state detection.

Typ.

Max.

Unit

100

300 μ s

250 μ s

Symbol

Table 11. Open-load detection (8

Parameter Test conditions

V

CC

<

Min.

Typ.

t

DSTKON

I

V

I

OL

OL

L(off2) td_vol

Open-load off-state voltage detection threshold

V

IN

V, V

CC

<

Off-state output current at V

OUT

= 4 V

Delay response from output rising edge to

V

SENSE

rising edge in open-load

V

IN rising from 0

SENSE

V to 4

V

OUT

V

V

V

IN

SENSE

=

OUT

V;

90 % of V

SENSEH

2

Open-load on-state current detection threshold

Output short circuit to

V

CC

detection delay at turn off

V

IN

V, V

CC

<

I

SENSE

= 5 μ A

10

See

Figure 5 180

-120

—

—

—

—

—

Max.

Unit

4 V

100 mA

1200 μ s

0

20

μ A

μ s

Figure 4. Current sense delay characteristics

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DocID026961 Rev 1

13/37

36

Electrical specifications

9

287

G9

287

GW

RQ

W

U

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GRQ

9

,1

Figure 5. Open-load off-state delay timing

287387678&.$79

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Figure 6. Switching characteristics

W

:RII

W

GRII

W

I

G9

287

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RII

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W

W

$*9

14/37

DocID026961 Rev 1

RVND5E006A Electrical specifications

Figure 7. Delay response time between rising edge of output current and rising edge of current sense (CS enabled)

9

,1 ǻW

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Figure 8. Output voltage drop limitation

9

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DocID026961 Rev 1

15/37

36

Electrical specifications

,RXW,VHQVH

$

Figure 9. I

OUT

/I

SENSE

vs I

OUT

%

RVND5E006A

&

'

(

,RXW>$@

$ 0D[7M ƒ&WRƒ&

% 0D[7M ƒ&WRƒ&

& 7\SLFDO7M ƒ&WRƒ&

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Figure 10. Maximum current sense ratio drift vs load current

G..>@

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%

16/37

,RXW>$@

$ 0D[7M ƒ&WRƒ&

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1. Parameter guaranteed by design; it is not tested.

DocID026961 Rev 1

RVND5E006A Electrical specifications

Conditions

Normal operation

Overtemperature

Undervoltage

Overload

Table 12. Truth table

Input

L

H

L

H

L

H

H

H

Output

L

L

L

H

L

L

X

(no power limitation)

Cycling

(power limitation)

L

L

Sense (V

CSD

0

Nominal

0

V

SENSEH

0

0

Nominal

V

SENSEH

Short circuit to GND

(Power limitation)

Open-load off-state

(with external pull up)

Short circuit to V

CC

(external pull up disconnected)

Negative output voltage clamp

L

H

L

L

H

L

H

H

H

L

V

V

V

0

SENSEH

SENSEH

SENSEH

< Nominal

0

1. If the V

CSD

is high, the SENSE output is at a high impedance, its potential depends on leakage currents and external circuit.

(1)

DocID026961 Rev 1

17/37

36

Electrical specifications RVND5E006A

ISO 7637-2:

2004(E)

Test Pulse

Table 13. Electrical transient requirements (part 1/3)

III

Test levels

(1)

IV

Number of pulses or test times

Burst cycle/pulse repetition time

Delays and impedance

1

2a

3a

3b

-75 V

+37 V

-100 V

+75 V

-100 V

+50 V

-150 V

+100 V

5000 pulses

5000 pulses

1h

1h

0.5 s

0.2 s

90 ms

90 ms

5 s

5 s

100 ms

100 ms

2 ms, 10

50  s, 2

Ω

Ω

0.1  s, 50 Ω

0.1  s, 50 Ω

4

5b

(2)

-6 V

+65 V

-7 V

+87 V

1 pulse

1 pulse

-

-

100 ms, 0.01

400 ms, 2 Ω

1. The above test levels must be considered referred to V

CC

13.5

V except for pulse 5b.

2. Valid in case of external load dump clamp: 40V maximum referred to ground. The protection strategy allows PowerMOS to be cyclically switched on during load dump, so distributing the load dump energy along the time and to transfer a part of it to the load.

Ω

ISO 7637-2:

2004(E)

Test Pulse

Table 14. Electrical transient requirements (part 2/3)

III

Test level results

(1)

IV

1

2a

C

C

C

C

3a

3b

C

C

C

C

5b

4

(2)(3)

C

C

C

C

1. The above test levels must be considered referred to V

CC

13.5

V except for pulse 5b.

2. Valid in case of external load dump clamp: 40V maximum referred to ground. The protection strategy allows PowerMOS to be cyclically switched on during load dump, so distributing the load dump energy along the time and to transfer a part of it to the load.

3. Suppressed load dump (pulse 5b) is withstood with a minimum load connected as specified in

Table 4: Absolute maximum ratings .

Class

C

E

Table 15. Electrical transient requirements (part 3/3)

Contents

All functions of the device are performed as designed after exposure to disturbance.

One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the

18/37

DocID026961 Rev 1

RVND5E006A

3.4 Waveforms

Electrical specifications

Figure 11. Normal operation

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DocID026961 Rev 1

19/37

36

Electrical specifications RVND5E006A

Figure 13. Intermittent overload

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DocID026961 Rev 1

RVND5E006A Electrical specifications

Figure 15. Short to V

CC

6KRUWWR9

&&

5HVLVWLYH

6KRUWWR9

&&

+DUG

6KRUWWR9

&&

9

2/

9

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evolution in overload or short to GND

7

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DocID026961 Rev 1

21/37

36

Electrical specifications RVND5E006A

3.5 Electrical characteristics curves

Figure 17. Off-state output current

,ORII>Q$@

Figure 18. High level input current

,LK>X$@

9LQ 9

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Figure 19. Input clamp voltage

,LQ P$

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Figure 20. Input high level voltage

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Figure 21. Input low level voltage

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Figure 22. Input hysteresis voltage

9LK\VW>9@

22/37

7F>ƒ&@

$*9

DocID026961 Rev 1

7F>ƒ&@

$*9

RVND5E006A

Figure 23. On-state resistance vs T case

5RQ>P2KP@

,RXW $

9FF 9

Electrical specifications

Figure 24. On-state resistance vs V

CC

5RQ>P2KP@

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Figure 25. Undervoltage shutdown

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Figure 26. I

LIMH

vs T case

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Figure 27. Turn-on voltage slope

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Figure 28. Turn-off voltage slope

G9RXWGW2II>9PV@

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5O ȍ

7F>ƒ&@

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DocID026961 Rev 1

7F>ƒ&@

$*9

23/37

36

Electrical specifications

Figure 29. CS_DIS clamp voltage

9FVGFO>9@

,LQ P$

RVND5E006A

Figure 30. Low level CS_DIS voltage

9FVGO>9@

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Figure 31. High level CS_DIS voltage

9FVGK>9@

7F>ƒ&@

$*9

7F>ƒ&@

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24/37

DocID026961 Rev 1

RVND5E006A Application information

Note:

4.1

4.2

Figure 32. Application schematic

9

9

&&

9

5

SURW &6B',6

'

OG

0&8

5

SURW

5

SURW

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Channel 2 has the same internal circuit as channel 1.

Load dump protection

D ld

is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the

V

CC

max DC rating. The same applies if the device is subject to transients on the V that are greater than the ones shown in the ISO 7637-2 2004 (E) table.

CC

line

MCU I/Os protection

When negative transients are present on the V

CC

line, the control pins are pulled negative to approximately -1.5

V. ST suggests to insert a resistor (R microcontroller I/O pins from latching-up. prot

) in line to prevent the

The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os.

Equation 1

-V

CCpeak

/I latchup

 R prot

 (V

OH  C

- V

IH

) / I

IHmax

Calculation example:

For V

CCpeak

= -1.5

V and I latchup

 20 V

OH  C

 4.5

V

75   R prot

 240 k  .

Recommended values: R prot

10  C

EXT

10 .

DocID026961 Rev 1

25/37

36

Application information

4.3 Current sense and diagnostic

RVND5E006A

The current sense pin performs a double function (see

Figure diagnostic ):

33: Current sense and

 Current mirror of the load current in normal operation, delivering a current proportional to the load one according to a known ratio K

X

.

The current I

SENSE external resistor R

can be easily converted to a voltage V

SENSE

SENSE

. Linearity between I minimum (see parameter V

SENSE

in

Table

by means of an

OUT

and V

SENSE

is ensured up to 5V

VCC < ). The

current sense accuracy depends on the output current (refer to current sense electrical characteristics

Table 10: Current sense (8 VCC < ).

 Diagnostic flag in fault conditions , delivering a fixed voltage V

SENSEH maximum current I

SENSEH

up to a

in case of the following fault conditions (refer to

Truth table ):

– Power limitation activation

– Overtemperature

– Short to V

CC

in off-state

– Open-load in off-state with additional external components.

A logic level high on CS_DIS pin sets at the same time all the current sense pins of the device in a high impedance state, thus disabling the current monitoring and diagnostic detection. This feature allows multiplexing of the microcontroller analog inputs by sharing of sense resistance and ADC line among different devices.

Figure 33. Current sense and diagnostic

9

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26/37

DocID026961 Rev 1

RVND5E006A

4.3.1

Application information

Short to V

CC

and off-state open-load detection

Short to V

CC

A short circuit between V

CC

V

SENSEH and output is indicated by the relevant current sense pin set to

during the device off-state. Small or no current is delivered by the current sense during the on-state depending on the nature of the short circuit.

Off-state open-load with external circuitry

Detection of an open-load in off mode requires an external pull-up resistor R

PU the output to a positive supply voltage V

PU

.

connecting

It is preferable V

PU

to be switched off during the module standby mode in order to avoid the overall standby current consumption to increase in normal conditions, i.e. when load is connected.

For proper open-load detection in off-state, the external pull-up resistor must be selected according to the following formula:

For the values of V

OLmin

,V

OLmax

18

.

, and I

L(off2)

see Table 11: Open-load detection

DocID026961 Rev 1

27/37

36

Application information

4.4 Maximum demagnetization energy (V

CC

=

Figure 34. Maximum turn-off current versus inductance

RVND5E006A

91'($63 6LQJOH3XOVH

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A: T jstart

= 150°C single pulse

B: T jstart

= 100°C repetitive pulse

C: T jstart

= 125°C repetitive pulse

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Values are generated with R

L

= Ω .

In case of repetitive pulses, T jstart

(at the beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B.

28/37

DocID026961 Rev 1

RVND5E006A

5 Package and PCB thermal data

Package and PCB thermal data

5.1 PowerSO-16 thermal data

Figure 35. PowerSO-16 PC board

$*9

1. Layout condition of R area mm x 86 th

and Z th

measurements (PCB: Double layer, Thermal Vias, FR4 areas: from minimum pad lay-out to 8cm

1.6

2 ).

mm, Cu thickness 70  m (front and back side), Copper

Figure 36. R thj-amb

vs PCB copper area in open box free air condition (one channel

ON)

57+MBDPEYV&XKHDWVLQNDUHD

57+MDPE

3&%&XKHDWVLQNDUHDFPA

$*9

DocID026961 Rev 1

29/37

36

Package and PCB thermal data RVND5E006A

Figure 37. PowerSO-16 thermal impedance junction ambient single pulse (one channel ON)

=7+ƒ&:

&X FP

&X FP

&X IRRWSULQW

7LPHV

$*9

Figure 38. Thermal fitting model of a double channel HSD in PowerSO-16

30/37

1. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered.

Equation 2: pulse calculation formula

ZTH

 = RTH where



=

 

+ –

 

DocID026961 Rev 1

RVND5E006A

Area/island (cm

2

)

R1 =

R2 =

C1 =

C2 =

R3 (°C/W)

R4 (°C/W)

R5 (°C/W)

R6 (°C/W)

C3 (W.s/°C)

C4 (W.s/°C)

C5 (W.s/°C)

C6 (W.s/°C)

Package and PCB thermal data

Table 16. Thermal parameters

Footprint

12

22

0.01

0.1

0.05

0.4

1

7

1

2

3

5

2

10

18

4

6

8

8

12

7

12

DocID026961 Rev 1

31/37

36

Package information RVND5E006A

6.1 ECOPACK

®

packages

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK

® specifications, grade definitions and product status are available at: www.st.com

.

ECOPACK

®

is an ST trademark.

Figure 39. PowerSO-16 package dimensions

32/37

DocID026961 Rev 1

$*9

RVND5E006A

Dim.

e

R1

R2

T

T1

T2

G

L e1

F c

D

D1 d

A1

A2

A3

A4 a b

E (1)

E1

E2

E3

0.27

0.23

9.4

7.4

0

13.85

9.3

7.3

5.9

Table 17. PowerSO-16 mechanical data mm

Min.

0

3.4

1.2

0.15

Typ.

0.27

9.5

7.5

0.05

0.05

3.5

1.3

0.2

0.2

0.35

14.1

9.4

7.4

6.1

0.8

0.8

5.6

0.5

1.2

1

2°

0.8

5°

6° (typ.)

10° (typ.)

Package information

1.1

0.25

8°

Max.

0.1

3.6

1.4

0.25

0.43

0.32

9.6

7.6

0.1

14.35

9.5

7.5

6.3

DocID026961 Rev 1

33/37

36

Package information RVND5E006A

$

Figure 40. PowerSO-16 tube shipment (no suffix)

Base Q.ty

Bulk Q.ty

A

B

C (± 0.1)

Tube length (± 0.5)

All dimensions are in mm.

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1000

4.9

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Figure 41. PowerSO-16 tape and reel shipment (suffix “TR”)

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RVND5E006A Package information

Figure 42. PowerSO-16 suggested pad layout

$*9

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Revision history

Date

29-Sep-2014

Table 18. Document revision history

Revision Changes

1 Initial release.

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