STMicroelectronics VND5E160MJ-E Datasheet
Advertentie
Advertentie
VND5E160MJ-E
Double-channel high-side driver with analog current sense for automotive applications
Features
Max transient supply voltage
Operating voltage range V
CC
Max on-state resistance (per ch.) R
ON
Current limitation (typ.)
Off-state supply current
V
CC
I
LIMH
I
S
41 V
4.5 V to 28 V
160 m
10 A
2 µA
(1)
1. Typical value with all loads connected.
• General
– Inrush current active management by power limitation
– Very low standby current
– 3 V CMOS compatible inputs
– Optimized electromagnetic emissions
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/EC european directive
– Very low current sense leakage
• Diagnostic functions
– Proportional load current sense
– High-precision current sense for wide currents range
– Current sense disable
– Overload and short to ground (power limitation) indication
– Thermal shutdown indication
• Protections
– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss of V
CC
– Overtemperature shutdown with auto restart (thermal shutdown)
– Reverse battery protected (see Figure 29 )
PowerSSO-12
– Electrostatic discharge protection
Application
• All types of resistive, inductive and capacitive loads
• Suitable as LED driver
Description
The VND5E160MJ-E is a double-channel high-side driver manufactured in the ST proprietary VIPower™ M0-5 technology and housed in the tiny PowerSSO-12 package. The
VND5E160MJ-E is designed to drive 12 V automotive grounded loads delivering protection, diagnostics and easy 3 V and 5 V CMOS compatible interface with any microcontroller.
The device integrates advanced protective functions such as load current limitation, inrush and overload active management by power limitation, overtemperature shut-off with auto-restart and overvoltage active clamp. A dedicated analog current sense pin is associated with every output channel in order to provide enhanced diagnostic functions including fast detection of overload and short-circuit to ground through power limitation indication and overtemperature indication.
The current sensing and diagnostic feedback of the whole device can be disabled by pulling the
CS_DIS pin high to allow sharing of the external sense resistor with other similar devices.
September 2013 Doc ID 15616 Rev 2 1/34 www.st.com
1
Contents
Contents
VND5E160MJ-E
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 22
Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 22
Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 23
Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Maximum demagnetization energy (VCC = 13.5 V) . . . . . . . . . . . . . . . . . 25
Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2/34 Doc ID 15616 Rev 2
VND5E160MJ-E
List of tables
List of tables
Doc ID 15616 Rev 2 3/34
List of figures
List of figures
VND5E160MJ-E
Current and voltage conventions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Delay response time between rising edge of output current and rising edge of current sense
Maximum current sense ratio drift vs load current
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
J
evolution in overload or short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
LIMH
vs T case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Maximum turn-off current versus inductance (for each channel)
(1)
. . . . . . . . . . . . . . . . . . 25
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Rthj-amb vs PCB copper area in open box free air condition (one channel on) . . . . . . . . . 26
PowerSSO-12 thermal impedance junction ambient single pulse (one channel on) . . . . . 27
Thermal fitting model of a double-channel HSD in PowerSSO-12
(1)
. . . . . . . . . . . . . . . . . 27
4/34 Doc ID 15616 Rev 2
VND5E160MJ-E
1
Block diagram and pin description
Block diagram and pin description
Figure 1.
Block diagram
IN1
IN2
Signal Clamp
Undervoltage Control & Diagnostic 1
Power
Clamp
DRIVER
V
ON
Limitation
Over temp.
Current
Limitation
CH 1
V
CC
CS_
DIS
CS1
CS2
LOGIC
V
SENSEH
Current
Sense
OVERLOAD PROTECTION
(ACTIVE POWER LIMITATION)
GND
CH 2
OUT2
OUT1
Table 1.
Name
Pin function
V
CC
OUT n
GND
IN n
CS n
CS_DIS
Function
Battery connection.
Power output.
Ground connection. Must be reverse battery protected by an external diode/resistor network.
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state.
Analog current sense pin, delivers a current proportional to the load current.
Active high CMOS compatible pin, to disable the current sense pin.
Doc ID 15616 Rev 2 5/34
Block diagram and pin description
Figure 2.
Configuration diagram (top view)
GND
IN2
IN1
CS1
CS2
CS_DIS
4
5
6
1
2
3
12
11
10
9
8
7
TAB = V cc
N.C.
OUT2
OUT2
OUT1
OUT1
N.C.
VND5E160MJ-E
PowerSSO-12
Table 2.
Suggested connections for unused and not connected pins
Connection / pin Current sense N.C.
Output Input
Floating
To ground
Not allowed
Through 1 k resistor
X
X
X
Not allowed
CS_DIS
X X
Through 10 k resistor
Through 10 k resistor
6/34 Doc ID 15616 Rev 2
VND5E160MJ-E Electrical specifications
2.1
Figure 3.
Current and voltage conventions
V
CSD
I
CSD
I
IN1
V
IN1
I
IN2
V
IN2
CS_DIS
IN1
IN2
GND
I
S
V
CC
OUT1
CS1
OUT2
CS2
V
Fn
I
OUT1
I
SENSE1
V
SENSE1
I
OUT2
I
SENSE2
V
SENSE2
V
OUT2
V
OUT1
I
GND
V
CC
1. V
Fn
= V
OUTn
- V
CC
during reverse battery condition.
Absolute maximum ratings
Stressing the device above the rating listed in the “absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to the conditions in table below for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE program and other relevant quality document.
Table 3.
Symbol
Absolute maximum ratings
Parameter
V
CC
-V
CC
- I
GND
I
OUT
- I
OUT
I
IN
I
CSD
-I
CSENSE
DC supply voltage
Reverse DC supply voltage
DC reverse ground pin current
DC output current
Reverse DC output current
DC input current
DC current sense disable input current
DC reverse CS pin current
V
CSENSE
Current sense maximum voltage
Value
41
0.3
200
Internally limited
6
-1 to 10
-1 to 10
200
V
CC
-41
+V
CC
Unit
V
V mA
A
A mA mA mA
V
V
Doc ID 15616 Rev 2 7/34
Electrical specifications
Table 3.
Symbol
E
MAX
V
ESD
V
ESD
T j
T stg
Absolute maximum ratings (continued)
Parameter
Maximum switching energy (single pulse)
(L = 12 mH, R
L
I
OUT
= I limL
= 0 , V
(Typ.) ) bat
= 13.5 V, T jstart
= 150 °C,
Electrostatic discharge (human body model: R = 1.5 K
C = 100 pF)
- IN
- CS
- CS_DIS
- OUT
- V
CC
Charge device model (CDM-AEC-Q100-011)
Junction operating temperature
Storage temperature
VND5E160MJ-E
Value
34
Unit mJ
4000
2000
4000
5000
5000
750
-40 to 150
-55 to 150
V
°C
V
V
V
V
V
°C
Table 4.
Symbol
Thermal data
Parameter
R thj-case
R thj-amb
Thermal resistance junction-case (with one channel on)
Thermal resistance junction-ambient
Max. value Unit
8 °C/W
See
°C/W
8/34 Doc ID 15616 Rev 2
VND5E160MJ-E Electrical specifications
Values specified in this section are for 8 V < V
CC otherwise stated.
< 28 V, -40 °C < T j
< 150 °C, unless
Table 5.
Symbol
Power section
Parameter
V
CC
Operating supply voltage
V
USD
Undervoltage shutdown
V
USDhyst
Undervoltage shutdown hysteresis
Test conditions
V
I
R
I
ON clamp
S
L(off1)
V
F
ON-state resistance (1)
Clamp voltage
Supply current
OFF-state output current (1)
Output - V voltage (1)
CC
diode
1. For each channel.
2. PowerMOS leakage included.
I
OUT
= 1 A, T j
= 25 °C
I
OUT
= 1 A, T j
= 150 °C
I
OUT
= 1 A, V
CC
= 5 V, T j
= 25 °C
I
S
= 20 mA
OFF-state: V
CC
= 13 V, T j
= 25 °C,
V
IN
= V
OUT
= V
SENSE
= V
CSD
= 0 V
ON-state: V
CC
= 13 V, V
IN
= 5 V,
I
OUT
= 0 A
V
IN
T j
= V
OUT
= 25 °C
= 0 V, V
CC
= 13 V,
V
IN
T j
= V
OUT
= 125 °C
= 0 V, V
CC
= 13 V,
-I
OUT
= 0.6 A, T j
= 150 °C
Min. Typ. Max. Unit
4.5
13 28 V
3.5
4.5
V
0.5
160
320
210
41 46 52
2
(2)
5
(2) m
V
µA
3
V
6 mA
0 0.01
3
0 5
µA
0.7
V
Table 6.
Symbol t d(on) t d(off)
Switching (V
CC
= 13 V, T j
= 25 °C)
Parameter Test conditions
Turn-on delay time
Turn-off delay time
R
L
= 13
R
L
= 13 (see
(dV
OUT
/dt) on
Turn-on voltage slope R
L
= 13
(dV
OUT
/dt) off
Turn-off voltage slope
W
W
ON
OFF
Switching energy losses during t won
Switching energy losses during t woff
R
L
= 13
R
L
= 13 (see
R
L
= 13 (see
Min.
Typ.
10
15
See
See
Max.
Unit
µs
µs
V/µs
V/µs
0.03
0.02
mJ mJ
Doc ID 15616 Rev 2 9/34
Electrical specifications VND5E160MJ-E
Table 7.
Symbol
Logic inputs
Parameter Test conditions
V
IL
I
IL
V
IH
I
IH
V
I(hyst)
Low-level input voltage
Low-level input current
High-level input voltage
High-level input current
Input voltage hysteresis
V
V
IN
IN
= 0.9 V
= 2.1 V
V
ICL
Input voltage clamp
I
IN
= 1 mA
I
IN
= -1 mA
V
CSDL
I
CSDL
V
CSDH
I
CSDH
V
CSD(hyst)
V
CSCL
Low-level CS_DIS voltage
Low-level CS_DIS current
High-level CS_DIS voltage hysteresis CS_DIS voltage
CS_DIS voltage clamp
V
High-level CS_DIS current V
CSD
CSD
= 0.9 V
= 2.1 V
I
CSD
= 1mA
I
CSD
= -1mA
Min.
Typ.
Max. Unit
1
2.1
0.25
5.5
0.9
10
7
V
µA
V
µA
V
V
-0.7
1
2.1
0.25
5.5
0.9
10
7
V
µA
V
µA
V
V
-0.7
Table 8.
Symbol
Protections and diagnostics (1)
Parameter Test conditions Min.
Typ.
Max.
Unit
I limH
DC short-circuit current
I limL
Short-circuit current during thermal cycling
T
TSD
T
R
Shutdown temperature
Reset temperature
T
RS
Thermal reset of
STATUS
T
HYST
V
DEMAG
Thermal hysteresis
(T
TSD
- T
R
)
Turn-off output voltage clamp
V
CC0
= 13 V
5 V < V
CC
< 28 V
V
CC
T
R
= 13 V,
< T j
< T
TSD
7
150
T
RS
135
10
2.5
175
+ 1 T
RS
7
+ 5
14
14
200
A
A
°C
°C
°C
°C
V
ON
Output voltage drop limitation
I
OUT
= 1 A, V
IN
= 0 V,
L = 20 mH
I
OUT
= 0.03 A,
T j
= -40 °C to 150 °C
(see
V
CC
- 41 V
CC
- 46 V
25
CC
- 52 V
1. To ensure long term reliability under heavy overload or short-circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles.
mV
10/34 Doc ID 15616 Rev 2
VND5E160MJ-E Electrical specifications
Table 9.
Symbol
Current sense (8 V < VCC < 18 V)
Parameter Test conditions Min. Typ. Max. Unit dK dK dK
1
2
3
/K
/K
/K
1
(1)
2
(1)
3
(1)
V
SENSEH
(2)
I
I
V
I
K
K
K
K
0
1
2
3
SENSE0
OL
SENSE
SENSEH
(2)
I
I
I
I
OUT
OUT
Current sense ratio drift
OUT
Current sense ratio drift
OUT
/I
/I
/I
/I
SENSE
SENSE
SENSE
SENSE
Current sense ratio drift
Analog sense leakage current
I
OUT
= 0.025 A, V
SENSE
V
CSD
= 0 V, T j
= 0.5 V,
= -40 °C to 150 °C
I
OUT
= 0.35 A, V
SENSE
V
CSD
= 0 V, T j
= 0.5 V,
= -40 °C to 150 °C
I
OUT
= 0.35 A, V
SENSE
V
CSD
= 0 V, T j
= 0.5 V,
= 25 °C to 150 °C
I
OUT
= 0.35 A; V
SENSE
= 0.5 V,
V
CSD
= 0 V, T j
= -40 °C to 150 °C
I
OUT
= 0.5 A, V
SENSE
= 4 V, V
CSD
= 0 V,
T j
= -40 °C to 150 °C
I
OUT
= 0.5 A, V
SENSE
= 4 V, V
CSD
= 0 V,
T j
= 25 °C to 150 °C
I
OUT
= 0.5 A, V
SENSE
= 4 V,
V
CSD
= 0 V,
T j
= -40 °C to 150 °C
I
OUT
= 1.5 A, V
SENSE
= 4 V, V
CSD
= 0 V,
T j
= -40 °C to 150 °C
I
OUT
= 1.5 A, V
SENSE
= 4 V, V
CSD
= 0 V,
T j
= 25 °C to 150 °C
I
OUT
= 1.5 A, V
SENSE
= 4 V,
V
CSD
= 0 V,
T j
= -40 °C to 150 °C
I
OUT
V
IN
= 0 A, V
SENSE
= 0 V, T j
= 0 V, V
CSD
= 5 V,
= -40 °C to 150 °C
I
OUT
V
IN
= 0 A, V
SENSE
= 5 V, T j
= 0 V;, V
CSD
= 0 V,
= -40 °C to 150 °C
I
OUT
V, V
= 0.6 A, V
IN
= 5 V, T
SENSE
= 0 V; V
CSD
= 5 j
= -40 °C to 150 °C
Open-load ON-state current detection threshold
Max analog sense output voltage
I
V
IN
= 5 V, 8 V < V
CC
< 18 V
I
SENSE
= 5 µA
OUT
= 1.5 A, V
CSD
= 0 V
Analog sense output voltage in fault condition
V
CC
= 13 V, R
SENSE
= 3.9 K
Analog sense output current in fault condition
V
CC
= 13 V, V
SENSE
= 5 V
270 520 730
345 470 610
370 470 540
-13
370 460 550
390 460 510
-8
400 430 470
410 430 460
-4
0
0
0
1
5
8
9
13
8
4
1
2
1
5
%
%
%
µA mA
V
V mA
Doc ID 15616 Rev 2 11/34
Electrical specifications
Table 9.
Symbol
Current sense (8 V < VCC < 18 V) (continued)
Parameter Test conditions t t
DSENSE1H
DSENSE1L
Delay response time from falling edge of
CS_DIS pin
V
SENSE
< 4 V,
0.08 A < I
OUT
< 1.5 A
I
SENSE
= 90% of I
)
SENSE max
Delay response time from rising edge of
CS_DIS pin
V
SENSE
< 4 V,
0.08 A < I
OUT
< 1.5 A
I
SENSE
= 10% of I
SENSE max
) t
t
DSENSE2H t
DSENSE2H
DSENSE2L
Delay response time from rising edge of
IN pin
V
SENSE
< 4 V,
0.08 A < I
OUT
< 1.5 A
I
SENSE
=90% of I
)
SENSE max
Delay response time between rising edge of output current and rising edge of current sense
V
SENSE
< 4V,
I
SENSE
= 90% of I
SENSEMAX,
I
OUT
= 90% of I
OUTMAX
I
OUTMAX
= 1.5 A (see
)
Delay response time from falling edge of
IN pin
V
SENSE
< 4 V,
0.08 A < I
OUT
< 1.5 A
I
SENSE
= 10% of I
SENSE max
)
1. Parameter guaranteed by design; it is not tested.
2. Fault condition includes: power limitation and overtemperature.
Figure 4.
Current sense delay characteristics
INPUT
CS_DIS
LOAD CURRENT
CURRENT SENSE t
DSENSE2H t
DSENSE1L
VND5E160MJ-E
Min. Typ. Max. Unit
40 100 µs
5 20 µs
30 150 µs
80 250 µs t
DSENSE1H t
DSENSE2L
110 µs
12/34 Doc ID 15616 Rev 2
VND5E160MJ-E
Figure 5.
Switching characteristics
V
OUT t
Won
80% dV
OUT
/dt
(on) t r
INPUT t d(on)
10% t d(off) t
Woff
90% t f
Electrical specifications dV
OUT
/dt
(off) t t
Figure 6.
Delay response time between rising edge of output current and rising edge of current sense (CS enabled)
V
IN
t
DSENSE2H t
I
OUT
90% I
OUTMAX
I
OUTMAX t
I
SENSE I
SENSEMAX
90% I
SENSEMAX t
Doc ID 15616 Rev 2 13/34
Electrical specifications
Figure 7.
Output voltage drop limitation
Vcc-Vout
Tj=150 o
C
Tj=25 o
C
Tj=-40 o
C
VND5E160MJ-E
Von
Iout
Von/Ron(T)
Figure 8.
I out
/ I sense
vs I out
I out
/ I sense
700
450
400
350
300
650
600
550
500
250
200
0,35
A
B
C
0,58
D
E
0,81
I
OUT
(A)
1,04
A : Max, T j
B : Max, T j
= -40 °C to 150 °C
= 25 °C to 150 °C
C : Typical, T j
= -40 °C to 150 °C
1,27
D : Min, T j
E : Min, T j
= 25 °C to 150 °C
= -40 °C to 150 °C
1,5
14/34 Doc ID 15616 Rev 2
VND5E160MJ-E Electrical specifications
Figure 9.
Maximum current sense ratio drift vs load current
dk/k(%)
15
10
5
A
0
-5
B
-10
-15
0,35 0,58 0,81
A : Max, T j
= -40 °C to 150 °C
1. Parameter guaranteed by design; it is not tested.
I
OUT
(A)
1,04 1,27 1,5
B : Min, T j
= 25 °C to 150 °C
Table 10.
Truth table
Conditions
Normal operation
Overtemperature
Undervoltage
Overload
Short-circuit to GND
(power limitation)
Negative output voltage clamp
Input
L
H
L
H
L
H
H
H
L
H
L
Output
L
L
L
H
L
L
X
(no power limitation)
Cycling
(power limitation)
L
L
L
Sense (V
CSD
= 0 V)
(1)
0
Nominal
0
V
SENSEH
0
0
Nominal
V
V
SENSEH
0
SENSEH
0
1. If the V
CSD
is high, the SENSE output is at a high-impedance, its potential depends on leakage currents and external circuit.
Doc ID 15616 Rev 2 15/34
Electrical specifications VND5E160MJ-E
Table 11.
Electrical transient requirements (part 1)
ISO 7637-2:
2004(E)
Test pulse
III
Test levels
(1)
IV
Number of pulses or test times
Burst cycle/pulse repetition time
Min.
Max.
1
2a
3a
3b
4
5b (2)
-75 V
+37 V
-100 V
+75 V
-6 V
+65 V
-100 V
+50 V
-150 V
+100 V
-7 V
+87 V
5000 pulses
5000 pulses
1 h
1 h
1 pulse
1 pulse
0.5 s
0.2 s
90 ms
90 ms
5 s
5 s
100 ms
100 ms
1. The above test levels must be considered referred to V
CC
= 13.5 V except for pulse 5b.
2. Valid in case of external load dump clamp: 40 V maximum referred to ground.
Delays and
Impedance
2 ms, 10
50 µs, 2
0.1 µs, 50
0.1 µs, 50
100 ms, 0.01
400 ms, 2
Table 12.
Electrical transient requirements (part 2)
ISO 7637-2:
2004(E)
Test pulse III
Test level results
1
2a
3a
3b
4
5b
(1)
C
C
C
C
C
C
1. Valid in case of external load dump clamp: 40 V maximum referred to ground.
IV
C
C
C
C
C
C
Table 13.
Electrical transient requirements (part 3)
Class Contents
C
E
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
16/34 Doc ID 15616 Rev 2
VND5E160MJ-E
2.4 Waveforms
Figure 10. Normal operation
Electrical specifications
Normal operation
INPUT
Nominal load Nominal load
I
OUT
V
SENSE
V
CS_DIS
Figure 11. Overload or short to GND
Overload or Short to GND
INPUT
I
LimH
>
I
OUT
Power Limitation
I
LimL
>
Thermal cycling
V
SENSE
V
CS_DIS
Doc ID 15616 Rev 2 17/34
Electrical specifications
Figure 12. Intermittent overload
Intermittent Overload
VND5E160MJ-E
INPUT
I
LimH
>
I
OUT
V
SENSEH
>
V
SENSE
V
CS_DIS
Overload
I
LimL
>
Nominal load
Figure 13. T
J
evolution in overload or short to GND
T
J
evolution in
Overload or Short to GND
INPUT
Self-limitation of fast thermal transients T
TSD
T
R
T
J
I
LimH
>
T
J_START
Power Limitation
T
HYST
< I
LimL
I
OUT
18/34 Doc ID 15616 Rev 2
VND5E160MJ-E Electrical specifications
Figure 14. OFF-state output current
Iloff (nA)
300
250
200
150
100
50
Off State
Vcc=13V
Vin=Vout=0V
0
-50 -25 0 25 50 75
Tc (°C)
100
Figure 16. Input clamp voltage
125 150 175
6,6
6,4
6,2
6
5,8
5,6
5,4
Vicl (V)
7
6,8 lin=1mA
5,2
5
-50 -25 0 25 50 75
Tc (°C)
100 125
Figure 18. High-level input voltage
150 175
Vih (V)
4
3,5
3
2,5
2
1,5
1
0,5
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Figure 15. High-level input current
Iih (µA)
5
4,5
4
3,5
3
2,5
2
1,5
1
Vin=2.1V
0,5
0
-50 -25 0 25 50 75
Tc (°C)
100 125
Figure 17. Low-level input voltage
150 175
1,6
1,4
1,2
1
0,8
0,6
0,4
Vil (V)
2
1,8
0,2
0
-50 -25 0 25 50 75
Tc (°C)
100 125
Figure 19. Hysteresis input voltage
150 175
Vihyst (V)
1
0,9
0,8
0,7
0,6
0,5
0,4
0,3
0,2
0,1
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Doc ID 15616 Rev 2 19/34
Electrical specifications
Figure 20. ON-state resistance vs T case
Ron (mOhm)
300
250
Iout= 1A
Vcc=13V
200
150
100
50
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Figure 22. Undervoltage shutdown
Vusd (V)
16
10
8
6
4
14
12
2
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Figure 24. I
LIMH
vs T case
Ilimh (A)
20
Vcc=13V
15
10
5
0
-50 -25 0 25 50
Tc (°C)
75 100 125 150
VND5E160MJ-E
Figure 21. ON-state resistance vs V
CC
Ron (mOhm)
300
250
Tc=150°C
Tc=125°C
200
150
100
Tc=25°C
Tc=-40°C
50
0 5 10 15 20
Vcc (V)
25
Figure 23. Turn-on voltage slope
30 35 40
(dVout/dt )On (V/ms)
1000
900
800
700
600
500
400
300
200
100
0
-50 -25 0
Vcc=13V
RI=13 Ohm
25 50 75
Tc (°C)
100 125 150 175
Figure 25. Turn-off voltage slope
(dVout/dt )Off (V/ms)
1400
1300
1200
1100
1000
900
800
700
600
500
-50 -25 0 25
Vcc=13V
RI= 13 Ohm
50 75
Tc (°C)
100 125 150 175
20/34 Doc ID 15616 Rev 2
VND5E160MJ-E
Figure 26. High-level CS_DIS voltage
Vcsdh (V)
4
3,5
3
2,5
2
1,5
1
0,5
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Figure 28. Low-level CS_DIS voltage
Vcsdl (V)
3
2,5
2
1,5
1
0,5
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Electrical specifications
Figure 27. CS_DIS clamp voltage
Vcsdcl(V)
10
9
8
7
4
3
2
6
5
1
0
-50 -25 0
Iin = 1 mA
25 50 75
Tc (°C)
100 125 150 175
Doc ID 15616 Rev 2 21/34
Application information VND5E160MJ-E
Figure 29. Application schematic (1)
+5V
CU
V
CC
R prot CS_DIS
R
R prot prot
C
EXT
R
SENSE
INPUT
CURRENT SENSE
GND
V
GND
R
GND
D
GND
OUTPUT
D ld
3.1
1. Channel 2 has the same internal circuit as channel 1.
GND protection network against reverse battery
This section provides two solutions for implementing a ground protection network against reverse battery.
resistor in the ground line (R
GND
only)
This can be used with any type of load.
The following is an indication on how to dimension the R
GND resistor.
1.
R
GND
600 mV / (I
S(on)max
)
2. R
GND
V
CC
) / (-I
GND
) where -I
GND
is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet.
Power dissipation in R
GND
(when V
CC
< 0: during reverse battery situations) is:
Equation 1
P
D
= (-V
CC
) 2 / R
GND
22/34 Doc ID 15616 Rev 2
VND5E160MJ-E
3.1.2
Application information
This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where I
S(on)max maximum ON-state currents of the different devices.
becomes the sum of the
Please note that if the microprocessor ground is not shared by the device ground then the
R
GND will produce a shift (I
S(on)max
* R
GND
) in the input thresholds and the status output values. This shift will vary depending on how many devices are on in the case of several high-side drivers sharing the same R
GND
.
If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize Solution 2 (see below).
Solution 2: diode (D
GND
) in the ground line
A resistor (R
GND inductive load.
= 1 k should be inserted in parallel to D
GND
if the device drives an
This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift ( 600 mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network.
3.3
D ld
is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the
V
CC
max DC rating. The same applies if the device is subject to transients on the V
CC that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
line
MCU I/Os protection
If a ground protection network is used and negative transient are present on the V
CC the control pins will be pulled negative. ST suggests to insert a resistor (R prot prevent the microcontroller I/Os pins to latch-up.
line,
) in line to
The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (input levels compatibility) with the latch-up limit of microcontroller I/Os:
Equation 2
-V
CCpeak
/ I latchup
R prot
(V
OH C
- V
IH
- V
GND
) / I
IHmax
Calculation example:
For V
CCpeak
= - 100 V, I latchup
20 mA; V
OHµC
4.5 V
5 k R prot
180 k
Recommended values: R prot
=10 k , C
EXT
=10 nF.
Doc ID 15616 Rev 2 23/34
Application information
3.4 Current sense and diagnostic
VND5E160MJ-E
The current sense pin performs a double function (see Figure 30: Current sense and diagnostic
):
?
Current mirror of the load current in normal operation, delivering a current proportional to the load one according to a know ratio K
X
.
The current I
SENSE external resistor R
can be easily converted to a voltage V
SENSE
SENSE
. Linearity between I minimum (see parameter V
SENSE
OUT
and V
SENSE
by means of an
is ensured up to 5 V
Table 9: Current sense (8 V < VCC < 18 V)
). The current sense accuracy depends on the output current (refer to current sense electrical characteristics
Table 9: Current sense (8 V < VCC < 18 V)
).
?
Diagnostic flag in fault conditions , delivering a fixed voltage V
SENSEH maximum current I
SENSEH
):
up to a
in case of the following fault conditions (refer to Table 10:
– Power limitation activation
– Overtemperature
A logic level high on CS_DIS pin sets at the same time all the current sense pins of the device in a high-impedance state, thus disabling the current monitoring and diagnostic detection. This feature allows multiplexing of the microcontroller analog inputs by sharing of sense resistance and ADC line among different devices.
Figure 30. Current sense and diagnostic
V
BAT
V
CC
Main MOSn
41V
Overtemperature
I
OUT
/K
X
I
SENSEH
Pwr_Lim
OUTn
CS_DIS
R
PROT
To uC ADC
R
SENSE
CURRENT
SENSEn
V
SENSEH
V
SENSE
GND
Load
24/34 Doc ID 15616 Rev 2
VND5E160MJ-E
3.5 Maximum demagnetization energy (V
CC
Application information
Figure 31. Maximum turn-off current versus inductance (for each channel)
100
= 13.5 V)
10
A
C
B
1
0,1
0,1 1 L (mH) 10 100
A: T jstart
= 150 °C single pulse
B: T jstart
C: T jstart
= 100 °C repetitive pulse
= 125 °C repetitive pulse
V
IN
, I
L
Demagnetization Demagnetization Demagnetization
1. Values are generated with R
L
= 0
In case of repetitive pulses, T jstart
(at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B.
t
Doc ID 15616 Rev 2 25/34
Package and PC board thermal data
4 Package and PC board thermal data
4.1 PowerSSO-12 thermal data
Figure 32. PowerSSO-12 PC board (1)
VND5E160MJ-E
26/34
1. Layout condition of R th
and Z th
measurements (PCB: double layer, thermal vias, areas: from minimum pad lay-out to 8 cm
2
).
Figure 33. R thj-amb
vs PCB copper area in open box free air condition (one channel on)
RTHj_amb(°C/ W)
70
65
60
55
50
45
40
0 2 4 6
PCB Cu heatsink area (cm^ 2)
8 10
Doc ID 15616 Rev 2
VND5E160MJ-E Package and PC board thermal data
Figure 34. PowerSSO-12 thermal impedance junction ambient single pulse (one channel on)
ZTH (°C/ W)
100
Footprint
2 cm
2
8 cm 2
10
1
0,001 0,01 0,1 1
Time ( s)
Equation 3: pulse calculation formula
ZTH
= RTH + where = t
P
/T
10
–
100 1000
Figure 35. Thermal fitting model of a double-channel HSD in PowerSSO-12
1. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
Doc ID 15616 Rev 2 27/34
Package and PC board thermal data
Table 14.
Thermal parameters
Area/island (cm
2
)
R1= R7 (°C/W)
R2= R8 (°C/W)
R3 (°C/W)
R4 (°C/W)
R5 (°C/W)
R6 (°C/W)
C1= C7 (W.s/°C)
C2= C8 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
Footprint
22
26
0.0008
0.0016
1.2
6
3
8
0.0166
0.2
0.27
3
0.1
0.8
6
8
15
20
2
VND5E160MJ-E
8
7
10
15
0.1
1
9
28/34 Doc ID 15616 Rev 2
VND5E160MJ-E
5
Package and packing information
Package and packing information
5.1 ECOPACK
®
5.2
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK
®
is an ST trademark.
Package mechanical data
Figure 36. PowerSSO-12 package dimensions
Doc ID 15616 Rev 2 29/34
Package and packing information
Table 15.
PowerSSO-12 mechanical data
Symbol h
L k
X
D
E e
H
Y ddd
A
A1
A2
B
C
5.800
0.250
0.400
0°
2.200
2.900
Min.
1.250
0.000
1.100
0.230
0.190
4.800
3.800
Millimeters
Typ.
0.800
VND5E160MJ-E
Max.
1.620
0.100
1.650
0.410
0.250
5.000
4.000
6.200
0.500
1.270
8°
2.800
3.500
0.100
30/34 Doc ID 15616 Rev 2
VND5E160MJ-E Package and packing information
Figure 37. PowerSSO-12 tube shipment (no suffix)
A
B
C
Base q.ty
Bulk q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
100
2000
532
1.85
6.75
0.6
Figure 38. PowerSSO-12 tape and reel shipment (suffix “TR”)
Reel dimensions
Base q.ty
Bulk q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
2500
2500
330
1.5
13
20.2
12.4
60
18.4
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
Tape hole spacing
Component spacing
Hole diameter
Hole diameter
Hole position
Compartment depth
Hole spacing
W
P0 (± 0.1)
P
D (± 0.05)
D1 (min)
F (± 0.1)
K (max)
P1 (± 0.1)
12
4
8
1.5
1.5
5.5
4.5
2
All dimensions are in mm.
End
Top cover tape
No components Components No components
Start
500mm min 500mm min
Empty components pockets saled with cover tape.
User direction of feed
Doc ID 15616 Rev 2 31/34
Order codes VND5E160MJ-E
Table 16.
Device summary
Package
PowerSSO-12
Tube
VND5E160MJ-E
Order codes
Tape and reel
VND5E160MJTR-E
32/34 Doc ID 15616 Rev 2
VND5E160MJ-E
Table 17.
Document revision history
Date Revision
08-Oct-2009
20-Sep-2013
1
2
Initial release.
Updated Disclaimer.
Changes
Revision history
Doc ID 15616 Rev 2 33/34
VND5E160MJ-E
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34/34 Doc ID 15616 Rev 2
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