STFW12N150K5
Nchannel 1500 V, 1.6 Ω typ.,7 A MDmesh™ K5
Power MOSFET in a TO-3PF package
Datasheet - preliminary data
1
2
3
TO-3PF
Figure 1: Internal schematic diagram
Features
Order code V
DS
R
DS(on) max.
I
D
P
TOT
STFW12N150K5 1500 V
1.9 Ω
7 A 63W
Industry’s lowest R
DS(on) * area
Industry’s best FoM (figure of merit)
Ultra low gate charge
100% avalanche tested
Zener-protected
Applications
Switching applications
Description
This very high voltage N-channel Power
MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency.
Order code
STFW12N150K5
Table 1: Device summary
Marking Package
12N150K5 TO-3PF
Packaging
Tube
May 2015 DocID027835 Rev 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/10 www.st.com
Contents
Contents
STFW12N150K5
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
3 Test circuits ..................................................................................... 6
4 Package information ....................................................................... 7
4.1
TO-3PF package information ............................................................ 7
5 Revision history .............................................................................. 9
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STFW12N150K5
1 Electrical ratings
Symbol
Table 2: Absolute maximum ratings
Parameter
V
GS
I
D
Gate-source voltage
Drain current at T
C
= 25 °C
I
D
Drain current at T
C
= 100 °C
I
DM
(1)
Drain current (pulsed)
P
TOT
Total dissipation at T
C
= 25 °C
V iso
Insulation withstand voltage (RMS) from all three leads to external heat sink(t=1s; T
C
=25°C)
dv/dt
(2)
Peak diode recovery voltage slope
dv/dt
(3)
MOSFET dv/dt ruggedness
T j
T stg
Operating junction temperature
Storage temperature
Notes:
(1)
Pulse width limited by safe operating area
(2)
I
SD
≤ 7 A, di/dt ≤ 100 A/µs, V
Peak
≤ V
(BR)DSS
(3)
V
DS
≤ 1200V
Symbol
Table 3: Thermal data
Parameter
R thj-case
R thj-amb
Thermal resistance junction-case
Thermal resistance junction-amb
Symbol
I
AR
E
AS
Table 4: Avalanche characteristics
Parameter
Max current during repetitive or single pulse avalanche
Single pulse avalanche energy
Electrical ratings
Value
± 30
7
4.7
28
63
3500
750
50
Unit
V
A
A
A
W
V
V/ns
V/ns
- 55 to 150 °C
Value
1.98
50
Unit
°C/W
°C/W
Value Unit
2
900
A mJ
DocID027835 Rev 1 3/10
Electrical characteristics
2 Electrical characteristics
(T
CASE
= 25 °C unless otherwise specified)
Symbol Parameter
Table 5: On/off states
Test conditions
V
(BR)DSS
Drain-source breakdown voltage
V
GS
= 0 V, I
D
= 1 mA
I
DSS
Zero gate voltage drain current
V
GS
= 0 V, V
DS
= 1500 V
V
GS
= 0 V, V
DS
= 1500 V,
Tc=125 °C
I
GSS
Gate body leakage current
V
GS(th)
Gate threshold voltage
V
V
DS
DS
= 0 V,V
GS
= V
GS
, I
D
= ± 20 V
= 100 µA
R
DS(on)
Static drain-source on- resistance
V
GS
= 10 V, I
D
= 3.5 A
Symbol Parameter
Table 6: Dynamic
Test conditions
STFW12N150K5
Min. Typ. Max. Unit
1500
3 4
1
50
V
µA
µA
±10 µA
5 V
1.6 1.9 Ω
C
C
R
G
Q g
Q gs
Q iss
C oss rss gd
Input capacitance
Output capacitance
Reverse transfer capacitance
C
oss(eq)
(1)
Equivalent output capacitance,
V
V
GS
DS
= 0 V, V
DS
=100 V,f = 1MHz
= 0 V to 1200 V, V
GS
= 0 V
Intrinsic gate resistance f = 1 MHz, I
D
= 0 A
Total gate charge
Gate-source charge
Gate-drain charge
V
DD
= 1200V, I
V
GS
=10 V
D
= 7 A
(see Figure 3: "Gate charge test circuit" )
Min. Typ. Max. Unit
-
-
1360
85
-
- pF pF
-
-
-
-
-
-
0.74
186
3
47
8
32
-
-
-
-
-
- pF pF
Ω nC nC nC
Notes:
(1)
C oss (eq)
is defined as a constant equivalent capacitance giving the same charging time as C oss
when V
DS increases from 0 to 80% V
DSS
Symbol Parameter
Table 7: Switching times
Test conditions Min. Typ. Max. Unit t d(on) t r t d(off) t f
Turn-on delay time
Rise time
Turn-off delay time
Fall time
V
DD
= 750 V, I
D
= 3.5 A, R
G
=4.7 Ω V
GS
=10 V
(see Figure 2: "Switching times test circuit for resistive load" )
-
-
-
-
25
8
90
37
-
-
-
- ns ns ns ns
4/10 DocID027835 Rev 1
STFW12N150K5
Symbol
V
I
I
I
I
SDM
SD
(1)
t t
SD
Q
RRM
Q rr rr rr rr
RRM
Parameter
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
SD
Table 8: Source drain diode
= 7 A, V
Test conditions
GS
=0 V
I
SD
= 7 A, V
DD
= 60 V di/dt = 100 A/µs,
(see Figure 4: "Test circuit for inductive load switching and diode recovery times" )
I
SD
= 7 A,V
DD
= 60 V di/dt=100 A/µs,
Tj=150 °C
(see Figure 4: "Test circuit for inductive load switching and diode recovery times" )
Electrical characteristics
Min. Typ. Max. Unit
-
-
-
-
-
-
-
-
-
302
3.71
24.6
432
4.71
21.8
7
28
1.5
A
A
V ns
µC
A ns
µC
A
Notes:
(1)
Pulsed: pulse duration = 300µs, duty cycle 1.5%
Symbol
Table 9: Gate-source Zener diode
Parameter Test conditions
V(BR)GSO
Gate-source breakdown voltage I
GS
= ±1 mA, I
D
= 0 A
Min. Typ. Max. Unit
30 - V
The built-in back-to-back Zener diodes have been specifically designed to enhance the
ESD capability of the device. The Zener voltage is appropriate for efficient and costeffective intervention to protect the device integrity. These integrated Zener diodes thus eliminate the need for external components.
DocID027835 Rev 1 5/10
Test circuits
3 Test circuits
Figure 2: Switching times test circuit for resistive load
STFW12N150K5
Figure 3: Gate charge test circuit
Figure 4: Test circuit for inductive load switching and diode recovery times
Figure 5: Unclamped inductive load test circuit
Figure 6: Unclamped inductive waveform
Figure 7: Switching time waveform
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STFW12N150K5
4
4.1
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK
®
is an ST trademark.
TO-3PF package information
Figure 8: TO-3PF package outline
DocID027835 Rev 1
7627132_D
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Package information
Dim.
G1
H
L
L2
L3
L4
L5
L6
L7
N
R
Dia
E
F
F2
G
A
C
D
D1
15.30
9.80
22.80
26.30
43.20
4.30
24.30
14.60
1.80
3.80
3.40
Table 10: TO-3PF mechanical data mm
Min. Typ.
5.30
2.80
3.10
1.80
0.80
0.65
1.80
10.30
5.45
10
STFW12N150K5
Max.
5.70
3.20
3.50
2.20
1.10
0.95
2.20
11.50
15.70
10.20
23.20
26.70
44.40
4.70
24.70
15
2.20
4.20
3.80
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STFW12N150K5
5
Revision history
Revision history
Date
20-May-2015
Table 11: Document revision history
Revision
1
Changes
First release.
DocID027835 Rev 1 9/10
STFW12N150K5
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