STMicroelectronics VN5E160AS-E Datasheet

VN5E160AS-E

Single channel high side driver with analog for automotive applications

Features

Max supply voltage

Operating voltage range

V

CC

V

CC

41 V

4.5 V to 28 V

Max ON-state resistance

(per ch.)

R

ON

Current limitation (typ)

OFF-state supply current

I

LIMH

I

S

1.

Typical value with all loads connected.

160 m

10 A

2 µA

Ω

(1)

■

■

■

General

– Inrush current active management by power limitation

– Very low standby current

– 3.0 V CMOS compatible inputs

– Optimized electromagnetic emission

– Very low electromagnetic susceptibility

– In compliance with the 2002/95/EC european directive

– Very low current sense leakage

Diagnostic functions

– Proportional load current sense

– High-precision current sense for wide-range currents

– Current sense disable

– OFF-state open-load detection

– Output short to V

CC

detection

– Overload and short to ground

(power limitation) indication

Protections

– Undervoltage shutdown

– Overvoltage clamp

– Load current limitation

– Self-limiting of fast thermal transients

– Protection against loss of ground and loss of V

CC

– Overtemperature shutdown with autorestart (thermal shutdown)

September 2013 Doc ID 15609 Rev 4

62

("1($'5

– Reverse battery protected

– Electrostatic discharge protection

Application

■

■

All types of resistive, inductive and capacitive loads

Suitable as LED driver

Description

The VN5E160AS-E is a single-channel high-side driver manufactured in the ST proprietary

VIPower™ M0-5 technology and housed in the tiny SO-8 package. The VN5E160AS-E is designed to drive 12 V automotive grounded loads delivering protection, diagnostics and easy

3 V and 5 V CMOS compatible interface with any microcontroller.

The device integrates advanced protective functions such as load current limitation, inrush and overload active management by power limitation, overtemperature shut-off with auto-restart and overvoltage active clamp. A dedicated analog current sense pin is associated with every output channel in order to provide ehnanced diagnostic functions including fast detection of overload and short-circuit to ground through power limitation indication, overtemperature indication, short-circuit to V

CC diagnosis and ON & OFF state open-load detection. The current sensing and diagnostic feedback of the whole device can be disabled by pulling the CS_DIS pin high to allow sharing of the external sense resistor with other similar devices.

1/37 www.st.com

1

6

7

1

2

Contents

Contents

3

4

5

VN5E160AS-E

Block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.5

Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.1

GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 24

3.1.1

3.1.2

Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 24

Solution 2: a diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . 25

3.2

Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.3

MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.4

Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.4.1

Short to VCC and OFF-state open load detection . . . . . . . . . . . . . . . . . 27

3.5

Maximum demagnetization energy (VCC = 13.5 V) . . . . . . . . . . . . . . . . . 28

Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.1

SO-8 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.1

ECOPACK

®

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.2

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.3

Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2/37 Doc ID 15609 Rev 4

VN5E160AS-E

List of tables

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 5.

Table 6.

Table 7.

Table 8.

Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Switching (V

CC

= 13 V; Tj = 25 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Protection and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 9.

Current sense (8 V < V

CC

< 18 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 10.

Openload detection (8 V < V

CC

< 18 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 11.

Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 12.

Electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 13.

Electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 14.

Electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 15.

Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 16.

SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 17.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 18.

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Doc ID 15609 Rev 4 3/37

List of figures

List of figures

VN5E160AS-E

Figure 1.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2.

Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3.

Current and voltage conventions

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4.

Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 5.

OFF-state open-load delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 6.

Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 7.

Delay response time between rising edge of ouput current and rising edge of current sense (CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 8.

Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 9.

I

OUT

/I

SENSE

vs I

OUT

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 10.

Maximum current sense ratio drift vs load current

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 11.

Normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 12.

Overload or short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 13.

Intermittent overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 14.

OFF-state open-load with external circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 15.

Short to V

CC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 16.

T

J

evolution in overload or short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 17.

OFF-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 18.

High-level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 19.

Input voltage clamp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 20.

Low-level input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 21.

High-level input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 22.

Hysteresis input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 23.

ON-state resistance vs. T case

Figure 24.

ON-state resistance vs. V

CC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 25.

Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 26.

Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 27.

I

LIMH

vs. T case

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 28.

Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 29.

High-level CS_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 30.

CS_DIS voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 31.

Low-level CS_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 32.

Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 33.

Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 34.

Maximum turn-off current versus inductance (for each channel)

(1)

. . . . . . . . . . . . . . . . . . 28

Figure 35.

SO-8 PC board

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 36.

Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 29

Figure 37.

SO-8 thermal impedance junction ambient single pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 38.

Thermal fitting model of an HSD in SO-8

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 39.

SO-8 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 40.

SO-8 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 41.

SO-8 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4/37 Doc ID 15609 Rev 4

VN5E160AS-E

1

Block diagram and pin configuration

Block diagram and pin configuration

Figure 1.

Block diagram

6LJQDO&ODPS

8QGHUYROWDJH

,1

&6B

',6

&6

/2*,&

&RQWURO 'LDJQRVWLF

3RZHU

&ODPS

'5,9(5

9

21

/LPLWDWLRQ

2YHU

WHPSHUDWXUH

&XUUHQW

/LPLWDWLRQ

2))6WDWH

2SHQORDG

9

6(16(+

&XUUHQW

6HQVH

29(5/2$'3527(&7,21

$&7,9(32:(5/,0,7$7 ,21

9

&&

287

*1'

*$3*&)7

Table 1.

Name

Pin function

V

CC

OUT

GND

IN

CS

Function

Battery connection.

Power output.

Ground connection. Must be reverse battery protected by an external diode/resistor network.

Voltage-controlled input pin with hysteresis, CMOS compatible. Controls output switch state.

Analog current sense pin, delivers a current proportional to the load current.

CS_DIS Active high CMOS compatible pin, to disable the current sense pin.

Doc ID 15609 Rev 4 5/37

Block diagram and pin configuration

Figure 2.

Configuration diagram (top view)

9

&&

287

287

9

&&

62

&6B',6

&6

,1

*1'

*$3*&)7

VN5E160AS-E

Table 2.

Suggested connections for unused and not connected pins

Connection / pin Current sense N.C.

Output Input

Floating

To ground

Not allowed

Through 1 k Ω resistor

X

X

CS_DIS

X

Not allowed

X

Through 10 k Ω resistor

X

Through 10 k Ω resistor

6/37 Doc ID 15609 Rev 4

VN5E160AS-E Electrical specifications

Figure 3.

Current and voltage conventions

(1)

9

&6'

9

,1

,

&6'

,

,1

9

&&

&6B',6

,1

287

*1'

,

*1'

&6

,

6

9

)

,

287

,

6(16(

9

6(16(

9

287

9

&&

*$3*&)7

1.

V

F

= V

OUT

- V

CC

during reverse battery condition.

Stressing the device above the ratings listed in the “absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to the conditions in the “absolute maximum ratings” table for extended periods may affect device reliability. Refer also to the

STMicroelectronics SURE program and other relevant quality documents.

Table 3.

Symbol

Absolute maximum ratings

Parameter

V

CC

-V

CC

- I

GND

DC supply voltage

Reverse DC supply voltage

DC reverse ground pin current

I

OUT

- I

OUT

I

IN

I

CSD

DC output current

Reverse DC output current

DC input current

DC current sense disable input current

-I

CSENSE

DC reverse CS pin current

V

CSENSE

Current sense maximum voltage

Value Unit

41

0.3

200

V

V mA

Internally limited A

6 A

-1 to 10

-1 to 10 mA mA

200

V

CC

- 41

+V

CC mA

V

V

Doc ID 15609 Rev 4 7/37

Electrical specifications

Table 3.

Symbol

E

MAX

V

ESD

V

ESD

T j

T stg

Absolute maximum ratings (continued)

Parameter

Maximum switching energy (single pulse)

(L = 8 mH; R

L

= 0 Ω ; V bat

= 13.5 V; T jstart

= 150 °C;

I

OUT

= I limL

(Typ.) )

Electrostatic discharge

(human body model: R = 1.5 K

Ω;

C = 100 pF)

– IN

– CS

– CS_DIS

– OUT

– V

CC

Charge device model (CDM-AEC-Q100-011)

Junction operating temperature

Storage temperature

Table 4.

Symbol

Thermal data

Parameter

R thj-pins

R thj-amb

Thermal resistance junction-pins

Thermal resistance junction-ambient

VN5E160AS-E

Value

36

Unit mJ

4000

2000

4000

5000

5000

750

-40 to 150

-55 to 150

V

°C

°C

V

V

V

V

V

Max value

30

See Figure 36

Unit

°C/W

°C/W

8/37 Doc ID 15609 Rev 4

VN5E160AS-E Electrical specifications

Values specified in this section are for 8 V < V

CC otherwise stated.

< 28 V; -40 °C < Tj < 150 °C, unless

Table 5.

Symbol

Power section

Parameter

V

CC

V

USD

Operating supply voltage

Undervoltage shut-down

V

USDhyst

Undervoltage shut-down hysteresis

Test conditions

V

R clamp

I

Voltage clamp

I

L(off1)

OFF-state output current

V

ON

S

F

ON-state resistance

Supply current

Output - V

CC

diode voltage

1.

PowerMOS leakage included.

I

OUT

= 1 A, T j

= 25 °C

I

OUT

= 1 A, T j

= 150 °C

I

OUT

= 1 A, V

CC

= 5 V, T j

= 25 °C

I

S

= 20 mA

OFF-state: V

CC

= 13 V,

V

IN

= V

OUT

= 0 V, T j

= 25 °C

ON-state: V

IN

I

OUT

= 0 A

= 5 V, V

CC

= 13 V,

V

IN

T j

= V

OUT

= 25 °C

= 0 V, V

CC

= 13 V,

V

IN

T j

= V

OUT

= 125 °C

= 0 V, V

CC

= 13 V,

-I

OUT

= 1 A, T j

= 150 °C

Min. Typ. Max.

Unit

4.5

13 28

3.5

4.5

V

V

160

320

210

41 46 52 m

Ω

V

2

(1)

5

(1)

µA

0

0.5

V

1.9

3.5

mA

0 0.01

3

5

0.7

µA

V

Table 6.

Symbol

Switching (V

CC

= 13 V; T j

= 25 °C)

Parameter Test conditions t d(on) t d(off) dV

OUT

/dt

(on) dV

OUT

/dt

(off)

W

ON

W

OFF

Turn-on delay time

Turn-off delay time

R

L

= 13 Ω

(see

Figure 6

)

R

L

= 13

Ω

(see

Figure 6

)

Turn-on voltage slope R

L

= 13

Ω

Turn-off voltage slope R

L

= 13 Ω

Switching energy losses during t won

R

L

= 13 Ω

(see

Figure 6

)

Switching energy losses during t woff

R

L

= 13

Ω

(see

Figure 6

)

Min.

—

—

Typ.

10

0.03

Max.

Unit

— µs

— 10 — µs

—

See Figure 26

— V/µs

—

See Figure 28

— V/µs

— 0.05

— mJ

— mJ

Doc ID 15609 Rev 4 9/37

Electrical specifications VN5E160AS-E

Table 7.

Symbol

V

IL

I

IL

V

IH

I

IH

V

I(hyst)

V

ICL

V

CSDL

I

CSDL

V

CSDH

I

CSDH

V

CSD(hyst)

V

CSCL

Logic inputs

Parameter Test conditions

Low-level input voltage

Low-level input current

High-level input voltage

High-level input current

Hysteresis input voltage

V

V

IN

IN

= 0.9 V

= 2.1 V

Input voltage clamp

I

IN

= 1 mA

I

IN

= -1 mA

Low-level CS_DIS voltage

Low-level CS_DIS current V

CSD

= 0.9 V

High-level CS_DIS voltage

High-level CS_DIS current V

CSD

= 2.1 V

Hysteresis CS_DIS voltage

CS_DIS voltage clamp

I

CSD

= 1 mA

I

CSD

= -1 mA

Min.

Typ.

Max.

Unit

0.9

1

2.1

0.25

5.5

10

7

V

µA

V

µA

V

V

-0.7

1

2.1

0.25

5.5

0.9

10

7

V

µA

V

µA

V

V

-0.7

Table 8.

Symbol

Protection and diagnostics

(1)

Parameter Test conditions Min.

Typ.

Max.

Unit

I

I

T limH limL

TSD

DC short-circuit current

V

CC

= 13 V

5 V < V

CC

< 28 V

Short-circuit current during thermal cycling

V

CC

= 13 V

T

R

< T j

< T

TSD

Shutdown temperature

Reset temperature T

R

T

RS

Thermal reset of

STATUS

T

HYST

V

DEMAG

Thermal hysteresis

(T

TSD

- T

R

)

Turn-off output voltage clamp

I

OUT

= 1 A, V

L = 20 mH

IN

= 0,

T

V

150

RS

135

CC

7

+ 1 T

10

2.5

175

RS

- 41 V

CC

7

+ 5

14

14

200

- 46 V

CC

- 52

V

ON

Output voltage drop limitation

I

OUT

= 0.03 A (see Figure 8 )

T j

= -40 °C to +150 °C

25

1.

To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles.

A

A

A

°C

°C

°C

°C

V mV

10/37 Doc ID 15609 Rev 4

VN5E160AS-E Electrical specifications

Table 9.

Symbol

Current sense (8 V < V

CC

< 18 V)

Parameter Test conditions Min.

Typ.

Max.

Unit dK dK dK

K

K

1

/K

K

2

/K

K

0

1

2

3

3

/K

1

(1)

2

(1)

3

(1)

I

OUT

I

OUT

/I

/I

SENSE

SENSE

Current sense ratio drift

I

OUT

Current sense ratio drift

I

OUT

/I

/I

SENSE

SENSE

Current sense ratio drift

I

OUT

= 0.025 A, V

SENSE

= 0.5 V

T j

= -40 °C to 150 °C

I

OUT

= 0.35 A, V

SENSE

= 0.5 V

T j

= -40 °C to 150 °C

T j

= 25 °C to 150 °C

I

OUT

=0.35 A, V

SENSE

= 0.5 V

T j

= -40 °C to 150 °C

I

OUT

= 0.5 A, V

SENSE

= 4 V

T j

= -40 °C to 150 °C

T j

= 25 °C to 150 °C

I

OUT

= 0.5 A;

T j

= -40 °C to 150 °C

I

OUT

= 1.5 A, V

SENSE

= 4 V

T j

= -40 °C to 150 °C

T j

= 25 °C to 150 °C

I

OUT

= 1.5 A;

T j

= -40 °C to 150 °C

I

OUT

= 0 A, V

SENSE

= 0 V,

V

CSD

= 5 V, V

IN

= 0 V,

T j

= -40 °C to 150 °C

I

SENSE0

V

SENSE

Analog sense leakage current

Max analog sense output voltage

I

OUT

= 0 A, V

SENSE

= 0 V,

V

CSD

= 0 V, V

IN

= 5 V,

T j

= -40 °C to 150 °C

I

OUT

= 1 A, V

SENSE

= 0 V,

V

CSD

= 5 V, V

IN

= 5 V,

T j

= -40 °C to 150 °C

R

SENSE

= 10 K

Ω

I

OUT

= 1 A;

V

SENSEH

(2)

Analog sense output voltage in fault condition

V

CC

= 13 V, R

SENSE

= 3.9 K Ω t

I

SENSEH

(2)

Analog sense output current in fault condition

V

CC

= 13 V, V

SENSE

= 5 V t

DSENSE1H

DSENSE1L

Delay response time from falling edge of

CS_DIS pin

Delay response time from rising edge of

CS_DIS pin

V

SENSE

< 4 V,

0.025 A < I

OUT

< 1.5 A

I

SENSE

= 90% of I

SENSE max

(see Figure 4 )

V

SENSE

< 4 V,

0.025 A < I

OUT

< 1.5 A

I

SENSE

= 10% of I

SENSE max

(see Figure 4 )

265 490 715

355

385

-11

380

400

-8

420

420

-4

0

0

0

5

465

465

455

455

455

455

8

9

40

5

575

545

+11

530

510

+8

490

480

+4

1

2

1

100

20

%

%

%

µA

V

V mA

µs

µs

Doc ID 15609 Rev 4 11/37

Electrical specifications VN5E160AS-E

Table 9.

Symbol

Current sense (8 V < V

CC

< 18 V) (continued)

Parameter Test conditions Min.

Typ.

Max.

Unit t

DSENSE2H

Delay response time from rising edge of IN pin

V

SENSE

< 4 V,

0.025 A < I

OUT

< 1.5 A

I

SENSE

=90% of I

SENSE max

(see Figure 4 )

Δ t

DSENSE2H

Delay response time between rising edge of output current and rising edge of current sense

V

SENSE

< 4 V,

I

SENSE

= 90% of I

SENSEMAX,

I

OUT

= 90% of I

OUTMAX

I

OUTMAX

=1.5A (see

Figure 7

) t

DSENSE2L

Delay response time from falling edge of IN pin

V

SENSE

< 4 V,

0.025 A < I

OUT

< 1.5 A

I

SENSE

=10% of I

SENSE max

(see Figure 4 )

30 160

110

80 250

1.

Parameter guaranteed by design; it is not tested.

2.

Fault condition includes: power limitation, overtemperature and open load OFF-state detection.

µs

µs

µs

Table 10.

Openload detection (8 V < V

CC

< 18 V)

Symbol Parameter Test conditions

V

I

OL

OL t

DSTKON

I

I

L(off2)r

L(off2)f td_vol

OFF-state open-load voltage detection threshold

ON-state open-load current detection threshold

I

V

V

IN

IN

= 0 V, 8 V < V

= 5V, 8 V < V

SENSE

= 5 µA

CC

CC

< 18 V

< 18 V

Output short-circuit to V

CC detection delay at turn-off

See Figure 5

OFF-state output current at V

OUT

= 4 V

OFF-state output current at V

OUT

= 2 V

Delay response from output rising edge to

V

SENSE rising edge in open-load

V

IN

= 0 V, V

SENSE

= 0 V

V

OUT rising from 0 V to 4 V

V

IN

= 0 V, V

SENSE

= V

SENSEH

V

OUT falling from V

CC

to 2 V

V

OUT

= 4 V, V

V

SENSE

IN

= 0 V

= 90% of V

SENSEH

Min.

Typ.

Max.

Unit

2

0.5

180

-120

-50

4

5

V mA

1200 µs

0

90

20

µA

µs

12/37 Doc ID 15609 Rev 4

VN5E160AS-E

Figure 4.

Current sense delay characteristics

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OFF-state open-load delay timing

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Switching characteristics

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Doc ID 15609 Rev 4 13/37

Electrical specifications VN5E160AS-E

Figure 7.

Delay response time between rising edge of ouput current and rising edge of current sense (CS enabled)

9

,1 ǻW

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Output voltage drop limitation

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14/37 Doc ID 15609 Rev 4

VN5E160AS-E

Figure 9.

I

OUT

/I

SENSE

vs I

OUT

I

OUT

/I

SEN SE

620

590

560

530

A

B

500

470

440

C

410

380

350

320

0 0.2

D

0.4

E

0.6

0.8

I

OUT

(A)

1

Electrical specifications

1.2

1.4

1.6

1.8

A: Max, T j

= -40 °C to 150 °C

B: Max, T j

= 25 °C to 150 °C

C: Typical, T j

= -40 °C to 150 °C

D: Min, T j

= 25 °C to 150 °C

E: Min, T j

= -40 °C to 150 °C

Figure 10.

Maximum current sense ratio drift vs load current

(1)

0

-3

-6

-9

6

3 dK/K (%)

15

12

9

-12

-15

0 0.2

0.4

B

A

0.6

0.8

I

OUT

(A)

1 1.2

1.4

1.6

1.8

A: Max, T j

= -40 °C to 150 °C

1.

Parameter guaranteed by design; it is not tested.

B: Min, T j

= 25 °C to 150 °C

Doc ID 15609 Rev 4 15/37

Electrical specifications VN5E160AS-E

Table 11.

Truth table

Conditions

Normal operation

Overtemperature

Undervoltage

Overload

IN

L

H

L

H

L

H

H

H

OUT

L

L

L

H

L

L

X

(no power limitation)

Cycling

(power limitation)

L

L

SENSE (V

CSD

= 0 V)

(1)

0

Nominal

0

V

SENSEH

0

0

Nominal

V

SENSEH

Short circuit to GND

(Power limitation)

OFF-state open-load

(with external pull-up)

L

H

L H

V

V

0

SENSEH

SENSEH

1.

If the V

CSD

is high, the SENSE output is at a high impedance, its potential depends on leakage currents and external circuit.

16/37 Doc ID 15609 Rev 4

VN5E160AS-E Electrical specifications

Table 12.

Electrical transient requirements (part 1)

Test levels

(1)

ISO 7637-2:

2004(E)

Test pulse

III IV

Number of pulses or test times

Burst cycle/pulse repetition time

1

2a

3a

3b

-75 V

+37 V

-100 V

+75 V

-100 V

+50 V

-150 V

+100 V

5000 pulses

5000 pulses

1h

1h

0.5 s

0.2 s

90 ms

90 ms

5 s

5 s

100 ms

100 ms

4

5b

(2)

-6 V

+65 V

-7 V

+87 V

1 pulse

1 pulse

Delays and

Impedance

2 ms, 10 Ω

50 µs, 2 Ω

0.1 µs, 50 Ω

0.1 µs, 50 Ω

100 ms,

0.01

Ω

400 ms, 2 Ω

Table 13.

Electrical transient requirements (part 2)

Test level results

(1)

ISO 7637-2:

2004(E)

Test pulse III IV

1

2a

3a

3b

4

5b

(2)

C

C

C

C

C

C

1.

The above test levels must be considered referred to V

CC

= 13.5 V except for pulse 5b

2.

Valid in case of external load dump clamp: 40 V maximum referred to ground.

Table 14.

Electrical transient requirements (part 3)

Class Contents

C

C

C

C

C

C

C

E

All functions of the device are performed as designed after exposure to disturbance.

One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.

Doc ID 15609 Rev 4 17/37

Electrical specifications

2.4 Waveforms

Figure 11.

Normal operation

1RUPDORSHUDWLRQ

VN5E160AS-E

18/37

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Figure 12.

Overload or short to GND

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VN5E160AS-E

Figure 13.

Intermittent overload

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Electrical specifications

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OFF-state open-load with external circuitry

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19/37

Electrical specifications

Figure 15.

Short to V

CC

5HVLVWLYH

6KRUWWR9

&&

6KRUWWR9

&&

+DUG

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VN5E160AS-E

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T

J

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Doc ID 15609 Rev 4

VN5E160AS-E Electrical specifications

Figure 17.

OFF-state output current

,ORII>Q$@

Figure 18.

High-level input current

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Low-level input voltage

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Figure 21.

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7F> ƒ&@

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Figure 22.

Hysteresis input voltage

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Doc ID 15609 Rev 4

7F> ƒ&@

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21/37

Electrical specifications VN5E160AS-E

Figure 23.

ON-state resistance vs. T case

Figure 24.

ON-state resistance vs. V

CC

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Undervoltage shutdown

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Turn-on voltage slope

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Turn-off voltage slope

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VN5E160AS-E Electrical specifications

Figure 29.

High-level CS_DIS voltage Figure 30.

CS_DIS voltage clamp

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Low-level CS_DIS voltage

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Doc ID 15609 Rev 4 23/37

Application information VN5E160AS-E

Figure 32.

Application schematic

9

P &

5

SURW &6B',6

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H[W

5

SURW

5

SURW

,1

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5

6(16(

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3.1

3.1.1

GND protection network against reverse battery

Solution 1: resistor in the ground line (R

GND

only)

This can be used with any type of load.

The following is an indication on how to dimension the R

GND resistor.

1.

R

GND

≤ 600 mV / (I

S(on)max

).

2. R

GND

≥ (−

V

CC

) / (-I

GND

) where -I

GND

is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet.

Power dissipation in R

GND

(when V

CC

< 0: during reverse battery situations) is:

Equation 1

P

D

= (-V

CC

)

2

/ R

GND

This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where I

S(on)max

becomes the sum of the maximum ON-state currents of the different devices.

Please note that if the microprocessor ground is not shared by the device ground then the

R

GND produces a shift (I

S(on)max

* R

GND

) in the input thresholds and the status output

24/37 Doc ID 15609 Rev 4

VN5E160AS-E

3.1.2

Application information values. This shift varies depending on how many devices are ON in the case of several highside drivers sharing the same R

GND

.

If the calculated power dissipation leads to a large resistor or several devices have to share

the same resistor then ST suggests to utilize Solution 2 (see Section 3.1.2: Solution 2: a diode (DGND) in the ground line ).

Solution 2: a diode (D

GND

) in the ground line

A resistor (R

GND

= 1 k

Ω) should be inserted in parallel to D inductive load.

GND

if the device drives an

This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network produces a shift (

≈

600 mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift not varies if more than one HSD shares the same diode/resistor network.

3.2 Load dump protection

D ld

is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the

V

CC

max DC rating. The same applies if the device is subject to transients on the V

CC

line that are greater than the ones shown in the ISO T/R 7637/1 table.

3.3 MCU I/Os protection

If a ground protection network is used and negative transients are present on the V

CC

line, the control pins is pulled negative. ST suggests to insert a resistor (R prot

) in line to prevent the microcontroller I/O pins to latch-up.

The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (input levels compatibility) with the latch-up limit of microcontroller I/Os.

Equation 2

-V

CCpeak

/ I latchup

≤

R prot

≤

(V

OH

μ

C

- V

IH

- V

GND

) / I

IHmax

Calculation example:

For V

CCpeak

= - 100 V, I latchup

≥

20 mA, V

OH

μ

C

≥

4.5 V

5 k Ω ≤ R prot

≤ 180 k Ω .

Recommended values: R prot

=10 k Ω, C

EXT

= 10 nF.

Doc ID 15609 Rev 4 25/37

Application information

3.4

VN5E160AS-E

Current sense and diagnostic

The current sense pin performs a double function (see

Figure 33: Current sense and diagnostic

):

● Current mirror of the load current in normal operation, delivering a current proportional to the load one according to a known ratio K

X

.

The current I

SENSE

can be easily converted to a voltage V

SENSE

by means of an external resistor R

SENSE

. Linearity between I

OUT

and V

SENSE

is ensured up to 5 V minimum (see parameter V

SENSE

in Table 9: Current sense (8 V < V

CC

< 18 V)

). The current sense accuracy depends on the output current (refer to current sense electrical characteristics

Table 9: Current sense (8 V < V

CC

< 18 V) ).

● Diagnostic flag in fault conditions, delivering a fixed voltage V

SENSEH

up to a maximum current I

SENSEH

in case of the following fault conditions (refer to

Truth table

):

– Power limitation activation

– Overtemperature

– Short to V

CC

in OFF-state

– Open-load in OFF-state with additional external components.

A logic high-level on CS_DIS pin sets at the same time all the current sense pins of the devices in a high-impedance-state, thus disabling the current monitoring and diagnostic detection. This feature allows multiplexing of the microcontroller analog inputs by sharing of sense resistance and ADC line among different devices.

Figure 33.

Current sense and diagnostic

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26/37 Doc ID 15609 Rev 4

VN5E160AS-E

3.4.1

Application information

Short to V

CC

and OFF-state open load detection

Short to V

CC

A short-circuit between V

CC and output is indicated by the relevant current sense pin set to

V

SENSEH

during the device OFF-state. Small or no current is delivered by the current sense during the ON-state depending on the nature of the short-circuit.

OFF-state open-load with external circuitry

Detection of an open-load in off-mode requires an external pull-up resistor R

PU

connecting the output to a positive supply voltage V

PU

.

It is preferable V

PU

to be switched-off during the module standby-mode in order to avoid the overall standby current consumption to increase in normal conditions, i.e. when load is connected.

An external pull-down resistor R

PD

connected between output and GND is mandatory to avoid misdetection in case of floating outputs in OFF-state (see

Figure 33: Current sense and diagnostic

).

R

PD

must be selected in order to ensure V circuitry:

OUT

< V

OLmin

unless pulled up by the external

Equation 3

V

OUT

Pull

− up _ OFF

=

R

PD

⋅

I

L ( off 2 ) f

<

V

OL min

=

2 V

R

PD

≤ 22 K Ω is recommended.

For proper open load detection in OFF-state, the external pull-up resistor must be selected according to the following formula:

Equation 4

V

OUT

Pull − up _ ON

=

(

R

PD

⋅

V

PU

(

)

−

R

PU

(

R

PU

+

⋅

R

PD

R

PD

)

⋅

I

L ( off 2 ) r

)

>

V

OL max

=

4 V

For the values of V

OLmin

,V

OLmax

, I

L(off2)r and I

L(off2)f

(see Table 10: Openload detection (8 V

< V

CC

< 18 V)

.

Doc ID 15609 Rev 4 27/37

Application information

3.5 Maximum demagnetization energy (V

CC

= 13.5 V)

VN5E160AS-E

Figure 34.

Maximum turn-off current versus inductance (for each channel)

(1)

A

C

B

/P+

*$3*&)7

A: T jstart

= 150 °C single pulse

B: T jstart

= 100 °C repetitive pulse

C: T jstart

= 125 °C repetitive pulse

9

,1

,

/

'HPDJQHWL]DWLRQ 'HPDJQHWL]DWLRQ 'HPDJQHWL]DWLRQ

*$3*&)7

W

1.

Values are generated with R

L

= 0

Ω.

In case of repetitive pulses, T jstart

(at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B.

28/37 Doc ID 15609 Rev 4

VN5E160AS-E

4 Package and PCB thermal data

Package and PCB thermal data

Figure 35.

SO-8 PC board

(1)

("1($'5

1.

Layout condition of R th

and Z th

measurements (PCB: FR4 area = 4.8 mm x 4.8 mm,

PCB thickness = 2 mm, Cu thickness = 35 µm, Copper areas: from minimum pad lay-out to 2 cm

2

).

Figure 36.

R thj-amb

vs PCB copper area in open box free air condition

RTHj_amb(°C/W)

110

100

90

80

70

60

0 0.5

1 1.5

PCB Cu heatsink area (cm^2)

2 2.5

Doc ID 15609 Rev 4 29/37

Package and PCB thermal data

Figure 37.

SO-8 thermal impedance junction ambient single pulse

ZTH (°C/W)

1000

VN5E160AS-E

100

Footprint

2 cm

2

10

1

0.1

0.0001

0.001

0.01

0.1

Time (s)

1 10

Equation 5: pulse calculation formula

Z

TH δ = R

TH

⋅ δ

+ Z

THtp

( 1 –

δ ) where δ = t

P

/T

Figure 38.

Thermal fitting model of an HSD in SO-8

(1)

100 1000

30/37

*$3*&)7

1.

The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered.

Doc ID 15609 Rev 4

VN5E160AS-E

Table 15.

Thermal parameters

Area/island (cm

2

)

R1 (°C/W)

R2 (°C/W)

R3 (°C/W)

R4 (°C/W)

R5 (°C/W)

R6 (°C/W)

C1 (W.s/°C)

C2 (W.s/°C)

C3 (W.s/°C)

C4 (W.s/°C)

C5 (W.s/°C)

C6 (W.s/°C)

Footprint

1.2

6

3.5

21

16

58

0.0008

0.0016

0.0075

0.045

0.35

1.05

Package and PCB thermal data

2

28

25

Doc ID 15609 Rev 4 31/37

32/37

Package and packing information

5 Package and packing information

VN5E160AS-E

5.1 ECOPACK

®

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK

® specifications, grade definitions and product status are available at: www.st.com

.

ECOPACK

®

is an ST trademark.

Figure 39.

SO-8 package dimensions

/

F

E

H

'

H

0

6

(

("1($'5

Doc ID 15609 Rev 4

VN5E160AS-E

Table 16.

SO-8 mechanical data

Dim.

Min.

F

L e e3 c1

D

E

M

S

L1

A a1 a2 a3 b b1

C

0.1

4.8

5.8

3.8

0.4

0.8

0.65

0.35

0.19

0.25

Package and packing information mm.

Typ.

45 (typ.)

Max.

1.75

0.25

1.65

0.85

0.48

0.25

0.5

5

6.2

1.27

3.81

8 (max.)

4

1.27

0.6

1.2

Doc ID 15609 Rev 4 33/37

Package and packing information VN5E160AS-E

Figure 40.

SO-8 tube shipment (no suffix)

%

&

$

Base q.ty

Bulk q.ty

Tube length (± 0.5)

A

B

C (± 0.1)

All dimensions are in mm.

("1($'5

100

2000

532

3.2

6

0.6

Figure 41.

SO-8 tape and reel shipment (suffix “TR”)

%DVHTW\

%XONTW\

$PD[

%PLQ

&“

)

*

1PLQ

7PD[

$OOGLPHQVLRQVDUHLQPP

7$3(',0(16,216

$FFRUGLQJWR(OHFWURQLF,QGXVWULHV$VVRFLDWLRQ

(,$6WDQGDUGUHY$)HE

7DSHZLGWK

7DSHKROHVSDFLQJ

&RPSRQHQWVSDFLQJ

+ROHGLDPHWHU

+ROHGLDPHWHU

+ROHSRVLWLRQ

&RPSDUWPHQWGHSWK

+ROHVSDFLQJ

:

3“

3

'

'PLQ

)“

.PD[

3“

$OOGLPHQVLRQVDUHLQPP

(QG

7R S

FRYHU

WDSH

1RFRPSRQHQWV &RPSRQHQWV

PPPLQ

(PSW\FRPSRQHQWVSRFNHWV

PPPLQ

VDOHGZLWKFRYHUWDSH

6WDUW

1RFRPSRQHQWV

8VHUGLUHFWLRQRIIHHG

*$3*&)7

34/37 Doc ID 15609 Rev 4

VN5E160AS-E Order codes

Table 17.

Device summary

Package

SO-8

Tube

VN5E160AS-E

Order codes

Tape and reel

VN5E160ASTR-E

Doc ID 15609 Rev 4 35/37

Revision history VN5E160AS-E

Table 18.

Document revision history

Date Revision

28-Apr-2009

25-Jan-2010

25-May-2011

18-Sep-2013

1

2

3

4

Changes

Initial release.

Updated

Table 10: Openload detection (8 V < V

CC

< 18 V) .

Table 9: Current sense (8 V < V

CC

< 18 V)

:

– t

DSENSE2H

: updated typical and maximum values

Updated Disclaimer.

36/37 Doc ID 15609 Rev 4

VN5E160AS-E

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Doc ID 15609 Rev 4 37/37