STS7P4LLF6
Datasheet
P-channel 40 V, 17.5 mΩ typ., 7 A, STripFET F6 Power MOSFET in an SO-8 package
G(4)
8
5
1
SO-8
4
D(5, 6, 7, 8)
S(1, 2, 3)
AM01475v4
Features
Order code
STS7P4LLF6
• Very low on-resistance
• Very low gate charge
• High avalanche ruggedness
• Low gate drive power loss
V
DS
40 V
R
DS(on)
max.
20.5 mΩ
I
D
7 A
Applications
• Switching applications
Description
This device is a P-channel Power MOSFET developed using the STripFET F6 technology, with a new trench gate structure. The resulting Power MOSFET exhibits very low R
DS(on)
in all packages.
Product status link
STS7P4LLF6
Product summary
Order code STS7P4LLF6
Marking
Package
Packing
7K4L
SO-8
Tape and reel
Note: For the P-channel Power MOSFET, current polarity of voltages and current have to be reversed.
DS10067 - Rev 3 - February 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
1
Note:
STS7P4LLF6
Electrical ratings
Electrical ratings
Table 1. Absolute maximum ratings
Symbol
V
DS
V
GS
Drain-source voltage
Gate-source voltage
Parameter
I
D
Drain current (continuous) at T amb
= 25 °C
Drain current (continuous) at T amb
= 100 °C
Drain current (pulsed) I
DM
(1)
P
TOT
T stg
T
J
Total power dissipation at T
Storage temperature range amb
Maximum junction temperature
1. Pulse width limited by safe operating area.
= 25 °C
Table 2. Thermal data
Symbol
R thJA
(1)
Parameter
Thermal resistance, junction-to-ambient
1. When mounted on 1 inch² FR-4 board, 2 oz. Cu., t ≤ 10 s.
Value
47
For the P-channel Power MOSFET, current polarity of voltages and current have to be reversed.
Value
40
±20
7
4.2
28
2.7
-55 to 150
150
Unit
°C/W
Unit
V
V
A
A
W
°C
°C
DS10067 - Rev 3 page 2/14
2
Note:
STS7P4LLF6
Electrical characteristics
Electrical characteristics
T
C
= 25 °C unless otherwise specified.
Symbol
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Table 3. Static
Parameter
Static drain-source on-resistance
Test conditions
Drain-source breakdown voltage V
GS
= 0 V, I
D
= 250 µA
V
GS
= 0 V, V
DS
= 40 V
Zero gate voltage Drain current
V
GS
= 0 V, V
DS
= 40 V, T
C
= 125 °C
Gate-body leakage current
Gate threshold voltage
V
DS
= 0 V, V
GS
= ±20 V
V
DS
= V
GS
, I
D
= 250 µA
V
GS
= 10 V, I
D
= 3.5 A
V
GS
= 4.5 V, I
D
= 3.5 A
Min.
Typ.
Max.
Unit
40 V
1
10
µA
µA
1
±100 nA
V
17.5
20.5
20.5
29.0
mΩ
Symbol
C iss
C oss
C rss
Q g
Q gs
Q gd
R
G
Parameter
Input capacitance
Output capacitance
Reverse transfer capacitance
Total gate charge
Gate-source charge
Gate-drain charge
Gate input resistance
V
Table 4. Dynamic
DS
Test conditions
= 25 V, f = 1 MHz, V
GS
= 0 V
V
DD
= 20 V, I
D
= 7 A, V
GS
= 4.5 V
(see
Figure 13. Gate charge test circuit
)
I
D
= 0 A, gate DC bias = 0 V, f = 1 MHz, magnitude of alternative signal = 20 mV
Min.
Typ.
Max.
Unit
2850 pF
-
-
-
270
180
22
-
-
pF pF nC
-
9.4
7.3
-
nC nC
1.4
Ω
Symbol t d(on) t r t d(off) t f
Parameter
Turn-on delay time
Rise time
Turn-off-delay time
Fall time
Table 5. Switching times
Test conditions
V
DD
= 20 V, I
D
= 3.5 A,
R
G
= 4.7 Ω, V
GS
= 10 V
(see
Figure 12. Switching times test circuit for resistive load )
Min.
Typ.
Max.
Unit
43 ns
47 ns
-
148
19 -
ns ns
For the P-channel Power MOSFET, current polarity of voltages and current have to be reversed.
DS10067 - Rev 3 page 3/14
Note:
STS7P4LLF6
Electrical characteristics
Table 6. Source drain diode
Symbol
V
SD
(1)
t rr
I
Q rr
RRM
Parameter
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Test conditions
V
GS
= 0 V, I
SD
= 3.5 A
I
SD
= 3.5 A, di/dt = 100 A/µs,
V
DD
= 32 V, T
J
= 150 °C
(see
Figure 14. Test circuit for inductive load switching and diode recovery times )
1. Pulse test: pulse duration = 300 µs, duty cycle 1.5%
Min.
Typ.
Max.
Unit
1.1
V
-
26
21 ns nC
1.7
A
For the P-channel Power MOSFET, current polarity of voltages and current have to be reversed.
DS10067 - Rev 3 page 4/14
STS7P4LLF6
Electrical characteristics (curves)
2.1
Electrical characteristics (curves)
I
D
(A)
Figure 1. Safe operating area
GIPG230220151406ALS
10 1
Operation limited
in
this area is
max. R
DS(on)
by
100 μs
1 ms
10 ms
10 0
10 -1
10 -1
T j
≤ 150 °C
T amb
= 25 °C single pulse
10 0 10 1
V
DS
(V)
I
D
(A)
Figure 3. Output characteristics
V
GS
GIPG230220151029ALS
= 10, 9, 8 V
150 V
GS
= 7 V
V
GS
= 6 V
120
90
V
GS
= 5 V
60
V
GS
= 4V
30
0
0 2 4 6
V
GS
= 3V
8 V
DS
(V)
Figure 5. Normalized gate threshold voltage vs temperature
V
GS(th)
(norm.)
GIPG230220150952ALS
1.10
1.00
0.90
0.80
0.70
0.60
-75 -25 25 75 125 T j
(°C)
K
Figure 2. Thermal impedance
GIPG100320151651ALS
10 -1
10 -2 amb
10 -3
10 -4 10 -3 10 -2 10 -1 10 0 t p
(s)
90
60
30
0
0
I
D
(A)
Figure 4. Transfer characteristics
GIPG230220151043ALS
150
V
DS
= 9 V
120
2 4 6 8 V
GS
(V)
Figure 6. Normalized V
(BR)DSS
vs temperature
V
(BR)DSS
(norm.)
GIPG230220150822ALS
1.08
1.04
I
D
= 1 mA
1.00
0.96
0.92
-75 -25 25 75 125 T j
°C
DS10067 - Rev 3 page 5/14
STS7P4LLF6
Electrical characteristics (curves)
Figure 7. Static drain-source on-resistance
R
DS(on)
(mΩ)
GIPG230220151353ALS
18.5
18.0
V
GS
= 10 V
17.5
17.0
16.5
16.0
0 2 4 6 I
D
(A)
Figure 8. Normalized on-resistance vs. temperature
R
DS(on)
(norm.)
1.6
GIPG230220151002ALS
1.4
1.2
1.0
0.8
V
GS
= 10 V
0.6
0.4
-75 -25 25 75 125 T j
(C)
Figure 9. Gate charge vs gate-source voltage
V
GS
(V)
GIPG100320151657ALS
12
6
4
10
8
2
0
0 10 20
V
DD
= 20 V
I
D
= 7 A
30 40 50 Qg (nC )
Figure 10.
C
(pF)
10 3
Capacitance variations voltage f = 1 MHz
10 2
0 8 16 24 32 40
C oss
C rss
V
DS
(V)
Figure 11. Source-drain diode forward characteristics
V
SD
(V)
GIPG230220151016ALS
1.0
T j
= -55 °C
T j
= 25°C
T j
= 175°C
0.8
GIPG230220151808ALS
C iss
0.6
0.4
5 10 15 20 25 30 35 I
SD
(A)
DS10067 - Rev 3 page 6/14
STS7P4LLF6
Test circuits
3
Test circuits
Figure 12. Switching times test circuit for resistive load Figure 13. Gate charge test circuit
Figure 14. Test circuit for inductive load switching and diode recovery times
DS10067 - Rev 3 page 7/14
4
4.1
STS7P4LLF6
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
SO-8 package information
Figure 15. SO-8 package outline
DS10067 - Rev 3
0016023_So-807_fig2_Rev10 page 8/14
DS10067 - Rev 3
STS7P4LLF6
SO-8 package information
Dim.
c c1
D
E
E1
A
A1
A2 b b1
L1
L2 k ccc e h
L
Table 7. SO-8 mechanical data
Min.
mm
Typ.
0.10
0.10
4.80
5.80
3.80
0.10
1.25
0.31
0.28
0.25
0.40
4.90
6.00
3.90
1.27
1.04
0.25
0°
Figure 16. SO-8 recommended footprint (dimensions are in mm)
Max.
1.75
0.25
0.51
0.48
0.25
0.23
5.00
6.20
4.00
0.50
1.27
8°
0.10
0016023_So-807_footprint_Rev10 page 9/14
4.2
SO-8 packing information
Figure 17. SO-8 tape and reel dimensions
STS7P4LLF6
SO-8 packing information
A D N
Bo
Ko
T
Po
Ao P
Figure 18. Tape orientation
0016023_SO-8_O7_T_R
DS10067 - Rev 3 page 10/14
Dim.
Ao
Bo
Ko
Po
P
A
C
D
N
T
STS7P4LLF6
SO-8 packing information
Table 8. SO-8 tape and reel mechanical data
Min.
mm
Typ.
12.8
20.2
60
6.5
5.4
2.0
3.9
7.9
-
Max.
330
13.2
22.4
6.7
5.6
2.2
4.1
8.1
DS10067 - Rev 3 page 11/14
Revision history
Date
10-Dec-2013
10-Mar-2015
17-Feb-2021
Version
1
2
3
Table 9. Document revision history
Changes
First revision.
Text edits throughout document
On cover page, updated title, description and features table
Updated and renamed Table 4: Static
Updated Table 5: Dynamic
Updated Table 6: Switching times
Updated Table 7: Source-drain diode
Added Section 2.1: Electrical characteristics (curves)
Minor text changes.
Updated Internal schematic .
Updated Section 4.2 SO-8 packing information .
Minor text changes.
STS7P4LLF6
DS10067 - Rev 3 page 12/14
STS7P4LLF6
Contents
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4.1
SO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2
SO-8 packing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
DS10067 - Rev 3 page 13/14
STS7P4LLF6
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DS10067 - Rev 3 page 14/14
