STL40N75LF3
N-channel 75 V, 16 m Ω typ., 10 A STripFET™ III Power MOSFET
in a PowerFLAT™ 5x6 package
Datasheet
-
production data
1
2
3
4
PowerFLAT™ 5x6
Features
Order code
STL40N75LF3
V
DSS
75 V
R
DS(on) max.
19 m Ω
•
N-channel enhancement mode
•
Low gate charge
•
Low threshold voltage device
I
D
10 A
G(4)
Figure 1. Internal schematic diagram
D(5, 6, 7, 8)
8 7 6 5
S(1, 2, 3)
Order code
STL40N75LF3
Applications
• Switching applications
Description
This device is an N-channel enhancement mode
Power MOSFET produced using
STMicroelectronics’ STripFET™ III technology, which is specifically designed to minimize onresistance and gate charge to provide superior switching performance.
1 2 3 4
Top View
AM15540v2
Marking
Table 1. Device summary
Package
40N75LF3 PowerFLAT™ 5x6
Packaging
Tape and reel
February 2014
This is information on a product in full production.
DocID023810 Rev 2 1/14 www.st.com
5
6
3
4
1
2
Contents
Contents
STL40N75LF3
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Packaging information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2/14 DocID023810 Rev 2
STL40N75LF3 Electrical ratings
Symbol
Table 2. Absolute maximum ratings
Parameter
V
DS
V
GS
I
D
(1)
I
D
(1)
I
DM
(1)(2)
I
D
(3)
I
D
(3)
P
TOT
(1)
P
TOT
(3)
T
J
T stg
Drain-source voltage
Gate-source voltage
Drain current (continuous) at T
Drain current (continuous) at T
Drain current (pulsed)
Drain current (continuous) at T
1.
The value is rated according to R thj-case
2.
Pulse width limited by safe operating area
3.
The value is rated according to R thj-pcb
C
C
= 25 °C
= 100 °C pcb
Drain current (continuous) at T pcb
Total dissipation at T
C
Total dissipation at T
Storage temperature
= 25 °C pcb
= 25 °C
Operating junction temperature
= 25 °C
=100 °C
Value
-55 to 175
75
+20\-16
40
26
160
10
6
75
4.8
Symbol
Table 3. Thermal resistance
Parameter
R thj-case
R thj-pcb
(1)
Thermal resistance junction-case
Thermal resistance junction-ambient
1.
When mounted on FR-4 board of 1 inch², 2oz Cu., t < 10 sec.
Value
2
31.3
Unit
°C/W
°C/W
Unit
A
A
A
V
V
A
A
W
W
°C
DocID023810 Rev 2 3/14
14
Electrical characteristics STL40N75LF3
(T
CASE
= 25 °C unless otherwise specified).
Symbol Parameter
V
(BR)DSS
V
I
I
DSS
GSS
GS(th)
Drain-source breakdown voltage (V
GS
= 0)
Zero gate voltage drain current (V
GS
= 0)
Gate body leakage current
(V
DS
= 0)
Gate threshold voltage
R
DS(on)
Static drain-source on resistance
Table 4. On/off states
Test conditions
I
D
= 250 µA
V
DS
= 75 V,
V
DS
= 75 V, T
C
= 125 °C
V
GS
= +20 / -16 V
V
DS
= V
GS
, I
D
= 250 µA
V
GS
= 10 V, I
D
= 20 A
V
GS
= 5 V, I
D
= 20 A
Min.
Typ.
75
1
16
18.7
Max.
Unit
1
10
± 100
19
22
V
µA
µA nA
V m Ω m
Ω
Symbol
C
C
C
Q
Q
Q iss oss rss g gs gd
Parameter
Input capacitance
Output capacitance
Reverse transfer capacitance
Total gate charge
Gate-source charge
Gate-drain charge
R
G
Gate input resistance
Table 5. Dynamic
Test conditions
V
V
DS
GS
= 25 V, f = 1 MHz,
= 0
V
DD
= 37.5 V, I
D
= 40 A
V
GS
= 5 V
(see
Figure 14 )
f=1 MHz gate DC bias=0
Test signal level = 20 mV open drain
Min.
Typ.
Max.
Unit
-
-
1300
228
15
12
5
5.3
-
pF pF pF nC nC nC
3.5
Ω
Symbol t d(on) t r t d(off) t f
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Table 6. Switching times
Test conditions
V
DD
= 37.5 V, I
D
= 20 A,
R
G
= 4.7 Ω, V
GS
=10 V
(see Figure 13
)
Min.
Typ.
Max.
Unit
-
12
25
25
3
ns ns ns ns
4/14 DocID023810 Rev 2
STL40N75LF3 Electrical characteristics
Symbol Parameter
Table 7. Source-drain diode
Test conditions
I
SD
I
SDM
(1)
V
SD
(2) t rr
Q rr
I
RRM
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
1.
Pulse width limited by safe operating area
2.
Pulsed: pulse duration=300µs, duty cycle 1.5%
I
SD
= 40 A, V
GS
=0
I
SD
= 40 A, di/dt = 100 A/µs,
V
DD
=60 V
Min Typ.
Max Unit
-
-
40
160
1.1
-
35
44
27
A
A
V ns nC
A
DocID023810 Rev 2 5/14
14
Electrical characteristics STL40N75LF3
2.1
I
D
(A)
100
10
Electrical characteristics (curves)
Figure 2. Safe operating area
Limit y max R ea is
DS(on)
AM15409v1
10ms
Figure 3. Thermal impedance
GIPD130920131022FSR
K
δ= 0.5
0.2
0.1
10
-2
0.05
0.02
0.01
10
-3
1
100ms
0.1
Tj= 175°C
Tc=25°C
Single pulse
10
1s
0.01
0.1
1 V
DS
(V)
Figure 4. Output characteristics
AM15410v1
I
D
(A)
VGS= 10 V
100
10
-4
Single pulse
10
-5
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
10
0 t p
(s)
Figure 5. Transfer characteristics
AM15411v1
I
D
(A)
V
DS
= 4 V
100
80
80
VGS= 5 V
60 60
VGS= 4 V
40 40
20 20
0
0 1 2 3
VGS= 3 V
V
DS
(V)
0
0 1 2 3 4 5 6 7 8 V
GS
(V)
Figure 6. Gate charge vs gate-source voltage
AM15412v1
V
GS
(V)
10
V
DD
=37.5 V
I
D
=40A
Figure 7. Static drain-source on-resistance
R
DS(on)
(m
Ω
)
30
V
GS
=10V
AM15413v1
25
8
20
6
15
4
10
2
5
0
0 5 10 15 20 25 Q g
(nC)
0
0 10 20 30 40 I
D
(A)
6/14 DocID023810 Rev 2
STL40N75LF3 Electrical characteristics
Figure 8. Capacitance variations
C
(pF)
3500
AM15414v1
Figure 9. Normalized V(BR)
DSS
vs temperature
AM15415v1
V(BR)
DSS
(norm)
1.15
I
D
= 1mA
3000 1.1
1.05
2500
2000
1500 0.95
1
Ciss
1000
500
0
0 10 20 30 40
Coss
Crss
V
DS
(V)
0.9
0.85
0.8
-55 -30 -5 20 45 70 95 120 T
J
(°C)
Figure 10. Normalized gate threshold voltage vs temperature
AM15344v1 V
GS(th)
(norm)
1.2
1
I
D
=250 µA
Figure 11. Normalized on-resistance vs temperature
AM15417v1
R
DS(on)
(norm)
2
V
GS
=5 V
I
D=
20 A
1.5
0.8
1
0.6
0.5
0.4
0.2
-55 -30 -5 20 45 70 95 120 T
J
(°C)
Figure 12. Source-drain diode forward characteristics
AM15418v1
V
SD
(V)
1
T
J
=-50°C
0.9
T
J
=25°C
0.8
0.7
0.6
0.5
0.4
0 10 20 30
T
J
=175°C
40 I
SD
(A)
0
-55 -30 -5 20 45 70 95 120 I
D
(A)
DocID023810 Rev 2 7/14
14
Test circuits
3 Test circuits
STL40N75LF3
Figure 13. Switching times test circuit for resistive load
Figure 14. Gate charge test circuit
V
DD
12V
47k
Ω
100nF
1k Ω
V
GS
V
D
R
G
R
L
D.U.T.
2200
μ
F
3.3
μ
F
V
DD
V i
=20V=V
GMAX
2200
μ F
I
G
=CONST
2.7k
Ω
100 Ω
D.U.T.
V
G
P
W
AM01468v1
Figure 15. Test circuit for inductive load switching and diode recovery times
47k
Ω
P
W
1k
Ω
AM01469v1
Figure 16. Unclamped inductive load test circuit
25 Ω
G
D
A
D.U.T.
S
B
R
G
A
FAST
DIODE
A
B
B
G
D
S
L=100 μ H
3.3
μ F
1000
μ F
V
DD
V i
AM01470v1
Figure 17. Unclamped inductive waveform
V
(BR)DSS
V
D
V
D
I
D
L
2200
μ F
3.3
μ F
V
DD
D.U.T.
P w
AM01471v1
Figure 18. Switching time waveform t on td on t r t off td off t f
I
DM
90%
90%
10%
I
D 0
10% V
DS
V
DD
V
DD
90%
V
GS
AM01472v1
0
10%
AM01473v1
8/14 DocID023810 Rev 2
STL40N75LF3
4 Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK
®
is an ST trademark.
Figure 19. PowerFLAT™ 5x6 type S-C drawings
DocID023810 Rev 2
8231817_H_C
9/14
14
Package mechanical data STL40N75LF3
Dim.
A
A1
A2 b
D
E
D2
E2 e e1
L
K
Table 8. PowerFLAT™ 5x6 type S-C mechanical data mm
Typ.
Min.
0.80
0.02
0.25
0.30
5.20
6.15
4.11
3.50
1.27
0.65
0.715
1.05
Max.
1.00
0.05
0.50
4.31
3.70
1.015
1.35
Figure 20. PowerFLAT™ 5x6 type S-C recommended footprint (dimensions in mm)
10/14 DocID023810 Rev 2
Footprint
STL40N75LF3 Packaging information
T
(0.30
±0.05)
Figure 21. PowerFLAT™ 5x6 type S-C tape
P 2
2.0±0.1 (I)
P 0
4.0±0.1 (II)
Do
Ø1.55±0.05
Y
D1
Ø1.5 MIN.
REF 0.20
E
1
1.75±0.1
REF
.R0.50
Y
P1(8.00±0.1) Ao(6.30±0.1)
SECTION Y-Y
Ko (1.20±0.1)
(I) Measured from centerline of sprocket hole to centerline of pocket.
(II) Cumulative tolerance of 10 sprocket holes is ± 0.20 .
(III) Measured from centerline of sprocket hole to centerline of pocket.
Base and bulk quantity 3000 pcs
8234350_Tape_rev_C
Figure 22. PowerFLAT™ 5x6 type S-C package orientation in carrier tape
Pin 1 identification
DocID023810 Rev 2 11/14
14
Packaging information
PART NO.
06
PS
2.50
Figure 23. PowerFLAT™ 5x6 type S-C reel
R0.60
W3
11.9/15.4
1.90
2.50
W2
18.4 (max)
R25.00
4.00
ØN
178(±2.0)
77 ESD LOGO
W1
12.4 (+2/-0)
ØA
128
Ø21.2
R1.10
13.00
CORE DETAIL
STL40N75LF3
All dimensions are in millimeters
8234350_Reel_rev_C
A
330 (+0/-4.0)
12/14 DocID023810 Rev 2
STL40N75LF3 Revision history
Date
19-Oct-2012
24-Feb-2014
Revision
Table 9. Document revision history
Changes
1
2
First release.
Deleted note in the table of Features .
Updated Figure 1 .
Updated values of P
TOT ,
T
J and T stg
in Table 2 .
Updated notes in Table 2
.
Updated V
GS test condition in
Table 5 .
Updated V
DD test condition in
Table 6 .
Removed T j
test condition from Table 7
.
Updated Figure 2 , Figure 4 , Figure 6 ,
Figure 9 and Figure 11 .
Updated mechanical data.
DocID023810 Rev 2 13/14
14
STL40N75LF3
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