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SN32F100 Series
32-Bit Cortex-M0 Micro-Controller
3.2.3 EXTERNAL CLOCK SOURCE
3.2.3.1 External High-speed (EHS) Clock
External high clock includes Crystal/Ceramic modules. The start up time of is longer. The oscillator start-up time decides reset time length.
4MHz Crystal
4MHz Ceramic
3.2.3.2 CRYSTAL/CERAMIC
Crystal/Ceramic devices are driven by XIN, XOUT pins. For high/normal/low frequency, the driving currents are different.
C
20pF
CRYSTAL
XIN
XOUT
MCU
C
20pF
VDD
VCC
GND
Note: Connect the Crystal/Ceramic and C as near as possible to the XIN/XOUT/VSS pins of MCU.
Structure: 1MHz~25MHz EHS external crystal/ceramic resonator
Main Purpose: System high clock source, RTC clock source, and PLL clock source.
Warm-up Time: 2048*F
EHS
XIN/XOUT Shared Pin Selection:
Oscillator Mode XTALIN pin
GPIO
XTALOUT pin
IHRC
EHS X’TAL
Crystal/Ceramic
GPIO
Crystal/Ceramic
SONiX TECHNOLOGY CO., LTD
Page 46
Version 1.4
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Table of contents
- 2 HISTORY
- 13 PRODUCT OVERVIEW
- 13 FEATURES
- 15 DIAGRAM
- 17 ASSIGNMENT
- 20 DESCRIPTIONS
- 25 DIAGRAMS
- 27 CENTRAL PROCESSOR UNIT (CPU)
- 27 TIMER
- 28 OPERATION
- 28 SYSTICK USAGE HINTS AND TIPS
- 29 SYSTICK REGISTERS
- 29 System Tick Timer Control and Status register (SYSTICK_CTRL)
- 29 System Tick Timer Reload value register (SYSTICK_LOAD)
- 29 System Tick Timer Current Value register (SYSTICK_VAL)
- 30 System Tick Timer Calibration Value register (SYST_CALIB)
- 31 (NVIC)
- 31 INTERRUPT AND EXCEPTION VECTORS
- 31 NVIC REGISTERS
- 32 IRQ0~31 Interrupt Set-Enable Register (NVIC_ISER)
- 32 IRQ0~31 Interrupt Clear-Enable Register (NVIC_ICER)
- 32 IRQ0~31 Interrupt Set-Pending Register (NVIC_ISPR)
- 32 IRQ0~31 Interrupt Clear-Pending Register (NVIC_ICPR)
- 33 IRQ0~31 Interrupt Priority Register (NVIC_IPRn) (n=0~7)
- 33 (AIRC)
- 35 TABLE
- 36 OVERVIEW
- 37 SYSTEM CONTROL
- 37 RESET
- 37 POWER-ON RESET (POR)
- 38 WATCHDOG RESET (WDT RESET)
- 38 BROWN-OUT RESET
- 38 BROWN OUT DESCRIPTION
- 39 THE SYSTEM OPERATING VOLTAGE DECSRIPTION
- 39 BROWN-OUT RESET IMPROVEMENT
- 40 EXTERNAL RESET
- 41 SIMPLY RC RESET CIRCUIT
- 41 DIODE & RC RESET CIRCUIT
- 42 ZENER DIODE RESET CIRCUIT
- 42 VOLTAGE BIAS RESET CIRCUIT
- 43 EXTERNAL RESET IC
- 43 SOFTWARE RESET
- 44 CLOCK
- 44 INTERNAL RC CLOCK SOURCE
- 44 Internal High-speed RC Oscillator (IHRC)
- 44 Internal Low-speed RC Oscillator (ILRC)
- 45 PLL Frequency selection
- 46 EXTERNAL CLOCK SOURCE
- 46 External High-speed (EHS) Clock
- 46 CRYSTAL/CERAMIC
- 47 Audio External High-speed (AUEHS) Clock
- 47 External Low-speed (ELS) Clock
- 47 CRYSTAL
- 48 Bypass Mode
- 49 SYSTEM CLOCK (SYSCLK) SELECTION
- 49 CLOCK-OUT CAPABITITY
- 50 Analog Block Control register (SYS0_ANBCTRL)
- 50 PLL control register (SYS0_PLLCTRL)
- 51 RECOMMEND FREQUENCY SETTING
- 52 Clock Source Status register (SYS0_CSST)
- 52 System Clock Configuration register (SYS0_CLKCFG)
- 52 AHB Clock Prescale register (SYS0_AHBCP)
- 53 System Reset Status register (SYS0_RSTST)
- 53 LVD Control register (SYS0_LVDCTRL)
- 55 External RESET Pin Control register (SYS0_EXRSTCTRL)
- 55 SWD Pin Control register (SYS0_SWDCTRL)
- 55 Anti-EFT Ability Control register (SYS0_ANTIEFT)
- 56 AHB Clock Enable register (SYS1_AHBCLKEN)
- 57 APB Clock Prescale register 0 (SYS1_APBCP0)
- 58 APB Clock Prescale register 1 (SYS1_APBCP1)
- 59 Peripheral Reset register (SYS1_PRST)
- 61 SYSTEM OPERATION MODE
- 61 OVERVIEW
- 61 MODES
- 61 SLEEP MODE
- 62 DEEP-SLEEP MODE
- 62 DEEP POWER-DOWN (DPD) MODE
- 63 Entering Deep power-down mode
- 63 Exiting Deep power-down mode
- 63 INTERRUPT
- 64 TABLE
- 65 REGISTERS
- 65 Backup registers 0 to 15 (PMU_BKP0~15)
- 65 Power control register (PMU_CTRL)
- 66 GENERAL PURPOSE I/O PORT (GPIO)
- 66 OVERVIEW
- 67 REGISTERS
- 67 GPIO Port n Data register (GPIOn_DATA) (n=0,1,2,3)
- 67 GPIO Port n Mode register (GPIOn_MODE) (n=0,1,2,3)
- 67 GPIO Port n Configuration register (GPIOn_CFG) (n=0,1,2,3)
- 69 GPIO Port n Interrupt Sense register (GPIOn_IS) (n=0,1,2,3)
- 69 GPIO Port n Interrupt Both-edge Sense register (GPIOn_IBS) (n=0,1,2,3)
- 69 GPIO Port n Interrupt Event register (GPIOn_IEV) (n=0,1,2,3)
- 69 GPIO Port n Interrupt Enable register (GPIOn_IE) (n=0,1,2,3)
- 70 GPIO Port n Raw Interrupt Status register (GPIOn_RIS) (n=0,1,2,3)
- 70 GPIO Port n Interrupt Clear register (GPIOn_IC) (n=0,1,2,3)
- 70 GPIO Port n Bits Set Operation register (GPIOn_BSET) (n=0,1,2,3)
- 70 GPIO Port n Bits Clear Operation register (GPIOn_BCLR) (n=0,1,2,3)
- 70 GPIO Port n Open-Drain Control register (GPIOn_ODCTRL) (n=0,1,2,3)
- 72 16-BIT TIMER WITH CAPTURE FUNCTION
- 72 OVERVIEW
- 72 FEATURES
- 72 DESCRIPTION
- 73 DIAGRAM
- 74 OPERATION
- 76 REGISTERS
- 76 CT16Bn Timer Control register (CT16Bn_TMRCTRL) (n=0,1)
- 76 CT16Bn Timer Counter register (CT16Bn_TC) (n=0,1)
- 76 CT16Bn Prescale register (CT16Bn_PRE) (n=0,1)
- 76 CT16Bn Prescale Counter register (CT16Bn_PC) (n=0,1)
- 77 CT16Bn Count Control register (CT16Bn_CNTCTRL) (n=0,1)
- 77 CT16Bn Match Control register (CT16Bn_MCTRL) (n=0,1)
- 78 CT16Bn Match register 0~3 (CT16Bn_MR0~3) (n=0,1)
- 78 CT16Bn Capture Control register (CT16Bn_CAPCTRL) (n=0,1)
- 79 CT16Bn Capture 0 register (CT16Bn_CAP0) (n=0,1)
- 79 CT16Bn External Match register (CT16Bn_EM) (n=0,1)
- 79 CT16Bn PWM Control register (CT16Bn_PWMCTRL) (n=0,1)
- 80 CT16Bn Timer Raw Interrupt Status register (CT16Bn_RIS) (n=0,1)
- 80 CT16Bn Timer Interrupt Clear register (CT16Bn_IC) (n=0,1)
- 81 32-BIT TIMER WITH CAPTURE FUNCTION
- 81 OVERVIEW
- 81 FEATURES
- 81 DESCRIPTION
- 82 DIAGRAM
- 83 OPERATION
- 85 REGISTERS
- 85 CT32Bn Timer Control register (CT32Bn_TMRCTRL) (n=0,1)
- 85 CT32Bn Timer Counter register (CT32Bn_TC) (n=0,1)
- 85 CT32Bn Prescale register (CT32Bn_PRE) (n=0,1)
- 85 CT32Bn Prescale Counter register (CT32Bn_PC) (n=0,1)
- 85 CT32Bn Count Control register (CT32Bn_CNTCTRL) (n=0,1)
- 86 CT32Bn Match Control register (CT32Bn_MCTRL) (n=0,1)
- 87 CT32Bn Match register 0~3 (CT32Bn_MR0~3) (n=0,1)
- 87 CT32Bn Capture Control register (CT32Bn_CAPCTRL) (n=0,1)
- 88 CT32Bn Capture 0 register (CT32Bn_CAP0) (n=0,1)
- 88 CT32Bn External Match register (CT32Bn_EM) (n=0,1)
- 88 CT32Bn PWM Control register (CT32Bn_PWMCTRL) (n=0,1)
- 89 CT32Bn Timer Raw Interrupt Status register (CT32Bn_RIS) (n=0,1)
- 89 CT32Bn Timer Interrupt Clear register (CT32Bn_IC) (n=0,1)
- 90 WATCHDOG TIMER (WDT)
- 90 OVERVIEW
- 91 DIAGRAM
- 92 REGISTERS
- 92 Watchdog Configuration register (WDT_CFG)
- 92 Watchdog Clock Source register (WDT_CLKSOURCE)
- 92 Watchdog Timer Constant register (WDT_TC)
- 93 Watchdog Feed register (WDT_FEED)
- 94 REAL-TIME CLOCK (RTC)
- 94 OVERVIEW
- 94 FEATURES
- 94 DESCRIPTION
- 94 INTRODUCTION
- 94 RESET RTC REGISTERS
- 94 RTC FLAG ASSERTION
- 95 RTC OPERATION
- 96 DIAGRAM
- 97 REGISTERS
- 97 RTC Control register (RTC_CTRL)
- 97 RTC Clock Source Select register (RTC_CLKS)
- 97 RTC Interrupt Enable register (RTC_IE)
- 97 RTC Raw Interrupt Status register (RTC_RIS)
- 98 RTC Interrupt Clear register (RTC_IC)
- 98 RTC Second Counter Reload Value register (RTC_SECCNTV)
- 98 RTC Second Count register (RTC_SECCNT)
- 98 RTC Alarm Counter Reload Value register (RTC_ALMCNTV)
- 99 RTC Alarm Count register (RTC_ALMCNT)
- 100 SPI/SSP
- 100 OVERVIEW
- 100 FEATURES
- 101 DESCRIPTION
- 103 COMMUNICATION FLOW
- 103 SINGLE-FRAME
- 104 MULTI-FRAME
- 105 REGISTERS
- 105 SSP n Control register 0 (SSPn_CTRL0) (n=0, 1)
- 106 SSP n Control register 1 (SSPn_CTRL1) (n=0, 1)
- 106 SSP n Clock Divider register (SSPn_CLKDIV) (n=0, 1)
- 106 SSP n Status register (SSPn_STAT) (n=0, 1)
- 107 SSP n Interrupt Enable register (SSPn_IE) (n=0, 1)
- 107 SSP n Raw Interrupt Status register (SSPn_RIS) (n=0, 1)
- 107 SSP n Interrupt Clear register (SSPn_IC) (n=0, 1)
- 108 SSP n Data register (SSPn_DATA) (n=0, 1)
- 109 OVERVIEW
- 109 FEATURES
- 110 DESCRIPTION
- 110 CHARACTERISTICS
- 111 MODES
- 111 MASTER TRANSMITTER MODE
- 111 MASTER RECEIVER MODE
- 111 ARBITRATION
- 112 MODES
- 112 SLAVE TRANSMITTER MODE
- 112 SLAVE RECEIVER MODE
- 113 INTERRUPT
- 113 LOSS of ARBITRATION
- 114 REGISTERS
- 114 I2C n Control register (I2Cn_CTRL) (n=0,1)
- 115 I2C n Status register (I2Cn_STAT) (n=0,1)
- 115 I2C n TX Data register (I2Cn_TXDATA) (n=0,1)
- 116 I2C n RX Data register (I2Cn_RXDATA) (n=0,1)
- 116 I2C n Slave Address 0 register (I2Cn_SLVADDR0) (n=0,1)
- 116 I2C n Slave Address 1~3 register (I2Cn_SLVADDR1~3) (n=0,1)
- 116 I2C n SCL High Time register (I2Cn_SCLHT) (n=0,1)
- 117 I2C n SCL Low Time register (I2Cn_SCLLT) (n=0,1)
- 117 I2C n Timeout Control register (I2Cn_TOCTRL) (n=0,1)
- 117 I2C n Monitor Mode Control register (I2Cn_MMCTRL) (n=0,1)
- 118 UNIVERSAL ASYNCHRONOUS SERIAL RECEIVER AND TRANSMITTER (UART)
- 118 OVERVIEW
- 118 FEATURES
- 118 DESCRIPTION
- 119 DIAGRAM
- 120 CALCULATION
- 121 AUTO-BAUD
- 122 AUTO-BAUD MODES
- 124 REGISTERS
- 124 UART n Receiver Buffer register (UARTn_RB) (n=0, 1)
- 124 UART n Transmitter Holding register (UARTn_TH) (n=0, 1)
- 124 UART n Divisor Latch LSB registers (UARTn_DLL) (n =0, 1)
- 124 UART n Divisor Latch MSB register (UARTn_DLM) (n=0,1)
- 125 UART n Interrupt Enable register (UARTn_IE) (n=0, 1)
- 125 UART n Interrupt Identification register (UARTn_II) (n=0,1)
- 127 UART n FIFO Control register (UARTn_FIFOCTRL) (n=0,1)
- 127 UART n Line Control register (UARTn_LC) (n=0,1)
- 127 UART n Line Status register (UARTn_LS) (n=0,1)
- 129 UART n Scratch Pad register (UARTn_SP) (n=0, 1)
- 129 UART n Auto-baud Control register (UARTn_ABCTRL) (n=0, 1)
- 129 UART n Fractional Divider register (UARTn_FD) (n=0, 1)
- 130 UART n Control register (UARTn_CTRL) (n=0, 1)
- 130 UART n Half-duplex Enable register (UARTn_HDEN) (n=0, 1)
- 132 AUDIO (I2S/CODEC)
- 132 OVERVIEW
- 132 I2S Description
- 132 Codec Description
- 132 FEATURES
- 132 I2S Features
- 132 Codec Features
- 133 DESCRIPTION
- 133 I2S Pin Description
- 133 Codec Pin Description
- 133 Audio Clock Pin Description
- 134 DIAGRAM
- 134 I2S CLCOK CONTROL
- 134 I2S BLOCK DIAGRAM
- 135 16-Bit Sigma-Delta ADC BLOCK DIAGRAM
- 136 16-Bit Sigma-Delta DAC BLOCK DIAGRAM
- 137 DESCRIPTION
- 137 I2S OPERATION
- 139 I2S FIFO OPERAION
- 139 STEREO
- 140 REGISTERS
- 140 I2S Control register (I2S_CTRL)
- 141 I2S Clock register (I2S_CLK)
- 141 I2S Status register (I2S_STATUS)
- 142 I2S Interrupt Enable register (I2S_IE)
- 142 I2S Raw Interrupt Status register (I2S_RIS)
- 143 I2S Interrupt Clear register (I2S_IC)
- 143 I2S RX FIFO register (I2S_RXFIFO)
- 143 I2S TX FIFO register (I2S_TXFIFO)
- 143 REGISTERS
- 143 ADC Setting 1 register (ADC_SET1)
- 144 ADC Setting 2 register (ADC_SET2)
- 144 ADC Setting 3 register (ADC_SET3)
- 144 ADC Setting 4 register (ADC_SET4)
- 144 ADC Setting 5 register (ADC_SET5)
- 144 ADC Setting 6 register (ADC_SET6)
- 144 ADC Setting 7 register (ADC_SET7)
- 145 ADC Setting 8 register (ADC_SET8)
- 145 ADC Setting 9 register (ADC_SET9)
- 145 ADC Setting 10 register (ADC_SET10)
- 145 ADC Setting 11 register (ADC_SET11)
- 145 ADC Setting 12 register (ADC_SET12)
- 146 ADC Setting 13 register (ADC_SET13)
- 146 ADC Setting 14 register (ADC_SET14)
- 146 ADC Setting 15 register (ADC_SET15)
- 146 ADC Setting 16 register (ADC_SET16)
- 147 ADC Setting 18 register (ADC_SET18)
- 147 ADC Setting 19 register (ADC_SET19)
- 148 ADC Setting 20 register (ADC_SET20)
- 148 ADC Setting 21 register (ADC_SET21)
- 148 ADC Setting 22 register (ADC_SET22)
- 148 ADC Setting 23 register (ADC_SET23)
- 149 ADC Setting 24 register (ADC_SET24)
- 149 REGISTERS
- 149 DAC Setting 1 register (DAC_SET1)
- 149 DAC Setting 2 register (DAC_SET2)
- 149 DAC Setting 3 register (DAC_SET3)
- 150 DAC Setting 4 register (DAC_SET4)
- 150 DAC Status register (DAC_STATUS)
- 150 Sigma-delta ADC Power-up Sequence
- 150 Sigma-delta ADC Power-down Sequence
- 151 Sigma-delta ADC Enable Sequence
- 151 Sigma-delta DAC Power-up Sequence
- 151 Sigma-delta DAC Power-down Sequence
- 151 Sigma-delta DAC Enable Sequence
- 152 24-CHANNEL COMPARATOR
- 152 OVERVIEW
- 153 OPERATION
- 154 NOTICE
- 154 REGISTERS
- 154 Comparator Control register (CMPM)
- 155 Comparator Interrupt Enable register (CMP_IE)
- 156 Comparator Interrupt Status register (CMP_RIS)
- 156 Comparator Interrupt Clear register (CMP_IC)
- 157 FLASH
- 157 OVERVIEW
- 157 MEMORY
- 157 FEATURES
- 158 ORGANIZATION
- 158 PROGRAM/ERASE
- 158 LOADER
- 159 (FMC)
- 159 CODE SECURITY (CS)
- 160 PROGRAM FLASH MEMORY
- 160 ERASE
- 160 PAGE ERASE
- 160 MASS ERASE
- 160 PROTECTION
- 161 REGISTERS
- 161 Flash Status register (FLASH_STATUS)
- 161 Flash Control register (FLASH_CTRL)
- 161 Flash Data register (FLASH_DATA)
- 162 Flash Address register (FLASH_ADDR)
- 163 SERIAL-WIRE DEBUG (SWD)
- 163 OVERVIEW
- 163 FEATURES
- 163 DESCRIPTION
- 163 LIMITATIONS
- 163 DEBUG RECOVERY
- 163 INTERNAL PULL-UP/DOWN RESITIORS on SWD PINS
- 164 DEVELOPMENT TOOL
- 164 SN-LINK
- 165 STARTER-KIT
- 165 SN32F100 Start Kit V
- 167 SN32F100 Start Kit V1.1/V
- 169 ELECTRICAL CHARACTERISTIC
- 169 RATING
- 169 CHARACTERISTIC
- 171 GRAPHS
- 172 FLASH ROM PROGRAMMING PIN
- 173 PACKAGE INFORMATION
- 176 MARKING DEFINITION
- 176 INTRODUCTION
- 176 SYSTEM
- 177 EXAMPLE
- 177 SYSTEM