SN32F100 Spec.

SN32F100 Series

32-Bit Cortex-M0 Micro-Controller

19:1

0

Reserved

PWM0EN

PWM0EN bit.

PWM0 enable

0: CT16Bn_PWM0 is controlled by EM0.

1: PWM mode is enabled for CT16Bn_PWM0.

R

R/W

0

0

6.7.12 CT16Bn Timer Raw Interrupt Status register (CT16Bn_RIS) (n=0,1)

Address Offset: 0x38

This register indicates the raw status for Timer/PWM interrupts. A Timer/PWM interrupt is sent to the interrupt controller if the corresponding bit in the CT16Bn_IE register is set.

Bit Name Description Attribute Reset

31:5

Reserved

4

3

2

1

0

CAP0IF

MR3IF

MR2IF

MR1IF

MR0IF

Interrupt flag for capture channel 0.

0: No interrupt on CAP0

1: Interrupt requirements met on CAP0.

Interrupt flag for match channel 3.

0: No interrupt on match channel 3

1: Interrupt requirements met on match channel 3.

Interrupt flag for match channel 2.

0: No interrupt on match channel 2

1: Interrupt requirements met on match channel 2.

Interrupt flag for match channel 1.

0: No interrupt on match channel 1

1: Interrupt requirements met on match channel 1.

Interrupt flag for match channel 0.

0: No interrupt on match channel 0

1: Interrupt requirements met on match channel 0.

6.7.13 CT16Bn Timer Interrupt Clear register (CT16Bn_IC) (n=0,1)

Address Offset: 0x3C

Bit Name Description

R

R

R

R

R

R

0

0

0

0

0

0

Attribute Reset

31:5

4

Reserved

CAP0IC

R

W

0

0

3

2

1

0

MR3IC

MR2IC

MR1IC

MR0IC

0: No effect

1: Clear CAP0IF bit

0: No effect

1: Clear MR3IF bit

0: No effect

1: Clear MR2IF bit

0: No effect

1: Clear MR1IF bit

0: No effect

1: Clear MR0IF bit

W

W

W

W

0

0

0

0

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