SN32F100 Spec.

SN32F100 Series

32-Bit Cortex-M0 Micro-Controller

counting.

When Counter Mode is chosen as a mode of operation, the CAP input (selected by CIS bits) is sampled on every rising edge of the PCLK clock. After comparing two consecutive samples of this CAP input, one of the following four events is recognized: rising edge, falling edge, either of edges or no changes in the level of the selected CAP input. Only if the identified event occurs, and the event corresponds to the one selected by CTM bits in this register, will the Timer

Counter register be incremented.

Effective processing of the externally supplied clock to the counter has some limitations. Since two successive rising edges of the PCLK clock are used to identify only one edge on the CAP selected input, the frequency of the CAP input can not exceed one half of the PCLK clock. Consequently, the duration of the HIGH/LOW levels on the same CAP input in this case can not be shorter than 1/ (2 x PCLK).



Note: If Counter mode is selected in the CNTCTRL register, Capture Control (CAPCTRL) register must be programmed as 0x0.

Bit Name Description Attribute Reset

31:4

Reserved

3:2

1:0

CIS[1:0]

CTM[1:0]

Count Input Select.

In counter mode (when CTM[1:0] are not 00), these bits select which CAP pin is sampled for clocking.

00: CT32Bn_CAP0

Other: Reserved.

Counter/Timer Mode.

This field selects which rising PCLK edges can clear PC and increment

Timer Counter (TC).

00: Timer Mode: every rising PCLK edge

01: Counter Mode: TC is incremented on rising edges on the CAP input selected by CIS bits.

10: Counter Mode: TC is incremented on falling edges on the CAP input selected by CIS bits.

11: Counter Mode: TC is incremented on both edges on the CAP input selected by CIS bits.

7.7.6 CT32Bn Match Control register (CT32Bn_MCTRL) (n=0,1)

R

R/W

R/W

0

0

0

Address Offset: 0x14

Bit Name

31:12

11

Reserved

MR3STOP

10

9

8

7

6

5

4

MR3RST

MR3IE

MR2STOP

MR2RST

MR2IE

MR1STOP

MR1RST

Description

Stop MR3: TC will stop and CEN bit will be cleared if MR3 matches TC.

0: Disable

1: Enable

Enable reset TC when MR3 matches TC.

0: Disable

1: Enable

Enable generating an interrupt when MR3 matches the value in the TC.

0: Disable

1: Enable

Stop MR2: TC will stop and CEN bit will be cleared if MR2 matches TC.

0: Disable

1: Enable

Enable reset TC when MR2 matches TC.

0: Disable

1: Enable

Enable generating an interrupt when MR2 matches the value in the TC.

0: Disable

1: Enable

Stop MR1: TC will stop and CEN bit will be cleared if MR1 matches TC.

0: Disable

1: Enable

Enable reset TC when MR1 matches TC.

Attribute Reset

R

R/W

0

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0

0

0

0

0

0

0

SONiX TECHNOLOGY CO., LTD

Page 86

Version 1.4