SN32F100 Spec.

SN32F100 Series

32-Bit Cortex-M0 Micro-Controller

6

16-BIT TIMER WITH CAPTURE

FUNCTION

6.1 OVERVIEW

Each Counter/timer is designed to count cycles of the peripheral clock (PCLK) or an externally supplied clock and can optionally generate interrupts or perform other actions at specified timer values based on four match registers. Each counter/timer also includes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt.

In PWM mode, one match register can be used to provide a single-edge controlled PWM output on the match output pins.

6.2 FEATURES



Two 16-bit counter/timers.



Counter or timer operation



Two 16-bit capture channels that can take a snapshot of the timer value when an input signal transitions. A capture event may also optionally generate an interrupt.



The timer value may be configured to be cleared on a designated capture event. This feature permits easy pulse-width measurement by clearing the timer on the leading edge of an input pulse and capturing the timer value on the trailing edge.



Four 16-bit match registers that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.



One (CT16B0 or CT16B1) PWM output corresponding to match register with the following capabilities:

– Set LOW on match.

– Set HIGH on match.

– Toggle on match.

– Do nothing on match.



For each timer, one match register (MR0) can be configured as PWM allowing to use one match output as single edge controlled PWM output.

6.3 PIN DESCRIPTION

Pin Name

CT16Bn_CAP0

CT16Bn_PWMx

Type

I

O

Description

Capture channel input 0

Output channel x of Match/PWM output.

GPIO Configuration

Depends on GPIOn_CFG

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