SN32F100 Spec.

SN32F100 Series

32-Bit Cortex-M0 Micro-Controller

Bit Name Description

31:8

Reserved

7

6

5

4

RXFIFOTHIF

TXFIFOTHIF

RXFIFOUDIF

TXFIFOOVIF

RX FIFO threshold interrupt flag

0: No RX FIFO threshold interrupt

1: RX FIFO threshold triggered.

TX FIFO threshold interrupt flag

0: No TX FIFO threshold interrupt

1: TX FIFO threshold triggered.

RX FIFO underflow interrupt flag

0: No RX FIFO underflow

1: RX FIFO underflow (RX FIFO is empty and still being read).

TX FIFO overflow interrupt flag

0: No TX FIFO overflow

1: TX FIFO overflow (TX FIFO is full and still being written).

3:0

Reserved

13.6.6 I2S Interrupt Clear register (I2S_IC)

Address Offset: 0x14

Bit Name Description

31:8

Reserved

7

6

5

4

RXFIFOTHIC

TXFIFOTHIC

RXFIFOUDIC

TXFIFOOVIC

0: No effect

1: Clear RXFIFOTHIF bit

0: No effect

1: Clear TXFIFOTHIF bit

0: No effect

1: Clear RXFIFOOUDIF bit

0: No effect

1: Clear TXFIFOOVIF bit

3:0

Reserved

13.6.7 I2S RX FIFO register (I2S_RXFIFO)

Address Offset: 0x18

Bit Name Description

31:0

RXFIFO[31:0]

8 x 32-bit RX FIFO

13.6.8 I2S TX FIFO register (I2S_TXFIFO)

Address Offset: 0x1C

Bit Name Description

TXFIFO[31:0]

8 x 32-bit TX FIFO

31:0

Attribute Reset

R

R

0

0

R

R

R

R

Attribute Reset

R

W

0

0

W

W

W

R

0

0

0

0

0

0

0

0

Attribute Reset

R 0

Attribute Reset

W 0

13.7 CODEC ADC REGISTERS

Base Address: 0x4006 4000

 Note: Codec ADC Registers are available only when codec mode is selected by I2SMOD=1.

13.7.1 ADC Setting 1 register (ADC_SET1)

Address Offset: 0x540

Bit Name Description Attribute Reset

31:8

Reserved R 0

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