USER`S MANUAL

S3F80N8_UM_REV1.10 ADDRESS

8-BIT WORKING REGISTER ADDRESSING

You can also use 8-bit working register addressing to access registers in a selected working register area. To initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value

"1100B." This 4-bit value (1100B) indicates that the remaining four bits have the same effect as 4-bit working register addressing.

As shown in Figure 2-12, the lower nibble of the 8-bit address is concatenated in much the same way as for 4-bit addressing: Bit 3 selects either RP0 or RP1, which then supplies the five high-order bits of the final address; the three low-order bits of the complete address are provided by the original instruction.

Figure 2-13 shows an example of 8-bit working register addressing. The four high-order bits of the instruction address (1100B) specify 8-bit working register addressing. Bit 4 ("1") selects RP1 and the five high-order bits in

RP1 (10101B) become the five high-order bits of the register address. The three low order bits of the register address (011) are provided by the three low order bits of 8-bit instruction address. The five address bits from RP1 and the three address bits from the instruction are concatenated to form the complete register address, 0ABH

(10101011B).

These address bits indicate 8-bit working register addressing

RP0

RP1

Selects

RP0 or RP1

1 1 0 0

Address

8-bit logical address

Three low-order bits Register pointer provides five high-order bits

8-bit physical address

Figure 2-12. 8-Bit Working Register Addressing

2-13

ADDRESS SPACES S3F80N8_UM_REV1.10

RP0

0 1 1 0 0 0 0 0

Selects RP1

R11

1 1 0 0 1 0 1 1

8-bit address form instruction

'LD R11, R2'

Specifies working register addressing

RP1

1 0 1 0 1 0 0 0

1 0 1 0 1 0 1 1

Register address

(0ABH)

Figure 2-13. 8-Bit Working Register Addressing Example

2-14

S3F80N8_UM_REV1.10 ADDRESS

SYSTEM AND USER STACK

The S3F8-series microcontrollers use the system stack for data storage, subroutine calls and returns. The PUSH and POP instructions are used to control system stack operations. The S3F80N8 architecture supports stack operations in the internal register file.

Stack Operations

Return addresses for procedure calls and interrupts and data are stored on the stack. The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents of the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to their original locations. The stack address is always decremented before a push operation and incremented after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top of the stack, as shown in Figure 2-14.

High Address

Top of stack

PCL

PCH

PCL

PCH

Flags

Top of stack

Stack contents after a call instruction

Stack contents after an interrupt

Low Address

Figure 2-14. Stack Operations

User-Defined Stacks

You can freely define stacks in the internal register file as data storage locations. The instructions PUSHUI,

PUSHUD, POPUI, and POPUD support user-defined stack operations.

Stack Pointers

Register location D9H contains the 8-bit stack pointer (SP) that is used for system stack operations. After a reset, the SP value is undetermined.

Because only internal memory space is implemented in the S3F80N8, the SP must be initialized to an 8-bit value in the range 00H–7FH.

2-15

ADDRESS SPACES S3F80N8_UM_REV1.10

)

PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP

The following example shows you how to perform stack operations in the internal register file using PUSH and

POP instructions:

LD ;

; (Normally, the SP is set to 07FH by the initialization

•

•

•

PUSH

PUSH

PUSH

PUSH

•

PP

RP0

RP1

R3

•

•

POP R3

; Stack address 0FEH

; Stack address 0FDH

; Stack address 0FCH

; Stack address 0FBH

← PP

← RP0

← RP1

← R3

POP PP

; R3

← Stack address 0FBH

;

RP0

; PP

← Stack address 0FEH

2-16

3

ADDRESSING MODES

OVERVIEW

Instructions that are stored in program memory are fetched for execution using the program counter. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand. The operands specified in SAM88RC instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory.

The S3F-series instruction set supports seven explicit addressing modes. Not all of these addressing modes are available for each instruction. The seven addressing modes and their symbols are:

— Indirect Register (IR)

— Direct Address (DA)

— Indirect Address (IA)

— Relative Address (RA)

3-1

ADDRESSING MODES S3F80N8_UM_REV1.10

REGISTER ADDRESSING MODE (R)

In Register addressing mode (R), the operand value is the content of a specified register or register pair

(see Figure 3-1).

Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that space (see Figure 3-2).

8-bit Register

File Address

One-Operand

Instruction

(Example)

Program Memory dst

OPCODE

Register File

Point to One

Register in Register

File

Value used in

Instruction Execution

OPERAND

Sample Instruction:

DEC CNTR ; Where CNTR is the label of an 8-bit register address

Figure 3-1. Register Addressing

Register File

MSB Point to

RP0 ot RP1

RP0 or RP1

Program Memory

4-bit

Working Register dst src

OPCODE

Two-Operand

Instruction

(Example)

Sample Instruction:

ADD R1, R2

3 LSBs

Point to the

Working Register

(1 of 8)

OPERAND

; Where R1 and R2 are registers in the currently

selected working register area.

Selected

RP points to start of working register block

Figure 3-2. Working Register Addressing

3-2

INDIRECT REGISTER ADDRESSING MODE (IR)

In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6).

You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to indirectly address another memory location. Please note, however, that you cannot access locations C0H–FFH in set 1 using the Indirect Register addressing mode.

8-bit Register

File Address

One-Operand

Instruction

(Example)

Program Memory dst

OPCODE

Point to One

Register in Register

File

Address of Operand used by Instruction

Register File

ADDRESS

OPERAND

Value used in

Instruction Execution

Sample Instruction:

RL @SHIFT ; Where SHIFT is the label of an 8-bit register address

Figure 3-3. Indirect Register Addressing to Register File

3-3

ADDRESSING MODES

INDIRECT REGISTER ADDRESSING MODE (Continued)

Register File

S3F80N8_UM_REV1.10

Example

Instruction

References

Program

Memory

Program Memory dst

OPCODE

Points to

Register Pair

Sample Instructions:

CALL

JP

@RR2

@RR2

REGISTER

PAIR

Value used in

Instruction

Program Memory

OPERAND

16-Bit

Address

Points to

Program

Memory

Figure 3-4. Indirect Register Addressing to Program Memory

3-4

INDIRECT REGISTER ADDRESSING MODE (Continued)

Register File

MSB Points to

RP0 or RP1

RP0 or RP1

4-bit

Working

Register

Address

Program Memory dst src

OPCODE

~

3 LSBs

Point to the

Working Register

(1 of 8)

~

ADDRESS

~

~

Sample Instruction:

OR R3, @R6

Value used in

Instruction

OPERAND

Selected

RP points to start fo working register block

Figure 3-5. Indirect Working Register Addressing to Register File

3-5

ADDRESSING MODES

INDIRECT REGISTER ADDRESSING MODE (Concluded)

S3F80N8_UM_REV1.10

MSB Points to

RP0 or RP1

Register File

RP0 or RP1

4-bit Working

Register Address

Example Instruction

References either

Program Memory or

Data Memory

Program Memory dst src

OPCODE

Next 2-bit Point

to Working

Register Pair

(1 of 4)

LSB Selects

Register

Pair

Program Memory or

Data Memory

Value used in

Instruction

OPERAND

Selected

RP points to start of working register block

16-Bit address points to program memory or data memory

Sample Instructions:

LCD

LDE

LDE

R5,@RR6

R3,@RR14

@RR4, R8

; Program memory access

; External data memory access

; External data memory access

Figure 3-6. Indirect Working Register Addressing to Program or Data Memory

3-6

INDEXED ADDRESSING MODE (X)

Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the internal register file or in external memory. Please note, however, that you cannot access locations C0H–FFH in set 1 using Indexed addressing mode.

In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range –128 to +127. This applies to external memory accesses only (see Figure 3-8.)

For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained in a working register. For external memory accesses, the base address is stored in the working register pair designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to that base address

(see Figure 3-9).

The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction

(LD). The LDC and LDE instructions support Indexed addressing mode for internal program memory and for external data memory, when implemented.

Register File

RP0 or RP1

Two-Operand

Instruction

Example

Value used in

Instruction

~

OPERAND

~

Selected RP points to start of working register block

+

Program Memory

Base Address dst/src x

OPCODE

3 LSBs

Point to One of the

Woking Register

(1 of 8)

~

INDEX

~

Sample Instruction:

LD R0, #BASE[R1] ; Where BASE is an 8-bit immediate value

Figure 3-7. Indexed Addressing to Register File

3-7

ADDRESSING MODES

INDEXED ADDRESSING MODE (Continued)

S3F80N8_UM_REV1.10

4-bit Working

Register Address

Program Memory

OFFSET dst/src x

OPCODE

MSB Points to

RP0 or RP1

NEXT 2 Bits

Point to Working

Register Pair

(1 of 4)

LSB Selects

8-Bits

+

16-Bits

~

Register File

RP0 or RP1

~

Selected

RP points to start of working register block

Register

Pair

16-Bit address added to offset

Program Memory or

Data Memory

16-Bits

OPERAND

Value used in

Instruction

Sample Instructions:

LDC R4, #04H[RR2]

LDE R4,#04H[RR2]

; The values in the program address (RR2 + 04H)

are loaded into register R4.

; Identical operation to LDC example, except that

external program memory is accessed.

Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset

3-8

INDEXED ADDRESSING MODE (Concluded)

4-bit Working

Register Address

Program Memory

OFFSET

OFFSET dst/src src

OPCODE

Register File

MSB Points to

RP0 or RP1

NEXT 2 Bits

Point to Working

Register Pair

LSB Selects

8-Bits

+

16-Bits

~

RP0 or RP1

~

Selected

RP points to start of working register block

Register

Pair

Program Memory or

Data Memory

16-Bit address added to offset

16-Bits

OPERAND

Value used in

Instruction

Sample Instructions:

LDC R4, #1000H[RR2]

LDE R4,#1000H[RR2]

; The values in the program address (RR2 + 1000H)

are loaded into register R4.

; Identical operation to LDC example, except that

external program memory is accessed.

Figure 3-9. Indexed Addressing to Program or Data Memory

3-9

ADDRESSING MODES S3F80N8_UM_REV1.10

DIRECT ADDRESS MODE (DA)

In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call

(CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed.

The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for

Load operations to program memory (LDC) or to external data memory (LDE), if implemented.

Program or

Data Memory

Program Memory

Memory

Address

Used

Upper Address Byte

Lower Address Byte dst/src "0" or "1"

OPCODE

LSB Selects Program

Memory or Data Memory:

"0" = Program Memory

"1" = Data Memory

Sample Instructions:

LDC R5,1234H

LDE R5,1234H

; The values in the program address (1234H)

are loaded into register R5.

; Identical operation to LDC example, except that

external program memory is accessed.

Figure 3-10. Direct Addressing for Load Instructions

3-10

DIRECT ADDRESS MODE (Continued)

Program Memory

Next OPCODE

Memory

Address

Used

Upper Address Byte

Lower Address Byte

OPCODE

Sample Instructions:

JP C,JOB1

CALL DISPLAY

; Where JOB1 is a 16-bit immediate address

; Where DISPLAY is a 16-bit immediate address

Figure 3-11. Direct Addressing for Call and Jump Instructions

3-11

ADDRESSING MODES S3F80N8_UM_REV1.10

INDIRECT ADDRESS MODE (IA)

In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program memory. The selected pair of memory locations contains the actual address of the next instruction to be executed.

Only the CALL instruction can use the Indirect Address mode.

Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory, only an 8-bit address is supplied in the instruction; the upper bytes of the destination address are assumed to be all zeros.

Program Memory

Current

Instruction dst

OPCODE

Next Instruction

LSB Must be Zero

Lower Address Byte

Upper Address Byte

Program Memory

Locations 0-255

Sample Instruction:

CALL #40H ; The 16-bit value in program memory addresses 40H

and 41H is the subroutine start address.

Figure 3-12. Indirect Addressing

3-12

RELATIVE ADDRESS MODE (RA)

In Relative Address (RA) mode, a twos-complement signed displacement between – 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction immediately following the current instruction.

Several program control instructions use the Relative Address mode to perform conditional jumps. The instructions that support RA addressing are BTJRF, BTJRT, DJNZ, CPIJE, CPIJNE, and JR.

Program Memory

Next OPCODE

Program Memory

Address Used

Current Instruction

Displacement

OPCODE

Current

PC Value

Signed

Displacement Value

+

Sample Instructions:

JR ULT,$+OFFSET ; Where OFFSET is a value in the range +127 to -128

Figure 3-13. Relative Addressing

3-13

ADDRESSING MODES S3F80N8_UM_REV1.10

IMMEDIATE MODE (IM)

In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. The operand may be one byte or one word in length, depending on the instruction used. Immediate addressing mode is useful for loading constant values into registers.

Program Memory

OPERAND

OPCODE

(The Operand value is in the instruction)

Sample Instruction:

LD R0,#0AAH

Figure 3-14. Immediate Addressing

3-14

4

CONTROL REGISTERS

OVERVIEW

In this chapter, detailed descriptions of the S3F80N8 control registers are presented in an easy-to-read format.

You can use this chapter as a quick-reference source when writing application programs. Figure 4-1 illustrates the important features of the standard register description format.

Control register descriptions are arranged in alphabetical order according to register mnemonic. More detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in

Part II of this manual. Data and counter registers are not described in detail in this reference chapter. More information about all of the registers used by a specific peripheral is presented in the corresponding peripheral descriptions in Part II of this manual.

The locations and read/write characteristics of all mapped registers in the S3F80N8 register file are listed in Table

4-1. The hardware reset value for each mapped register is described in Chapter 8, "RESET and Power-Down."

Table 4-1. Registers

Register NAME

Timer 0 Counter Register

Timer 0 Data Register

Timer 0 Control Register

Basic Timer Control Register

Clock Control Register

Mnemonic R/W

T0CNT R

T0DATA R/W

T0CON R/W

BTCON R/W

CLKCON R/W

Address Reset Value(bit)

Decimal Hex 7 6 5 4 3 2 1 0

208 D0H 0 0 0 0 0 0 0 0

209

210

D1H

D2H

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

211

212

D3H 0 0 0 0 0 0 0 0

D4H 0 – – 0 0 – – –

System Flags Register

Register Pointer 0

Register Pointer 1

FLAGS R/W

RP0 R/W

213

214

D5H x x x x x x 0 0

D6H 1 1 0 0 0 – – –

RP1 R/W 215 D7H 1 1 0 0 1 – – –

Location D8H is not mapped.

Stack Pointer Register (Low Byte) SPL R/W

Instruction Pointer (High Byte) IPH R/W

Instruction Pointer (Low Byte) IPL R/W

217

218

219

D9H x

DAH

DBH x x x x x x x x x x x x x x x x x x x x x x x

Interrupt Request Register

Interrupt Mask Register

IRQ

IMR

R

R/W

220

221

DCH 0 0 0 0 0 0 0 0

DDH 0 0 0 0 0 0 0 0

NOTE: - : Not mapped or not used, x: Undefined

4-1

CONTROL REGISTERS S3F80N8_UM_REV1.10

Table 4-1. Registers (continued)

Register NAME

System Mode Register

Register Page Pointer

Port 0 data register

Port 1 data register

Port 2 data register

Port 3 data register

Mnemonic R/W

SYM

PP

R/W

R/W

P0

P1

P2

P3

R/W

R/W

R/W

R/W

Address Reset Value (bit)

Decimal Hex 7 6 5 4 3 2 1 0

222

223

DEH

DFH

0

0

–

0

–

0 x

0 x

0 x

0

0

0

0

0

224

225

226

227

E0H

E1H

E2H

E3H

0

0

–

–

0

0

–

–

0

0

–

0

0

–

0

0

0

0

0 0 0 0

0 0

0

0

0

0

0

0

0

0

Port 0 control register (High byte) P0CONH R/W

Port 0 control register (Low byte) P0CONL R/W

Port 0 pull-up resistor enable register

P0PUR R/W

228

229

E4H

E5H

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

230 E6H 0 0 0 0 0 0 0

Locations E7H is not mapped.

Port 1 control register (High byte) P1CONH R/W 232 E8H 0 0 0 0 0 0 0 0

Port 1 control register (Low byte) P1CONL R/W

Port 1 pull-up resistor enable register

P1PUR R/W

External interrupt enable register EXTINT R/W

233

234

235

E9H

EBH

0

EAH 0

0

0

0

0

0

0

0

0

0

0

0

0 0 0 0

0

0

0

0

0

0

0

External interrupt pending register EXTPND R/W 236 ECH 0 0 0 0 0 0 0 0

Location EDH is not mapped.

Port 2 control register (High byte) P2CONH R/W

Port 2 control register (Low byte) P2CONL R/W

Port 2 pull-up resistor enable register

P2PUR R/W

238

239

240

EEH

EFH

F0H

–

0

–

0

–

–

0

–

0

1

0

0

0

0 0 0 0

0

0

0

0

0

0

Locations F1H is not mapped.

Port 3 control register

Port 3 pull-up resistor enable register

P3CON R/W

P3PUR R/W

242 F2H 0 0 0 0 0 0 0 0

243 F3H – – – 1 1 1 1

STOP control register

Basic timer counter register

Interrupt priority register

Locations F4H-FAH are not mapped.

STOPCON R/W 251 FBH 0 0 0 0 0 0 0 0

Location FCH is not mapped.

BTCNT R 253 FDH 0 0 0 0 0 0 0 0

Location FEH is not mapped.

IPR R/W 255 FFH x x x x x x x x

NOTES:

1. The reset value of P2.5 setting is open-drain output.

2. The reset value of P3PUR is 0FH, this value enables the pull up resistor.

4-2

Bit number(s) that is/are appended to the register name for bit addressing

Register ID Register name

Name of individual bit or related bits

Register address

(hexadecimal)

FLAGS - System Flags Register

Bit Identifier

RESET Value

Read/Write

Bit Addressing

Mode

.7

.6

.5

.7

.6

.5

.4

x

R/W x

R/W x

R/W

Register addressing mode only x

R/W

.3

x

R/W

.2

x

R/W

Carry Flag (C)

0 Operation does not generate a carry or borrow condition

1

Operation generates carry-out or borrow into high-order bit 7

Zero Flag (Z)

0

1

Operation result is a non-zero value

Operation result is zero

Sign Flag (S)

0

1

Operation generates positive number (MSB = "0")

Operation generates negative number (MSB = "1")

D5H

.1

x

R/W

.0

0

R/W

R = Read-only

W = Write-only

R/W = Read/write

'-' = Not used

Type of addressing that must be used to address the bit

(1-bit, 4-bit, or 8-bit)

Description of the effect of specific bit settings

Figure 4-1. Register Description Format

Bit number:

MSB = Bit 7

LSB = Bit 0

RESET value notation:

'-' = Not used

'x' = Undetermined value

'0' = Logic zero

'1' = Logic one

4-3