System Event Log Troubleshooting Guide for Intel® S5500/S3420

Memory Subsystem

Byte Field

12 Sensor Number

13 Event Direction and

Event Type

14 Event Data 1

15 Event Data 2

16 Event Data 3

Description

13h

[7] Event direction

0b = Assertion Event

1b = Deassertion Event

[6:0] Event Type = 09h (digital Discrete)

[7:6] – 10b = OEM code in Event Data 2

[5:4] – 00b = Unspecified Event Data 3

[3:0] – Event Trigger Offset as described in Table 57

Not used

Not used

Table 57: Sparing Configuration Status Sensor Event Trigger Offset – Next Steps

Hex

Event Trigger Offset

Description

01h The system has configured into

Spare Channel RAS mode.

00h The system has configured out of

Spare Channel RAS mode

Description

Sparing mode is enabled in setup.

Sparing mode is disabled, either from setup or due to error in which case post error

8500 also occurs.

Informational event only.

Next Steps

1. If this event is accompanied by a post error 8500, there was a problem applying the sparing configuration to the memory. Check for other errors related to the memory and troubleshoot accordingly.

2. If there is no post error then sparing mode was simply disabled in BIOS setup and this should be considered informational only.

7.1.4 Sparing Redundancy State Sensor

This sensor provides the RAS Redundancy state for the Spare Channel Mode.

50 Intel order number G74211-002 Revision 1.1

System Event Log Troubleshooting Guide for Intel

®

Byte

8

9

Field

Generator ID

11 Sensor Type

12 Sensor Number

13 Event Direction and

Event Type

14 Event Data 1

15 Event Data 2

Table 58: Sparing Redundancy State Sensor Typical Characteristics

Description

0001h = BIOS POST

0ch = Memory

11h

[7] Event direction

0b = Assertion Event

1b = Deassertion Event

[6:0] Event Type = 0Bh (Generic Discrete)

[7:6] – 10b = OEM code in Event Data 2

[5:4] – 10b = OEM code in Event Data 3

[3:0] – Event Trigger Offset as described in Table 59

[7:4] – If Domain Instance Type (ED3) is set to Local, this field specifies the 0-based Socket ID of the processor that contains the sparing domain local sub-instances.

A value of 1110b indicates that the sparing configuration specified in Bits [3:0] applies globally to all sockets in the system.

If Domain Instance Type (ED3) is set to Global, this field specifies the 0-based Socket

ID of the second participant processor in this sparing domain global instance.

A value of 1111b indicates that this field is unused and does not contain valid data.

[3:0] – If Domain Instance Type (ED3) is set to Local, this field specifies the sparing domain local sub-instances – which channels are included in this sub-instance:

0000b – Reserved

0001b – {Ch A, Ch B, Ch C} (only configuration possible on Intel

®

S5500/S5520

Server Boards)

0010b-1110b – Reserved

If Domain Instance Type (ED3) is set to Global, this field specifies the 0-based Socket

ID of the first participant processor in this sparing domain global instance.

A value of 1111b indicates that this field is unused and does not contain valid data.

Memory Subsystem

Revision 1.1 Intel order number G74211-002 51

Memory Subsystem

Byte Field

16 Event Data 3

Description

[7] – Domain Instance Type

0b: Local memory sparing domain instance. This SEL pertains to a local memory sparing domain that is restricted to memory sparing pairs within a processor socket only.

1b: Global memory sparing domain instance. This SEL pertains to a global memory sparing domain that pertains to memory sparing between processor sockets.

[6:4] – Reserved

[3:0] – 0-based Instance ID of this sparing domain

Table 59: Sparing Redundancy State Sensor Event Trigger Offset – Next Steps

Hex

Event Trigger Offset

Description

01h Memory is configured in Spare

Channel Mode, and the memory is operating in the fully redundant state, with the spare channel inactive and available.

00h Memory is configured in Spare

Channel Mode, and the memory has lost redundancy and is operating in the degraded state, with the spare channel active and used to replace a failed channel.

Description

System boots with spare channel mode active, one entry per processor.

Spare channel replaces failing channel, one SEL entry for processor with failing memory to signify loss of redundancy.

Informational event.

Next Steps

This event should be accompanied by memory errors indicating the source of the issue. Troubleshoot accordingly (probably replace affected DIMM).

52 Intel order number G74211-002 Revision 1.1