I²C bus specification STA333BW
Following the START condition the master sends a device select code with the RW bit set to 0. The STA333BW acknowledges this and then waits for the byte of internal address.
After receiving the internal byte address the STA333BW again responds with an acknowledgment.
In the byte write mode the master sends one data byte, this is acknowledged by the
STA333BW. The master then terminates the transfer by generating a STOP condition.
The multi-byte write modes can start from any internal address. The master generating a
STOP condition terminates the transfer.
BYTE
WRITE
MULTIBYTE
WRITE
START
START
DEV-ADDR
DEV-ADDR
RW
Figure 9. Write mode sequence
ACK ACK ACK
SUB-ADDR DATA IN
STOP
ACK ACK ACK
SUB-ADDR DATA IN
RW
DATA IN
ACK
STOP
6.4.1
6.4.2
6.4.3
Current address byte read
Following the START condition the master sends a device select code with the RW bit set to 1. The STA333BW acknowledges this and then responds by sending one byte of data.
The master then terminates the transfer by generating a STOP condition.
Current address multi-byte read
The multi-byte read modes can start from any internal address. Sequential data bytes are read from sequential addresses within the STA333BW. The master acknowledges each data byte read and then generates a STOP condition terminating the transfer.
Random address byte read
Following the START condition the master sends a device select code with the RW bit set to 0. The STA333BW acknowledges this and then the master writes the internal address byte. After receiving, the internal byte address the STA333BW again responds with an acknowledgement. The master then initiates another START condition and sends the device select code with the RW bit set to 1. The STA333BW acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition.
20/68 DocID13773 Rev 5
