STMicroelectronics VNQ5E050AK-E Datasheet
Mainos
Mainos
VNQ5E050AK-E
Quad channel high-side driver with analog current sense for automotive applications
Features
Max supply voltage
Operating voltage range
V
CC
V
CC
Max on-state resistance (per ch.) R
ON
Current limitation (typ) I
LIMH
Off-state supply current I
S
1.
Typical value with all loads connected.
41 V
4.5 to 28 V
50 m
27 A
2 µA
(1)
■
■
■
General
– Inrush current active management by power limitation
– Very low standby current
– 3.0 V CMOS compatible inputs
– Optimized electromagnetic emissions
– Very low electromagnetic susceptibility
– Compliance with European directive
2002/95/EC
– Very low current sense leakage
Diagnostic functions
– Proportional load current sense
– High current sense precision for wide currents range
– Current sense disable
– Off-state open-load detection
– Output short to V
CC
detection
– Overload and short to ground (power limitation) indication
– Thermal shutdown indication
Protections
– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss of V
CC
– Overtemperature shutdown with auto restart (thermal shutdown)
PowerSSO-24
– Reverse battery protected
– Electrostatic discharge protection
Application
■
■
All types of resistive, inductive and capacitive loads
Suitable as LED driver
Description
The VNQ5E050AK-E is a quad channel high-side driver manufactured using ST proprietary
VIPower™ M0-5 technology and housed in
PowerSSO-24 package. The device is designed to drive 12 V automotive grounded loads, and to provide protection and diagnostics. It also implements a 3 V and 5 V CMOS compatible interface for the use with any microcontroller.
The device integrates advanced protective functions such as load current limitation, inrush and overload active management by power limitation, overtemperature shut-off with auto-restart and overvoltage active clamp.
A dedicated analog current sense pin is associated with every output channel providing enhanced diagnostic functions including fast detection of overload and short-circuit to ground through power limitation indication, overtemperature indication, short-circuit to V
CC diagnosis and on-state and off-state open-load detection. The current sensing and diagnostic feedback of the whole device can be disabled by pulling the CS_DIS pin high to share external sense resistor with similar devices.
September 2013 Doc ID 13519 Rev 7 1/37 www.st.com
1
Contents
Contents
VNQ5E050AK-E
Block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 24
Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 24
Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 25
Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Short to VCC and off-state open-load detection . . . . . . . . . . . . . . . . . . 27
Maximum demagnetization energy (VCC = 13.5 V) . . . . . . . . . . . . . . . . . 28
Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
®
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PowerSSO-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2/37 Doc ID 13519 Rev 7
VNQ5E050AK-E
List of tables
List of tables
CC
= 13 V; T j
= 25 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
< 18 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CC
<18V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Doc ID 13519 Rev 7 3/37
List of figures
List of figures
VNQ5E050AK-E
OUT
/I
SENSE
vs I
OUT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
j
evolution in overload or short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
case
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
LIMH
vs T case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Rthj-amb vs PCB copper area in open box free air condition (one channel ON) . . . . . . . . 29
PowerSSO-24 thermal impedance junction ambient single pulse (one channel ON). . . . . 30
4/37 Doc ID 13519 Rev 7
VNQ5E050AK-E
1
Block diagram and pin configuration
Block diagram and pin configuration
Figure 1.
Block diagram
CS_
DIS
CS1
CS2
CS3
CS4
IN1
IN2
IN3
IN4
V
CC
Signal Clamp
Undervoltage
LOGIC
Control & Diagnostic 1
Power
Clamp
DRIVER
V
ON
Limitation
Over temp.
Current
Limitation
OFF State
Open load
V
SENSEH
Current
Sense
OVERLOAD PROTECTION
(ACTIVE POWER LIMITATION)
CH 1
GND
CH 2
CH 3
CH 4
OUT4
OUT3
OUT2
OUT1
Table 1.
Name
V
CC
OUTPUT n
GND
INPUT n
Pin functions
Function
Battery connection.
Power output.
Ground connection. Must be reverse battery protected by an external diode/resistor network.
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state.
CURRENT
SENSE n
CS_DIS
Analog current sense pin, delivers a current proportional to the load current.
Active high CMOS compatible pin, to disable the current sense pin.
Doc ID 13519 Rev 7 5/37
Block diagram and pin configuration
Figure 2.
Configuration diagram (top view)
V
CC
GND
INPUT1
CURRENT SENSE1
INPUT2
CURRENT SENSE2
INPUT3
CURRENT SENSE3
INPUT4
CURRENT SENSE4
CS_DIS.
V
CC
VNQ5E050AK-E
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT3
OUTPUT3
OUTPUT3
OUTPUT4
OUTPUT4
OUTPUT4
TAB = V
CC
Table 2.
Connection / pin Current sense N.C.
Floating
Suggested connections for unused and not connected pins
To ground
Not allowed
Through 1 k
resistor
X
X
Output Input CS_DIS
X
Through 22 k
resistor
X
Through 10 k
resistor
X
Through 10 k
resistor
6/37 Doc ID 13519 Rev 7
VNQ5E050AK-E Electrical specifications
Figure 3.
Current and voltage conventions
V
CSD
I
CSD
V
CC
OUTPUTn
V
Fn
CS_DIS
V
INn
I
INn
INPUTn
GND
CURRENT
SENSEn
I
GND
I
SENSEn
V
SENSEn
I
S
I
OUTn
V
OUTn
V
CC
Note:
2.1
V
Fn
= V
OUTn
- V
CC
during reverse battery condition.
Absolute maximum ratings
Stressing the device above the ratings listed in the “Absolute maximum ratings” tables may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to the conditions reported in this section for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 3.
Symbol
Absolute maximum ratings
Parameter
V
CC
-V
CC
-I
GND
I
OUT
-I
OUT
I
IN
I
CSD
-I
CSENSE
DC supply voltage
Reverse DC supply voltage
DC reverse ground pin current
DC output current
Reverse DC output current
DC input current
DC current sense disable input current
DC reverse CS pin current
V
CSENSE
Current sense maximum voltage
Value Unit
41
0.3
V
V
200 mA
Internally limited A
20
-1 to 10
-1 to 10
200
V
CC
- 41 to
+V
CC
V
A mA mA mA
Doc ID 13519 Rev 7 7/37
Electrical specifications
Table 3.
Symbol
E
MAX
V
ESD
V
ESD
T j
T stg
Absolute maximum ratings (continued)
Parameter
Maximum switching energy (single pulse)
(L = 3 mH; R
L
I
OUT
= I limL
= 0
(Typ.))
; V bat
= 13.5 V; T jstart
= 150 °C;
Electrostatic discharge
(human body model: R = 1.5 K
C = 100 pF)
– Input
– Current sense
– CS_DIS
– Output
– V
CC
Charge device model (CDM-AEC-Q100-011)
Junction operating temperature
Storage temperature
VNQ5E050AK-E
Value
104
Unit mJ
4000
2000
4000
5000
5000
750
-40 to 150
-55 to 150
V
V
V
V
V
V
°C
°C
Table 4.
Symbol
R thj-case
R thj-amb
Thermal data
Parameter
Thermal resistance junction-case (with one channel ON)
Thermal resistance junction-ambient
Max. value
2.8
Unit
°C/W
°C/W
Values specified in this section are for 8 V < V
CC otherwise stated.
< 28 V, -40 °C < T j
< 150 °C, unless
Table 5.
Symbol
Power section
Parameter
V
CC
V
USD
Operating supply voltage
Undervoltage shutdown
V
USDhyst
Undervoltage shutdown hysteresis
Test conditions Min. Typ. Max. Unit
4.5
13 28
2.5
3.5
4.5
V
V
0.5
V
R
ON
On-state resistance
(1)
V clamp
Clamp voltage
I
OUT
= 2 A; T j
= 25 °C
I
OUT
= 2 A; T j
= 150 °C
I
OUT
= 2 A; V
CC
= 5 V; T j
= 25 °C
I
S
= 20 mA 41 46
50
100
65
52 m
V
8/37 Doc ID 13519 Rev 7
VNQ5E050AK-E Electrical specifications
Table 5.
Symbol
Power section (continued)
Parameter Test conditions
I
I
L(off)
V
S
F
Supply current
Off-state; V
CC
V
IN
= V
OUT
= V
= 13 V; T
SENSE j
= 25 °C;
= V
CSD
= 0 V
I
On-state; V
CC
OUT
= 0 A
= 13 V; V
IN
= 5 V;
V
IN
T j
= V
OUT
= 25 °C
= 0 V; V
CC
= 13 V;
Off-state output current
(1)
V
IN
T j
= V
OUT
= 125 °C
= 0 V; V
CC
= 13 V;
Output - V voltage
(1)
CC
diode
-I
OUT
= 2 A; T j
= 150 °C
1.
For each channel
2.
PowerMOS leakage included.
Min. Typ. Max. Unit
0
2
(2)
8
5
(2)
µA
14 mA
0 0.01
3
5
0.7
µA
V
Table 6.
Symbol t d(on) t d(off)
Switching (V
CC
= 13 V; T j
= 25 °C)
Parameter Test conditions
Turn-on delay time
Turn-off delay time
R
L
= 6.5
(see
R
L
= 6.5
(see
(dV
OUT
/dt) on
Turn-on voltage slope R
L
= 6.5
Min.
Typ.
20
35
See
See
Max.
Unit
µs
µs
V
V
µs
µs (dV
OUT
/dt) off
Turn-off voltage slope R
L
= 6.5
W
ON
W
OFF
Switching energy losses during t won
Switching energy losses during t woff
R
L
= 6.5
)
R
L
= 6.5
)
0.15
0.25
mJ mJ
Table 7.
Symbol
V
IL
I
IL
V
IH
I
IH
V
I(hyst)
Logic inputs
Parameter
Input low level voltage
Low level input current
Input high level voltage
High level input current
Input hysteresis voltage
V
ICL
Input clamp voltage
V
CSDL
I
CSDL
V
CSDH
CS_DIS low level voltage
Low level CS_DIS current
CS_DIS high level voltage
Test conditions
V
IN
= 0.9 V
V
IN
= 2.1 V
I
IN
= 1 mA
I
IN
= -1 mA
V
CSD
= 0.9 V
Min.
Typ.
Max.
Unit
0.9
1
2.1
0.25
5.5
10
7
V
µA
V
µA
V
V
-0.7
1
2.1
0.9
V
µA
V
Doc ID 13519 Rev 7 9/37
Electrical specifications
Table 7.
Symbol
Logic inputs (continued)
Parameter
I
CSDH
V
CSD(hyst)
High level CS_DIS current
CS_DIS hysteresis voltage
Test conditions
V
CSD
= 2.1 V
V
CSCL
CS_DIS clamp voltage
I
CSD
= 1 mA
I
CSD
= -1 mA
VNQ5E050AK-E
Min.
Typ.
Max.
Unit
0.25
5.5
10
7
µA
V
V
-0.7
Table 8.
Symbol
Protections and diagnostics (1)
Parameter Test conditions
I limH
DC short circuit current
V
CC
= 13 V
5 V < V
CC
< 28 V
I
T limL
T
TSD
T
R
RS
Short circuit current during thermal cycling
Shutdown temperature
Reset temperature
Thermal reset of
STATUS
V
CC
= 13 V; T
R
< T j
T
HYST
V
DEMAG
Thermal hysteresis
(T
TSD
-T
R
)
Turn-off output voltage clamp
I
OUT
= 2 A; V
L = 6 mH
IN
= 0;
< T
TSD
V
ON
Output voltage drop limitation
I
OUT
T j
= 0.1 A;
= -40 °C...150 °C
(see
)
Min.
19
Typ.
27
7
150 175
T
RS
+ 1 T
RS
+ 5
135
7
25
Max.
Unit
38
38
A
A
A
200
°C
V
CC
-41 V
CC
-46 V
CC
-52 V mV
°C
°C
°C
1.
To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles.
Table 9.
Symbol
K
0
K
1
Current sense (8 V < V
CC
< 18 V)
Parameter Test conditions
I
OUT
/I
SENSE
I
OUT
/I
SENSE dK
1
/K
1
(1)
Current sense ratio drift
I
OUT
= 0.05 A;
V
SENSE
= 0.5 V; V
CSD
= 0 V;
T j
= -40 °C...150 °C
I
OUT
= 1 A;
V
SENSE
= 4V; V
CSD
= 0 V;
T j
= -40 °C...150 °C
T j
= 25 °C...150 °C
I
OUT
= 1 A; V
SENSE
= 4 V;
V
CSD
= 0 V;
T j
= -40 °C to 150 °C
Min. Typ. Max. Unit
1050 2110 3170
1510
1510
1890
1890
2650
2270
-13 13 %
10/37 Doc ID 13519 Rev 7
VNQ5E050AK-E Electrical specifications
Table 9.
Symbol
Current sense (8 V < V
CC
< 18 V) (continued)
Parameter Test conditions Min. Typ. Max. Unit dK dK
I
K
K
2
2
/K
3
3
/K
2
(1)
3
(1)
SENSE0
I
I
OUT
Current sense ratio drift
OUT
Current sense ratio drift
/I
/I
SENSE
SENSE
Analog sense leakage current
I
OUT
= 2 A;
V
SENSE
= 4 V; V
CSD
= 0 V;
T j
= -40 °C...150 °C
T j
= 25 °C...150 °C
I
OUT
= 2 A; V
SENSE
= 4 V;
V
CSD
= 0 V;
T j
= -40 °C to 150 °C
I
OUT
= 4 A;
V
SENSE
= 4 V; V
CSD
= 0 V;
T j
= -40 °C...150 °C
T j
= 25 °C...150 °C
I
OUT
= 4 A; V
SENSE
= 4 V;
V
CSD
= 0 V;
T j
= -40 °C to 150 °C
I
OUT
= 0 A; V
SENSE
= 0 V;
V
CSD
T j
= 5 V; V
IN
= 0 V;
= -40 °C...150 °C
I
OUT
V
CSD
= 0 A; V
SENSE
= 0 V; V
IN
= 0 V;
= 5 V;
T j
= -40 °C...150 °C
I
OUT
V
CSD
= 2 A; V
SENSE
= 5 V; V
IN
= 0 V;
= 5 V;
T j
= -40 °C...150 °C
1600
1600
-8
1620
1620
-6
0
0
0 t t
V
I
OL
SENSE
DSENSE1L
DSENSE2H
Open-load on-state current detection threshold
Max analog sense output voltage
Delay response time from rising edge of
CS_DIS pin
Delay response time from rising edge of
INPUT pin
I
V
IN
= 5 V; 8 V < V
I
SENSE
OUT
= 5 µA
= 4 A; V
CSD
CC
< 18 V;
4
= 0 V 5 t
V
SENSEH
I
SENSEH
Analog sense output voltage in fault condition
(2)
Analog sense output current in fault condition
(2)
V
CC
= 13 V; R
SENSE
= 10 K
V
CC
= 13 V; V
SENSE
= 5 V
DSENSE1H
Delay response time from falling edge of
CS_DIS pin
V
SENSE
< 4 V, 0.5 A < I
OUT
< 4 A
I
SENSE
= 90 % of I
SENSEMAX
(see
)
V
SENSE
< 4 V; 0.5 A < I
OUT
< 4 A
I
SENSE
= 10 % of I
SENSEMAX
(see
)
V
SENSE
< 4 V, 0.5 A < I
OUT
< 4 A
I
SENSE
= 90 % of I
SENSEMAX
(see
)
1800
1800
1770
1770
8
9
40
5
80
2230
2000
8
1990
1920
6
1
2
1
20
100
20
250
%
%
µA mA
V
V mA
µs
µs
µs
Doc ID 13519 Rev 7 11/37
Electrical specifications VNQ5E050AK-E
Table 9.
Symbol
Current sense (8 V < V
CC
< 18 V) (continued)
Parameter Test conditions Min. Typ. Max. Unit
t
DSENSE2H
Delay response time between rising edge of output current and rising edge of current sense t
DSENSE2L
Delay response time from falling edge of
INPUT pin
V
SENSE
< 4 V,
I
SENSE
= 90 % of I
SENSEMAX,
I
I
OUT
= 90 % of I
OUTMAX
OUTMAX
= 2 A (see
)
V
SENSE
< 4 V, 0.5 A < I
OUT
< 4 A
I
SENSE
= 10 % of I
SENSEMAX
(see
)
80
1.
Parameter guaranteed by design; it is not tested.
2.
Fault condition includes: power limitation, overtemperature and open-load off-state detection.
60
250
µs
µs
Table 10.
Open-load detection (8V<V
CC
<18V)
Symbol Parameter Test conditions
V
OL t
DSTKON
I
L(off2)r
I
L(off2)f
Open-load off-state voltage detection threshold
Output short circuit to V cc detection delay at turn-off
Off-state output current at
V
OUT
= 4 V
Off-state output current at
V
OUT
= 2 V
V
IN
= 0 V
Min.
Typ.
Max. Unit
2
See
4 V
180
V
IN
= 0 V; V
SENSE
= 0 V;
V
OUT rising from 0 V to 4 V
V
IN
= 0 V;
V
SENSE
= V
SENSEH
V
OUT falling from V
CC
to 2 V
-120
-50
1200 µs
0 µA
90 µA td_vol
Delay response from output rising edge to V
SENSE rising edge in open-load
V
OUT
= 4 V; V
IN
= 0 V
V
SENSE
= 90 % of V
SENSEH
20 µs
Figure 4.
Current sense delay characteristics
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT t
DSENSE2H t
DSENSE1L t
DSENSE1H t
DSENSE2L
12/37 Doc ID 13519 Rev 7
VNQ5E050AK-E Electrical specifications
Figure 5.
Open-load off-state delay timing
OUTPUT STUCK TO V
CC
V
IN
V
OUT
> V
OL
V
SENSEH
V
CS t
DSTKON
Figure 6.
Switching characteristics
V
OUT t
Won
80% dV
OUT
/dt
(on) t r
10%
INPUT t d(on) t d(off) t
Woff
90% t f dV
OUT
/dt
(off) t t
Doc ID 13519 Rev 7 13/37
Electrical specifications VNQ5E050AK-E
Figure 7.
Delay response time between rising edge of output current and rising edge of current sense (CS enabled)
V
IN
t
DSENSE2H t
I
OUT
90% I
OUTMAX
I
OUTMAX t
I
SENSE I
SENSEMAX
90% I
SENSEMAX t
Figure 8.
Output voltage drop limitation
V
CC
-V
OUT
T j
= 150 °C T j
= 25 °C
T j
= -40 °C
V
ON
V
ON
/R
ON
(T)
I
OUT
14/37 Doc ID 13519 Rev 7
VNQ5E050AK-E
Figure 9.
I
OUT
/I
SENSE
vs I
OUT
I out
/ I sense
2800
2600 max T j
= -40 °C to 150 °C
2400
2200 max T j
= 25 °C to 150 °C
Note:
2000
1800
1600
1400 min T j
= 25 °C to 150 °C = min T j
= -40 °C to 150 °C typical value
1200
1 1,5 2 2,5
I
OUT
(A)
3
Figure 10. Maximum current sense ratio drift vs load current dk/k(%)
20
15
10
5
0
-5
-10
-15
-20
1 2
I
OUT
(A)
Parameter guaranteed by design; it is not tested.
3
Electrical specifications
3,5
4
4
Doc ID 13519 Rev 7 15/37
Electrical specifications VNQ5E050AK-E
Table 11.
Truth table
Conditions
Normal operation
Overtemperature
Undervoltage
Overload
Input
L
H
L
H
L
H
H
H
Output
L
L
L
H
L
L
X
(no power limitation)
Cycling
(power limitation)
L
L
Sense (V
CSD
= 0 V)
(1)
0
Nominal
0
V
SENSEH
0
0
Nominal
V
SENSEH
Short circuit to GND
(power limitation)
Open-load off-state
(with external pull-up)
Short circuit to V
CC
(external pull-up disconnected)
Negative output voltage clamp
L
H
L
L
H
L
H
H
H
L
V
V
V
0
SENSEH
SENSEH
SENSEH
< Nominal
0
1.
If the V
CSD
is high, the SENSE output is at a high impedance, its potential depends on leakage currents and external circuit.
16/37 Doc ID 13519 Rev 7
VNQ5E050AK-E Electrical specifications
Table 12.
Electrical transient requirements (part 1)
ISO 7637-2:
2004(E)
Test pulse
III
Test levels
(1)
IV
Number of pulses or test times
Burst cycle/pulse repetition time
Min.
Max.
1
2a
3a
3b
4
5b
(2)
-75V
+37V
-100V
+75V
-6V
+65V
-100V
+50V
-150V
+100V
-7V
+87V
5000 pulses
5000 pulses
1h
1h
1 pulse
1 pulse
0.5s
0.2s
90ms
90ms
5s
5s
100ms
100ms
1.
The above test levels must be considered referred to V
CC
= 13.5V except for pulse 5b.
2.
Valid in case of external load dump clamp: 40V maximum referred to ground.
Delays and impedance
2 ms, 10
50µs, 2
0.1µs, 50
0.1µs, 50
100ms, 0.01
400ms, 2
Table 13.
Electrical transient requirements (part 2)
ISO 7637-2:
2004E
Test pulse III
Test level results
1
2a
3a
3b
4
5b
(1)
C
C
C
C
C
C
1.
Valid in case of external load dump clamp: 40V maximum referred to ground.
VI
C
C
C
C
C
C
Table 14.
Electrical transient requirements (part 3)
Class Contents
C
E
All functions of the device performed as designed after exposure to disturbance.
One or more functions of the device did not perform as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
Doc ID 13519 Rev 7 17/37
Electrical specifications
2.4 Waveforms
Figure 11. Normal operation
Normal operation
18/37
INPUT
I
OUT
Nominal load Nominal load
V
SENSE
V
CS_DIS
Figure 12. Overload or short to GND
Overload or Short to GND
INPUT
I
LimH
>
I
OUT
Power Limitation
I
LimL
>
Thermal cycling
V
SENSE
V
CS_DIS
Doc ID 13519 Rev 7
VNQ5E050AK-E
VNQ5E050AK-E
Figure 13. Intermittent overload
Intermittent Overload
Electrical specifications
INPUT
I
LimH
>
I
OUT
V
SENSEH
>
V
SENSE
Overload
I
LimL
>
V
CS_DIS
Figure 14. Off-state open-load with external circuitry
OFF-State Open Load with external circutry
Nominal load
INPUT
V
OUT
I
OUT
V
SENSE
V
CS_DIS
V
OL
V
OUT
V
SENSEH
> t
DSTK(on)
> V
OL
Doc ID 13519 Rev 7 19/37
Electrical specifications
Figure 15. Short to V
CC
Resistive
Short to V
CC
Short to V
CC
Hard
Short to V
CC
VNQ5E050AK-E
20/37
V
OUT
I
OUT
V
OL
V
OUT
> V
OL t
DSTK(on) t
DSTK(on)
V
CS_DIS
Figure 16. T j
evolution in overload or short to GND
T
J
evolution in
Overload or Short to GND
INPUT
Self-limitation of fast thermal transients T
TSD
T
R
T
J
I
LimH
>
T
J_START
Power Limitation
T
HYST
< I
LimL
I
OUT
Doc ID 13519 Rev 7
VNQ5E050AK-E Electrical specifications
Figure 17. Off-state output current
Iloff (nA)
700
600
500
400
300
200
100
Off State
Vcc=13V
Vin=Vout=0V
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Figure 19. Input clamp voltage
Vicl (V)
7
6,8
6,6
6,4
6,2
6
5,8
5,6 lin=1mA
5,4
5,2
5
-50 -25 0 25 50 75
Tc (°C)
Figure 21. Input high level
100 125 150 175
Vih (V)
4
3,5
3
2,5
2
1,5
1
0,5
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Figure 18. High level input current
Iih (µA)
5
4,5
Vin=2.1V
4
3,5
3
2,5
2
1,5
1
0,5
0
-50 -25 0 25 50 75
Tc (°C)
Figure 20. Input low level
100 125 150 175
Vihyst (V)
1
0,9
0,8
0,7
0,6
0,5
0,4
0,3
0,2
0,1
0
-50 -25
Vil (V)
2
1,8
1,6
1,4
1,2
1
0,8
0,6
0,4
0,2
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Figure 22. Input hysteresis voltage
0 25 50 75
Tc (°C)
100 125 150 175
Doc ID 13519 Rev 7 21/37
Electrical specifications VNQ5E050AK-E
Figure 23. On-state resistance vs T case
Ron (mOhm)
150
120
Iout= 2A
Vcc=13V
Figure 24. On-state resistance vs V
CC
Ron (mOhm)
100
80
Tc=150°C
Tc=125°C
90 60
Tc=25°C
60 40
Tc=-40°C
30 20
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Figure 25. Undervoltage shutdown
0
0 5 10 15 20
Vcc (V)
25 30
Figure 26. Turn-on voltage slope
35 40
4
2
10
8
6
Vusd (V)
16
14
12
0
-50 -25 0 25 50 75
Tc (°C)
Figure 27. I
LIMH
vs T case
Ilimh (A)
40
35
30
25
20
15
Vcc=13V
100 125 150 175
10
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
(dVout/dt )On (V/ms)
1000
900
800
700
600
500
400
300
200
100
Vcc=13V
RI=6.5 Ohm
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Figure 28. Turn-off voltage slope
(dVout/dt )Off (V/ms)
600
550
500
450
400
350
300
250
200
150
100
50
0
-50 -25 0 25
Vcc=13V
RI= 6.5 Ohm
50 75
Tc (°C)
100 125 150 175
22/37 Doc ID 13519 Rev 7
VNQ5E050AK-E Electrical specifications
Figure 29. CS_DIS high level voltage
Vcsdh (V)
4
3,5
3
2,5
2
1,5
1
0,5
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Figure 31. CS_DIS low level voltage
Vcsdl (V)
3
Figure 30. CS_DIS clamp voltage
6
5
4
3
2
1
0
-50
Vcsdcl(V)
10
9
8
7
-25 0
Iin = 1 mA
25 50 75
Tc (°C)
100 125 150 175
2,5
2
1,5
1
0,5
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Doc ID 13519 Rev 7 23/37
Application information VNQ5E050AK-E
Figure 32. Application schematic
+5V
V
CC
R prot
CS_DIS
CU
C
R prot
R prot
IINPUT
R
CURRENT SENSE
SENSE
GND
V
GND
R
GND ext
D
GND
OUTPUT
D ld
Note:
3.1
Channel 2, 3, 4 have the same internal circuit as channel 1.
GND protection network against reverse battery
This section provides two solutions for implementing a ground protection network against reverse battery.
resistor in the ground line (R
GND
only)
This can be used with any type of load.
The following is an indication on how to dimension the R
GND resistor.
1.
R
GND
600 mV / (I
S(on)max
).
2. R
GND
V
CC
) / (-I
GND
) where -I
GND
is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet.
Power Dissipation in R
GND
(when V
CC
< 0: during reverse battery situations) is:
Equation 1
P
D
= (-V
CC
)
2
/R
GND
24/37 Doc ID 13519 Rev 7
VNQ5E050AK-E
3.1.2
Application information
This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where I
S(on)max
becomes the sum of the maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the
R
GND will produce a shift (I
S(on)max
* R
GND
) in the input thresholds and the status output values. This shift will vary depending on how many devices are on in the case of several high side drivers sharing the same R
GND
.
If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize
Section 3.1.2: Solution 2: diode (DGND) in the ground line
.
Solution 2: diode (D
GND
) in the ground line
A resistor (R
GND inductive load.
= 1 k
should be inserted in parallel to D
GND
if the device drives an
This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift (
600mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network.
3.3
D ld
is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the
V
CC
max DC rating. The same applies if the device is subject to transients on the V
CC
line that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
MCU I/Os protection
If a ground protection network is used and negative transients are present on the V
CC
line, the control pins will be pulled negative. ST suggests to insert a resistor (R prot
) in line to prevent the microcontroller I/O pins to latch-up.
The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os.
Equation 2
-V
CCpeak
/I latchup
R prot
(V
OH
C
- V
IH
- V
GND
) / I
IHmax
Calculation example:
For V
CCpeak
= -100 V and I latchup
20 mA; V
OH
C
4.5 V
5 k
R prot
180 k
.
Recommended values: R prot
= 10 k
C
EXT
= 10 nF .
Doc ID 13519 Rev 7 25/37
Application information
3.4 Current sense and diagnostic
VNQ5E050AK-E
The current sense pin performs a double function (see
Figure 33: Current sense and diagnostic
):
●
●
Current mirror of the load current in normal operation, delivering a current proportional to the load one according to a known ratio K
X
.
The current I
SENSE
can be easily converted to a voltage V
SENSE
by means of an external resistor R
SENSE
. Linearity between I
OUT
and V
SENSE
is ensured up to 5V minimum (see parameter V
SENSE
in Table 9: Current sense (8 V < V
). The current sense accuracy depends on the output current (refer to current sense electrical characteristics
Table 9: Current sense (8 V < V
).
Diagnostic flag in fault conditions , delivering a fixed voltage V
SENSEH
up to a maximum current I
SENSEH
in case of the following fault conditions (refer to Truth table
):
– Power limitation activation
– Overtemperature
– Short to V
CC
in off-state
– Open-load in off-state with additional external components.
A logic level high on CS_DIS pin sets at the same time all the current sense pins of the device in a high impedance state, thus disabling the current monitoring and diagnostic detection. This feature allows multiplexing of the microcontroller analog inputs by sharing of sense resistance and ADC line among different devices.
Figure 33. Current sense and diagnostic
V
BAT
I
OUT
/K
X
CS_DIS
41V
I
SENSEH
R
PROT
To uC ADC
R
SENSE
CURRENT
SENSEn
V
SENSEH
V
SENSE
V
CC
Main MOSn
PU_CMD
Overtemperature
OL OFF
Pwr_Lim
INPUTn
+
-
R
PU
V
OL
OUTn
I
Loff2r
I
Loff2f
GND
R
PD
V
PU
Load
26/37 Doc ID 13519 Rev 7
VNQ5E050AK-E Application information
3.4.1 Short
CC
and off-state open-load detection
Short to V
CC
A short circuit between V
CC and output is indicated by the relevant current sense pin set to
V
SENSEH
during the device off-state. Small or no current is delivered by the current sense during the on-state depending on the nature of the short circuit.
Off-state open-load with external circuitry
Detection of an open-load in off mode requires an external pull-up resistor R
PU
connecting the output to a positive supply voltage V
PU
.
It is preferable V
PU
to be switched off during the module standby mode in order to avoid the overall standby current consumption to increase in normal conditions, i.e. when load is connected.
An external pull down resistor R
PD
connected between output and GND is mandatory to
).
R
PD
must be selected in order to ensure V
OUT
< circuitry:
V
OLmin
unless pulled up by the external
Equation 3
V
OUT
Pull up _ OFF
R
PD
I
L ( off 2 ) f
V
OL min
2 V
R
PD
22
K is recommended.
For proper open-load detection in off-state, the external pull-up resistor must be selected according to the following formula:
Equation 4
V
OUT
Pull up _ ON
R
PD
V
PU
R
R
PU
PU
R
PD
R
PD
I
L ( off 2 ) r V
OL max
4 V
For the values of V
OLmin
,V
OLmax
,
I
L(off2)r and I
L(off2)f see
Doc ID 13519 Rev 7 27/37
Application information
3.5 Maximum demagnetization energy (V
CC
= 13.5 V)
VNQ5E050AK-E
Figure 34. Maximum turn-off current versus inductance (for each channel)
100
10
C
A
B
1
0,1 1 L (mH) 10
A: T jstart
= 150°C single pulse
B: T jstart
= 100°C repetitive pulse
C: T jstart
= 125°C repetitive pulse
V
IN
, I
L
Demagnetization Demagnetization
100
Demagnetization t
Note: Values are generated with R
L
= 0
In case of repetitive pulses, T jstart
(at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B.
28/37 Doc ID 13519 Rev 7
VNQ5E050AK-E
4
Package and PC board thermal data
Package and PC board thermal data
4.1 PowerSSO-24 thermal data
Figure 35. PowerSSO-24 PC board
Note: Layout condition of R th
and Z th
measurements (PCB: Double layer, Thermal Vias, FR4 area = 77 mm x 86 mm, PCB thickness = 1.6 mm, Cu thickness = 70 µm (front and back side), Copper areas: from minimum pad lay-out to 8 cm
2
).
Figure 36. R thj-amb
vs PCB copper area in open box free air condition (one channel ON)
RTHj_amb(°C/W)
55
50
45
40
35
30
0 2 4 6
PCB Cu heatsink area (cm^2)
8 10
Doc ID 13519 Rev 7 29/37
Package and PC board thermal data VNQ5E050AK-E
Figure 37. PowerSSO-24 thermal impedance junction ambient single pulse (one channel ON)
ZTH (°C/W)
1000
100
10
1
0.1
0.0001
0.001
0.01
0.1
Time (s)
1 10 100 1000
Figure 38. Thermal fitting model of a double channel HSD in PowerSSO-24
Footprint
2 cm
2
8 cm
2
Note: The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
30/37 Doc ID 13519 Rev 7
VNQ5E050AK-E Package and PC board thermal data
Equation 5: pulse calculation formula
Z
TH
= R
TH
+ Z
THtp
1 –
where
= t
P
/T
Table 15.
Thermal parameters
Area/island (cm
2
)
R1 = R7 = R9 = R11 (°C/W)
R2 = R8 = R10 = R12 (°C/W)
R3 (°C/W)
R4 (°C/W)
R5 (°C/W)
R6 (°C/W)
C1 = C7 = C9 = C11 (W.s/°C)
C2 = C8 = C10 = C12 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
Footprint
0.001
0.0022
0.025
0.75
0.4
2
6
7.7
9
28
1
2.2
2
4
5
9
17
8
8
10
9
17
Doc ID 13519 Rev 7 31/37
Package and packing information
5 Package and packing information
VNQ5E050AK-E
5.1 ECOPACK
®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK® is an ST trademark.
Figure 39. PowerSSO-24 package dimensions
32/37 Doc ID 13519 Rev 7
VNQ5E050AK-E
Table 16.
PowerSSO-24 mechanical data
Symbol
Min.
e3
F
G
H h k
L
A
A2 a1 b c
D
E e
U
N
X
Y
O
Q
S
T
2.15
0
0.33
0.23
10.10
7.40
10.1
0°
0.55
4.1
6.5
Package and packing information
Millimeters
Typ.
0.8
8.8
2.3
1.2
0.8
2.9
3.65
1.0
0.1
10.5
0.4
8°
0.85
Max.
2.45
2.35
0.1
0.51
0.32
10.50
7.60
10°
4.7
7.1
Doc ID 13519 Rev 7 33/37
Package and packing information VNQ5E050AK-E
Figure 40. PowerSSO-24 tube shipment (no suffix)
C
B
Base q.ty
Bulk q.ty
49
1225
Tube length (± 0.5) 532
A 3.5
B
C (± 0.1)
13.8
0.6
All dimensions are in mm.
A
Figure 41. PowerSSO-24 tape and reel shipment (suffix “TR”)
Reel dimensions
Base q.ty
Bulk q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
1000
1000
330
1.5
13
20.2
24.4
100
30.4
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986
Tape width
Tape hole spacing
Component spacing
Hole diameter
Hole diameter
Hole position
Compartment depth
Hole spacing
W
P0 (± 0.1)
24
4
P 12
D (± 0.05) 1.55
D1 (min)
F (± 0.1)
K (max)
P1 (± 0.1)
1.5
11.5
2.85
2
All dimensions are in mm.
End
Top cover tape
Start
No components Components No components
500mm min 500mm min
Empty components pockets saled with cover tape.
User direction of feed
34/37 Doc ID 13519 Rev 7
VNQ5E050AK-E Order codes
Table 17.
Device summary
Package
PowerSSO-24
Tube
VNQ5E050AK-E
Order codes
Tape and reel
VNQ5E050AKTR-E
Doc ID 13519 Rev 7 35/37
36/37
Revision history VNQ5E050AK-E
Table 18.
Document revision history
Date
06-Jun-2007
27-Mar-2008
17-Mar-2009
22-Jun-2009
22-Jul-2009
26-Oct-2010
20-Sep-2013
Revision
1
2
3
4
5
6
7
Changes
Initial release.
Updated
Table 9: Current sense (8 V < V
– added dk1/k1, dk2/k2, dk3/k3 parameters
– changed t
DSENSE2H max value from 300 µs to 250 µs
Updated
Table 10: Open-load detection (8V<V
– added I
L(off2)r
, I
L(off2)f and td_vol parameters
Added
.
Added
Figure 10.: Maximum current sense ratio drift vs load current
Added
Added
Section 2.5: Electrical characteristics curves .
Updated
Section 3: Application information :
– added
Section 3.4: Current sense and diagnostic
Updated
Section 4: Package and PC board thermal data :
– added
Figure 37.: PowerSSO-24 thermal impedance junction ambient single pulse (one channel ON)
– added
Table 15: Thermal parameters .
Changed Table 16: PowerSSO-24 mechanical data
Table 16: PowerSSO-24 mechanical data
:
– Changed L (min) value from 6 to 0.55
– Changed L (max) value from 1 to 0.85
Updated
Figure 39: PowerSSO-24 package dimensions .
:
– V
USD
: updated minimum value
Updated Disclaimer
Doc ID 13519 Rev 7
VNQ5E050AK-E
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
ST PRODUCTS ARE NOT DESIGNED OR AUTHORIZED FOR USE IN: (A) SAFETY CRITICAL APPLICATIONS SUCH AS LIFE
SUPPORTING, ACTIVE IMPLANTED DEVICES OR SYSTEMS WITH PRODUCT FUNCTIONAL SAFETY REQUIREMENTS; (B)
AERONAUTIC APPLICATIONS; (C) AUTOMOTIVE APPLICATIONS OR ENVIRONMENTS, AND/OR (D) AEROSPACE APPLICATIONS
OR ENVIRONMENTS. WHERE ST PRODUCTS ARE NOT DESIGNED FOR SUCH USE, THE PURCHASER SHALL USE PRODUCTS AT
PURCHASER’S SOLE RISK, EVEN IF ST HAS BEEN INFORMED IN WRITING OF SUCH USAGE, UNLESS A PRODUCT IS
EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR “AUTOMOTIVE, AUTOMOTIVE SAFETY OR MEDICAL” INDUSTRY
DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS. PRODUCTS FORMALLY ESCC, QML OR JAN QUALIFIED ARE
DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2013 STMicroelectronics - All rights reserved
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Doc ID 13519 Rev 7 37/37
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