STMicroelectronics VND5E050MK-E Datasheet
The STMicroelectronics VND5E050MJ-E is a high-side driver with analog current sense for automotive applications. It features a wide operating voltage range of 4.5V to 28V, a maximum on-state resistance of 50mΩ, and a typical current limitation of 27A. The device also includes several protection features such as undervoltage shutdown, overvoltage clamp, load current limitation, and overtemperature shutdown with auto restart.
Reklam
Reklam
VND5E050MJ-E
VND5E050MK-E
Double-channel high-side driver with analog current sense for automotive applications
Features
Max transient supply voltage
Operating voltage range V
CC
Max on-state resistance(per ch.) R
ON
Current limitation (typ)
Off-state supply current
V
CC
I
LIMH
I
S
1. Typical value with all loads connected.
41 V
4.5 V to 28 V
50 m
27 A
2 µA
(1)
• General
– Inrush current active management by power limitation
– Very low standby current
– 3.0 V CMOS compatible inputs
– Optimized electromagnetic emissions
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/EC european directive
– Very low current sense leakage
• Diagnostic functions
– Proportional load current sense
– High-precision current sense for wide currents range
– Current sense disable
– Overload and short to ground (power limitation) indication
– Thermal shutdown indication
• Protections
– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss of V
CC
– Overtemperature shutdown with auto restart (thermal shutdown)
– Reverse battery protected (see
Figure 29
September 2013 Doc ID 15532 Rev 2
PowerSSO-12
PowerSSO-24
– Electrostatic discharge protection
Applications
• All types of resistive, inductive and capacitive loads
• Suitable as LED driver
Description
The VND5E050MJ-E and VND5E050MK-E are double-channel high-side drivers manufactured in the ST proprietary VIPower™ M0-5 technology and housed in the tiny PowerSSO-12 and
PowerSSO-24 packages. The VND5E050MJ-E and VND5E050MK-E are designed to drive 12 V automotive grounded loads delivering protection, diagnostics and easy 3 V and 5 V CMOS compatible interface with any microcontroller.
The devices integrate advanced protective functions such as load current limitation, inrush and overload active management by power limitation, overtemperature shut-off with auto-restart and overvoltage active clamp. A dedicated analog current sense pin is associated with every output channel in order to provide enhanced diagnostic functions including fast detection of overload and short-circuit to ground through power limitation indication and overtemperature indication.
The current sensing and diagnostic feedback of the whole device can be disabled by pulling the
CS_DIS pin high to allow sharing of the external sense resistor with other similar devices.
1/40
www.st.com
1
Contents
Contents
VND5E050MJ-E / VND5E050MK-E
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 22
Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 22
Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 23
Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Maximum demagnetization energy (V
CC
= 13.5 V) . . . . . . . . . . . . . . . . . 25
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PowerSSO-12 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PowerSSO-24 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
PowerSSO-12 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
PowerSSO-24 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2/40 Doc ID 15532 Rev 2
VND5E050MJ-E / VND5E050MK-E
List of tables
List of tables
< 18 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Doc ID 15532 Rev 2 3/40
List of figures
List of figures
VND5E050MJ-E / VND5E050MK-E
Current and voltage conventions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Delay response time between rising edge of output current and rising edge of current sense
OUT
/I
SENSE
vs I
OUT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Maximum current sense ratio drift vs load current
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
J
evolution in overload or short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Maximum turn-off current versus inductance (for each channel)
(1)
. . . . . . . . . . . . . . . . . . 25
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Rthj-amb vs PCB copper area in open box free air condition (one channel on) . . . . . . . . . 26
PowerSSO-12 thermal impedance junction ambient single pulse (one channel on) . . . . . 27
Thermal fitting model of a double-channel HSD in PowerSSO-12
(1)
. . . . . . . . . . . . . . . . . 27
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Rthj-amb vs PCB copper area in open box free air condition (one channel on) . . . . . . . . . 29
PowerSSO-24 thermal impedance junction ambient single pulse (one channel on) . . . . . 30
Thermal fitting model of a double-channel HSD in PowerSSO-24
(1)
. . . . . . . . . . . . . . . . . 30
tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4/40 Doc ID 15532 Rev 2
VND5E050MJ-E / VND5E050MK-E
1
Block diagram and pin description
Block diagram and pin description
Figure 1.
Block diagram
V
CC
Signal Clamp
Undervoltage
IN1
IN2
Control & Diagnostic 1
Power
Clamp
DRIVER
V
ON
Limitation
Over temp.
Current
Limitation
CH 1
CH 2
CS_
DIS
CS1
CS2
V
SENSEH
Current
Sense
OVERLOAD PROTECTION
(ACTIVE POWER LIMITATION)
OUT2
OUT1
LOGIC
GND
Table 1.
Name
V
CC
OUT
1,2
GND
IN
1,2
CS
1,2
CS_DIS
Pin function
Function
Battery connection.
Power output.
Ground connection. Must be reverse battery protected by an external diode/resistor network.
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state.
Analog current sense pin, delivers a current proportional to the load current.
Active high CMOS compatible pin, to disable the current sense pin.
Doc ID 15532 Rev 2 5/40
Block diagram and pin description VND5E050MJ-E / VND5E050MK-E
Figure 2.
Configuration diagram (top view)
TAB = V cc
GND
IN2
IN1
CS1
CS2
CS_DIS
3
4
5
6
1
2
12
11
10
9
8
7
V cc
OUT2
OUT2
OUT1
OUT1
V cc
V
CC
GND
N.C.
INPUT2
N.C.
INPUT1
N.C.
CURRENT SENSE1
N.C.
CURRENT SENSE2
CS_DIS.
V
CC
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
TAB = V
CC
PowerSSO-12
PowerSSO-24
Table 2.
Floating
Suggested connections for unused and not connected pins
Connection / pin Current sense
To ground
Not allowed
Through 1 K
resistor
N.C.
X
X
Output
X
Not allowed
Input CS_DIS
X X
Through 10 K
resistor
Through 10 K
resistor
6/40 Doc ID 15532 Rev 2
VND5E050MJ-E / VND5E050MK-E Electrical specifications
Figure 3.
Current and voltage conventions
V
CSD
I
CSD
I
IN1
V
IN1
I
IN2
V
IN2
CS_DIS
IN1
IN2
GND
I
S
V
CC
OUT1
CS1
OUT2
CS2
V
Fn
I
OUT1
I
SENSE1
V
SENSE1
I
OUT2
I
SENSE2
V
SENSE2
V
OUT2
V
OUT1
I
GND
V
CC
2.1
1. V
Fn
= V
OUTn
- V
CC
during reverse battery condition.
Absolute maximum ratings
Stressing the device above the rating listed in the “absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to the conditions in table below for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE program and other relevant quality document.
Table 3.
Symbol
V
CC
-V
CC
-I
GND
I
OUT
-I
OUT
I
IN
I
CSD
-I
CSENSE
V
CSENSE
Absolute maximum ratings
Parameter
DC supply voltage
Reverse DC supply voltage
DC reverse ground pin current
DC output current
Reverse DC output current
DC input current
DC current sense disable input current
DC reverse CS pin current
Current sense maximum voltage
Value
41
0.3
200
Internally limited
20
-1 to 10
-1 to 10
200
V
CC
- 41 to +V
CC
Unit
V
V mA
A
A mA mA mA
V
Doc ID 15532 Rev 2 7/40
Electrical specifications VND5E050MJ-E / VND5E050MK-E
Table 3.
Symbol
E
MAX
V
ESD
V
ESD
T j
T stg
Absolute maximum ratings (continued)
Parameter
Maximum switching energy (single pulse)
(L = 3 mH, R
L
I
OUT
= I limL
= 0
, V
(Typ.)) bat
= 13.5 V, T jstart
= 150 °C,
Electrostatic discharge
(human body model: R = 1.5 K
C = 100 pF)
- IN
- CS
- CS_DIS
- OUT
- V
CC
Charge device model (CDM-AEC-Q100-011)
Junction operating temperature
Storage temperature
Value
104
4000
2000
4000
5000
5000
750
- 40 to 150
- 55 to 150
Unit
mJ
°C
°C
V
V
V
V
V
V
Table 4.
Symbol
Thermal data
Parameter
R thj-case
R thj-amb
Thermal resistance junction-case
(with one channel on)
Thermal resistance junction-ambient
Max. value
PowerSSO-12 PowerSSO-24
Unit
2.7
See
2.7
°C/W
°C/W
8/40 Doc ID 15532 Rev 2
VND5E050MJ-E / VND5E050MK-E Electrical specifications
Values specified in this section are for 8 V < V
CC otherwise stated.
< 28 V, -40 °C < T j
< 150 °C, unless
Table 5.
Symbol
Power section
Parameter Test conditions
V
V
CC
V
USD
USDhyst
Operating supply voltage
Undervoltage shutdown
Undervoltage shutdown hysteresis
V
I
R
ON clamp
(2)
I
S
L(off1)
(2)
ON-state resistance
Clamp voltage
Supply current
(1)
OFF-state output current
(1)
V
F
Output-V
CC
diode voltage
(1)
1. For each channel.
2. Special characteristic according to ISO/TS 16949.
3. PowerMOS leakage included.
I
OUT
= 2 A, T j
= 25 °C
I
OUT
= 2 A, T j
= 150 °C
I
T
OUT
= 2 A, V
CC j
= 25 °C
= 5 V,
I
S
= 20 mA
OFF-state: V
CC
T j
= 25 °C,
V
IN
= 13 V,
= V
OUT
= V
SENSE
= V
CSD
= 0 V
ON-state: V
CC
= 13 V,
V
IN
= 5 V, I
OUT
= 0 A
V
IN
T j
= V
OUT
= 25 °C
= 0 V, V
CC
= 13 V,
V
IN
T j
= V
OUT
= 125 °C
= 0 V, V
CC
= 13 V,
-I
OUT
= 4 A, T j
= 150 °C
Min.
Typ.
Max.
Unit
4.5
13
3.5
28
4.5
V
V
41
0
0
0.5
46
2
(3)
3
0.01
50
100
65
52
5
(3)
6
3
5
0.7
V m
V
µA mA
µA
V
Table 6.
Symbol
Switching (V
CC
= 13 V, T j
= 25 °C)
Parameter Test conditions
t d(on) t d(off)
Turn-on delay time
Turn-off delay time
R
L
= 6.5
R
L
= 6.5
dV
OUT
/dt
(on)
Turn-on voltage slope R
L
= 6.5
dV
OUT
/dt
(off)
Turn-off voltage slope R
L
= 6.5
Min.
Typ.
20
45
See
See
Max. Unit
µs
µs
V
µs
V
µs
Doc ID 15532 Rev 2 9/40
Electrical specifications VND5E050MJ-E / VND5E050MK-E
Table 6.
Symbol
Switching (V
CC
= 13 V, T j
= 25 °C) (continued)
Parameter Test conditions Min.
W
ON
W
OFF
Switching energy losses during t won
Switching energy losses during t woff
R
L
= 6.5
R
L
= 6.5
Typ.
0.15
0.3
Max. Unit
mJ mJ
Table 7.
Symbol
Logic inputs
Parameter Test conditions
V
V
I
I
V
V
I
I
V
IL
IL
IH
IH
I(hyst)
V
CSD(hyst)
V
V
ICL
CSDL
CSDL
CSDH
CSDH
CSCL
Low-level input voltage
Low-level input current V
IN
= 0.9 V
High-level input voltage
High-level input current V
IN
= 2.1 V
Hysteresis input voltage
Input voltage clamp
I
IN
= 1 mA
I
IN
= -1 mA
Low-level CS_DIS voltage
Low-level CS_DIS current
High-level CS_DIS voltage
High-level CS_DIS current
CS_DIS hysteresis voltage
V
V
CSD
CSD
= 0.9 V
= 2.1 V
CS_DIS voltage clamps
I
CSD
= 1 mA
I
CSD
= -1 mA
Table 8.
Protections and diagnostics
(1)
Symbol Parameter Test conditions
I limH
I limL
T
TSD
(2)
T
R
T
RS
T
HYST
DC short circuit current
Short circuit current during thermal cycling
Shutdown temperature
Reset temperature
Thermal reset of status
Thermal hysteresis
(T
TSD
- T
R
)
V
CC
= 13 V
5 V < V
CC
< 28 V
V
CC
= 13 V,
T
R
< T j
< T
TSD
Min.
Typ. Max. Unit
1
2.1
0.25
5.5
0.9
10
7
V
µA
V
µA
V
V
-0.7
0.9
V
1
2.1
0.25
5.5
-0.7
10 µA
7
µA
V
V
V
Min.
19
Typ.
27
7
150 175
T
RS
+ 1 T
RS
+ 5
135
7
Max.
38
38
200
Unit
A
A
A
°C
°C
°C
°C
10/40 Doc ID 15532 Rev 2
VND5E050MJ-E / VND5E050MK-E Electrical specifications
Table 8.
Protections and diagnostics
(1)
(continued)
Symbol Parameter Test conditions Min.
Typ.
Max.
Unit
V
DEMAG
(2)
Turn-off output voltage clamp
V
ON
Output voltage drop limitation
I
OUT
= 2 A, V
IN
= 0,
L = 6 mH
I
OUT
= 0.1 A,
T j
= -40 °C to +150 °C
(see
)
V
CC
- 41 V
CC
- 46 V
25
CC
- 52
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles.
2. Special characteristic according to ISO/TS 16949.
V mV
Table 9.
Symbol
K
0
K
1 dK
1
/K
1
(1)
K
2 dK
2
/K
2
(1)
K
3 dK
3
/K
3
(1)
I
SENSE0
(2)
I
OL
V
SENSE
Current sense (8 V < V
CC
< 18 V)
Parameter
I
OUT
/I
SENSE
I
OUT
/I
SENSE
Current sense ratio drift
I
OUT
/I
SENSE
Current sense ratio drift
I
OUT
/I
SENSE
Current sense ratio drift
Analog sense leakage current
Test conditions Min. Typ. Max. Unit
I
OUT
= 0.05 A, V
SENSE
= 0.5 V,
V
CSD
= 0 V, T j
= -40 °C to 150 °C
I
OUT
= 1 A, V
SENSE
= 4 V, V
CSD
= 0 V,
T j
= -40 °C to 150 °C
T j
= 25°C...150°C
I
OUT
= 1 A, V
SENSE
= 4 V, V
CSD
= 0 V,
T j
= -40 °C to 150 °C
I
OUT
= 2 A, V
SENSE
= 4 V, V
CSD
= 0 V,
T j
= -40 °C to 150 °C
T j
= 25 °C to 150 °C
I
OUT
= 2 A; V
SENSE
= 4 V, V
CSD
= 0 V,
T j
= -40 °C to 150 °C
I
OUT
= 4 A, V
SENSE
= 4 V, V
CSD
= 0 V,
T j
= -40 °C to 150 °C
T j
= 25 °C to 150 °C
I
OUT
= 4 A, V
SENSE
= 4 V, V
CSD
= 0 V,
T j
= -40 °C to 150 °C
I
OUT
= 0 A, V
SENSE
= 0 V, V
CSD
= 5 V,
V
IN
= 0 V, T j
= -40 °C to 150 °C
I
OUT
V
IN
= 0 A, V
SENSE
= 5 V, T j
= 0 V, V
CSD
= 0 V,
= -40 °C to 150 °C
I
OUT
= 2 A, V
SENSE
= 0 V, V
CSD
= 5 V,
V
IN
= 5 V, T j
= -40 °C to 150 °C
1440 2250 3630
1740
1750
-15
1900
1899
-9
1969
1950
-6
0
0
0
2070
2070
2000
2000
1990
1990
2820
2562
15
2395
2282
9
2210
2153
6
1
2
1
%
%
%
µA
Open load on-state current detection threshold
Max analog sense output voltage
V
IN
= 5 V, 8 V < V
CC
< 18 V
I
SENSE
= 5 µA
I
OUT
= 4 A, V
CSD
= 0 V
4
5
20 mA
V
Doc ID 15532 Rev 2 11/40
Electrical specifications VND5E050MJ-E / VND5E050MK-E
Table 9.
Symbol
Current sense (8 V < V
CC
< 18 V) (continued)
Parameter Test conditions
t t
V
I
SENSEH
SENSEH
DSENSE1H
DSENSE1L
Analog sense output voltage in fault condition
(3)
Analog sense output current in fault condition
(3)
V
CC
= 13 V, R
SENSE
= 3.9 K
V
CC
= 13 V, V
SENSE
= 5 V
Delay response time from falling edge of
CS_DIS pin
Delay response time from rising edge of
CS_DIS pin
V
SENSE
< 4 V, 0.5 A < I
OUT
< 4 A
I
SENSE
= 90% of I
SENSE max
(see
V
SENSE
< 4 V, 0.5 A < I
OUT
< 4 A
I
SENSE
= 10% of I
SENSE max
(see
t t
DSENSE2H
DSENSE2L
Delay response time from rising edge of
INPUT pin
V
SENSE
< 4 V, 0.5 A < I
OUT
< 4 A
I
SENSE
= 90% of I
SENSE max
(see
t
DSENSE2H
Delay response time between rising edge of output current and rising edge of current sense
V
SENSE
< 4 V,
I
SENSE
= 90% of I
SENSEMAX,
I
OUT
= 90% of I
OUTMAX
I
OUTMAX
)
Delay response time from falling edge of
INPUT pin
V
SENSE
< 4 V, 0.5 A < I
OUT
< 4 A
I
SENSE
= 10% of I
SENSE max
(see
1. Parameter guaranteed by design; it is not tested.
2. Special characteristic according to ISO/TS 16949.
3. Fault condition includes: power limitation and overtemperature.
Min. Typ. Max. Unit
8 V
9 mA
40 100 µs
5 20 µs
80 250 µs
40 µs
80 250 µs
Figure 4.
Current sense delay characteristics
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT t
DSENSE2H t
DSENSE1L t
DSENSE1H t
DSENSE2L
12/40 Doc ID 15532 Rev 2
VND5E050MJ-E / VND5E050MK-E
Figure 5.
Switching characteristics
V
OUT t
Won
80% dV
OUT
/dt
(on) t r
10%
INPUT t d(on) t d(off) t
Woff
90% t f
Electrical specifications
dV
OUT
/dt
(off) t t
Figure 6.
Delay response time between rising edge of output current and rising edge of current sense (CS enabled)
V
IN
t
DSENSE2H t
I
OUT
90% I
OUTMAX
I
OUTMAX t
I
SENSE I
SENSEMAX
90% I
SENSEMAX t
Doc ID 15532 Rev 2 13/40
Electrical specifications VND5E050MJ-E / VND5E050MK-E
Figure 7.
Output voltage drop limitation
V cc
-V out
T j
=150 o
C
T j
=25 o
C
T j
=-40 o
C
V on
I out
Figure 8.
I
OUT
/I
SENSE
vs I
OUT
I out
/ I sense
3000
2800
2600
A
B
2400
2200
2000
C
1800
1600
1400
1200
1
D
1,5 2
A: Max, T j
B: Max, T j
= -40 °C to 150 °C
= 25 °C to 150 °C
C: Typical, T j
= -40 °C to 150 °C
V on
/R on(T)
2,5
I
OUT
(A)
3 3,5
D: Min, T j
E: Min, T j
= 25 °C to 150 °C)
= -40 °C to 150 °C)
E
4
14/40 Doc ID 15532 Rev 2
VND5E050MJ-E / VND5E050MK-E Electrical specifications
Figure 9.
Maximum current sense ratio drift vs load current
dk/k(%)
20
15
A
10
5
0
-5
-10
-15
-20
1
B
2
I
OUT
(A)
3 4
A: Max, T j
= -40 °C to 150 °C B: Min, T j
= 25 °C to 150 °C
1. Parameter guaranteed by design; it is not tested.
Table 10.
Truth table
Conditions Input Output Sense (V
CSD
= 0 V)
(1)
Normal operation
Overtemperature
Undervoltage
Overload
Short circuit to GND
(power limitation)
Negative output voltage clamp
L
H
L
H
L
H
H
H
L
H
L
L
L
L
H
L
L
X
(no power limitation)
Cycling
(power limitation)
L
L
L
0
Nominal
0
V
SENSEH
0
0
Nominal
V
V
SENSEH
0
SENSEH
0
1. If the V
CSD
is high, the SENSE output is at a high-impedance, its potential depends on leakage currents and external circuit.
Doc ID 15532 Rev 2 15/40
16/40
Electrical specifications VND5E050MJ-E / VND5E050MK-E
Table 11.
Electrical transient requirements (part 1)
ISO 7637-2:
2004(E)
Test pulse
III
Test levels
(1)
IV
Number of pulses or test times
Burst cycle/pulse repetition time
Min.
Max.
1
2a
3a
3b
4
5b
(2)
-75 V
+37 V
-100 V
+75 V
-6 V
+65 V
-100 V
+50 V
-150 V
+100 V
-7 V
+87 V
5000 pulses
5000 pulses
1 h
1 h
1 pulse
1 pulse
0.5 s
0.2 s
90 ms
90 ms
5 s
5 s
100 ms
100 ms
1. The above test levels must be considered referred to V
CC
= 13.5 V except for pulse 5b.
2. Valid in case of external load dump clamp: 40 V maximum referred to ground.
Delays and
Impedance
2 ms, 10
50 µs, 2
0.1µs, 50
0.1µs, 50
100 ms, 0.01
400 ms, 2
Table 12.
Electrical transient requirements (part 2)
ISO 7637-2:
2004(E)
Test pulse
III
Test level results
1
2a
3a
3b
4
5b
(1)
C
C
C
C
C
C
1. Valid in case of external load dump clamp: 40 V maximum referred to ground.
IV
C
C
C
C
C
C
Table 13.
Electrical transient requirements (part 3)
Class Contents
C
E
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
Doc ID 15532 Rev 2
VND5E050MJ-E / VND5E050MK-E
2.4 Waveforms
Figure 10. Normal operation
Electrical specifications
Normal operation
INPUT
Nominal load Nominal load
I
OUT
V
SENSE
V
CS_DIS
Figure 11. Overload or short to GND
Overload or Short to GND
INPUT
I
LimH
>
I
OUT
Power Limitation
I
LimL
>
Thermal cycling
V
SENSE
V
CS_DIS
Doc ID 15532 Rev 2 17/40
Electrical specifications
Figure 12. Intermittent overload
VND5E050MJ-E / VND5E050MK-E
Intermittent Overload
INPUT
I
LimH
>
I
OUT
V
SENSEH
>
V
SENSE
V
CS_DIS
Overload
I
LimL
>
Nominal load
Figure 13. T
J
evolution in overload or short to GND
T
J
evolution in
Overload or Short to GND
INPUT
Self-limitation of fast thermal transients T
TSD
T
R
T
J
I
LimH
>
T
J_START
Power Limitation
T
HYST
< I
LimL
I
OUT
18/40 Doc ID 15532 Rev 2
VND5E050MJ-E / VND5E050MK-E Electrical specifications
Figure 14. OFF-state output current
Iloff (nA)
550
350
300
250
200
150
500
450
400
100
50
0
-50 -25
Off State
Vcc=13V
Vin=Vout=0V
0 25 50 75
Tc (°C)
100 125 150 175
Figure 16. Input voltage clamp
Vicl (V)
7
6,8
6,6
6,4
6,2
6
5,8
5,6
5,4
5,2
5
-50 -25
lin=1mA
0 25 50 75
Tc (°C)
100 125 150 175
Figure 18. High-level input voltage
Vih (V)
4
3,5
3
2,5
2
1,5
1
0,5
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Figure 15. High-level input current
Iih (µA)
5
4,5
4
3,5
3
2,5
2
1,5
1
0,5
0
-50 -25
Vin=2.1V
0 25 50 75
Tc (°C)
100 125 150 175
Figure 17. Low-level input voltage
Vil (V)
2
1,8
1,6
1,4
1,2
1
0,8
0,6
0,4
0,2
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Figure 19. Hysteresis input voltage
Vihyst (V)
1
0,9
0,5
0,4
0,3
0,2
0,8
0,7
0,6
0,1
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Doc ID 15532 Rev 2 19/40
Electrical specifications
Figure 20. ON-state resistance vs T case
Ron (mOhm)
300
250
Iout= 2A
Vcc=13V
200
150
100
50
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Figure 22. Undervoltage shutdown
Vusd (V)
16
14
12
10
8
6
4
2
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Figure 24. I
LIMH
vs T case
Ilimh (A)
40
35
30
25
20
15
Vcc=13V
10
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
VND5E050MJ-E / VND5E050MK-E
Figure 21. ON-state resistance vs V
CC
Ron (mOhm)
100
80
Tc=150°C
Tc=125°C
60
40
Tc=25°C
Tc=-40°C
20
0
0 5 10 15 20
Vcc (V)
25 30 35 40
Figure 23. Turn-on voltage slope
(dVout/dt )On (V/ms)
1000
900
800
Vcc=13V
RI=6.5 Ohm
700
600
500
400
300
200
100
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Figure 25. Turn-off voltage slope
(dVout/dt )Off (V/ms)
600
550
500
450
400
350
300
250
200
150
100
50
0
-50 -25 0 25
Vcc=13V
RI= 6.5 Ohm
50 75
Tc (°C)
100 125 150 175
20/40 Doc ID 15532 Rev 2
VND5E050MJ-E / VND5E050MK-E
Figure 26. High-level CS_DIS voltage
Vcsdh (V)
4
3,5
3
2,5
2
1,5
1
0,5
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Figure 28. Low-level CS_DIS voltage
Vcsdl (V)
3
2,5
2
1,5
1
0,5
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Electrical specifications
Figure 27. CS_DIS voltage clamp
Vcsdcl(V)
10
9
4
3
6
5
8
7
2
1
0
-50 -25 0 25
Icsd = 1 mA
50 75
Tc (°C)
100 125 150 175
Doc ID 15532 Rev 2 21/40
Application information VND5E050MJ-E / VND5E050MK-E
Figure 29. Application schematic
+5V
CU
V
CC
R prot
CS_DIS
R
R prot prot
C
EXT
R
SENSE
INPUT
CURRENT SENSE
GND
V
GND
R
GND
D
GND
OUTPUT
D ld
3.1
1. Channel 2 has the same internal circuit as channel 1.
GND protection network against reverse battery
This section provides two solutions for implementing a ground protection network against reverse battery.
resistor in the ground line (R
GND
only)
This can be used with any type of load.
The following is an indication on how to dimension the R
GND resistor.
1.
R
GND
600 mV / (I
S(on)max
)
2. R
GND
V
CC
) / (-I
GND
) where -I
GND
is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet.
Power dissipation in R
GND
(when V
CC
< 0: during reverse battery situations) is:
Equation 1
P
D
= (-V
CC
)
2
/ R
GND
22/40 Doc ID 15532 Rev 2
VND5E050MJ-E / VND5E050MK-E
3.1.2
Application information
This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where I
S(on)max maximum on-state currents of the different devices.
becomes the sum of the
Please note that if the microprocessor ground is not shared by the device ground then the
R
GND produces a shift (I
S(on)max
* R
GND
) in the input thresholds and the status output values. This shift varies depending on how many devices are on in the case of several highside drivers sharing the same R
GND
.
If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize Solution 2 (see
Section 3.1.2
Solution 2: diode (D
GND
) in the ground line
A resistor (R
GND inductive load.
= 1 k
should be inserted in parallel to D
GND
if the device drives an
This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network produces a shift (
600 mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift not varies if more than one HSD shares the same diode/resistor network.
3.3
D ld
is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the
V
CC
max DC rating. The same applies if the device is subject to transients on the V
CC that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
line
MCU I/Os protection
If a ground protection network is used and negative transient are present on the V
CC the control pins is pulled negative. ST suggests to insert a resistor (R prot the microcontroller I/Os pins to latch-up.
line,
) in line to prevent
The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os:
Equation 2
-V
CCpeak
/ I latchup
R prot
(V
OH
C
- V
IH
- V
GND
) / I
IHmax
Calculation example:
For V
CCpeak
= - 100 V, I latchup
20 mA and V
OHµC
4.5 V
5 k
R prot
180 k
Recommended values: R prot
=10 k
, C
EXT
= 10 nF.
Doc ID 15532 Rev 2 23/40
Application information
3.4 Current sense and diagnostic
VND5E050MJ-E / VND5E050MK-E
The current sense pin performs a double function (see
Figure 30: Current sense and diagnostic
):
?
?
Current mirror of the load current in normal operation, delivering a current proportional to the load one according to a know ratio K
X
.
The current I
SENSE external resistor R
can be easily converted to a voltage V
SENSE
SENSE
. Linearity between I minimum (see parameter V
SENSE
OUT
and V
SENSE
by means of an
is ensured up to 5V
Table 9: Current sense (8 V < V
< 18 V)
). The current sense accuracy depends on the output current (refer to current sense electrical characteristics
Table 9: Current sense (8 V < V
< 18 V)
).
Diagnostic flag in fault conditions, delivering a fixed voltage V
SENSEH maximum current I
SENSEH
Truth table
):
up to a
in case of the following fault conditions (refer to
Table 10:
– Power limitation activation
– Over-temperature
A logic level high on CS_DIS pin sets at the same time all the current sense pins of the device in a high-impedance state, thus disabling the current monitoring and diagnostic detection. This feature allows multiplexing of the microcontroller analog inputs by sharing of sense resistance and ADC line among different devices.
Figure 30. Current sense and diagnostic
V
BAT
V
CC
Main MOSn
41V
Overtemperature
I
OUT
/K
X
I
SENSEH
Pwr_Lim
OUTn
CS_DIS
R
PROT
To uC ADC
R
SENSE
CURRENT
SENSEn
V
SENSEH
V
SENSE
GND
Load
24/40 Doc ID 15532 Rev 2
VND5E050MJ-E / VND5E050MK-E
3.5 Maximum demagnetization energy (V
CC
Application information
= 13.5 V)
Figure 31. Maximum turn-off current versus inductance (for each channel)
100
10
C
A
B
1
0,1 1 L (mH) 10 100
A: T jstart
= 150 °C single pulse
B: T jstart
C: T jstart
= 100 °C repetitive pulse
= 125 °C repetitive pulse
V
IN
, I
L
Demagnetization Demagnetization Demagnetization
1. Values are generated with R
L
= 0
In case of repetitive pulses, T jstart
(at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B.
t
Doc ID 15532 Rev 2 25/40
Package and PCB thermal data
4 Package and PCB thermal data
VND5E050MJ-E / VND5E050MK-E
4.1 PowerSSO-12 thermal data
Figure 32. PowerSSO-12 PC board
26/40
1. Layout condition of R th
and Z th
measurements (PCB: double layer, thermal vias, areas: from minimum pad lay-out to 8 cm
2
).
Figure 33. R thj-amb on)
vs PCB copper area in open box free air condition (one channel
RTHj_amb(°C/ W)
70
65
60
55
50
45
40
35
30
0 2 4 6
PCB Cu heatsink area (cm^ 2)
8 10
Doc ID 15532 Rev 2
VND5E050MJ-E / VND5E050MK-E Package and PCB thermal data
Figure 34. PowerSSO-12 thermal impedance junction ambient single pulse (one channel on)
ZTH (°C/ W)
100
Footprint
2 cm
2
8 cm
2
10
1
0,1
0,0001 0,001 0,01 0,1
Time ( s)
1 10 100 1000
Equation 3: pulse calculation formula
where
= t
P
/T
Figure 35. Thermal fitting model of a double-channel HSD in PowerSSO-12 (1)
1. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
Doc ID 15532 Rev 2 27/40
Package and PCB thermal data
Table 14.
Thermal parameters
Area/island (cm
2
)
R1=R7 (°C/W)
R2=R8 (°C/W)
R3 (°C/W)
R4 (°C/W)
R5 (°C/W)
R6 (°C/W)
C1=C7 (W.s/°C)
C2=C8 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
Footprint
0.001
0.0025
0.05
0.2
0.7
2.8
4
8
22
26
0.27
3
VND5E050MJ-E / VND5E050MK-E
2
0.1
0.8
6
8
15
20
8
0.1
1
9
7
10
15
28/40 Doc ID 15532 Rev 2
VND5E050MJ-E / VND5E050MK-E
4.2 PowerSSO-24 thermal data
Figure 36. PowerSSO-24 PC board
Package and PCB thermal data
1. Layout condition of R th
and Z th
measurements (PCB: double layer, Thermal vias, areas: from minimum pad lay-out to 8 cm
2
).
Figure 37. R thj-amb on)
vs PCB copper area in open box free air condition (one channel
RTHj_amb(°C/W)
55
50
45
40
35
30
0 2 4 6
PCB Cu heatsink area (cm^2)
8 10
Doc ID 15532 Rev 2 29/40
Package and PCB thermal data VND5E050MJ-E / VND5E050MK-E
Figure 38. PowerSSO-24 thermal impedance junction ambient single pulse (one channel on)
Equation 4: pulse calculation formula
where
= t
P
/T
Figure 39. Thermal fitting model of a double-channel HSD in PowerSSO-24 (1)
30/40
1. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
Doc ID 15532 Rev 2
VND5E050MJ-E / VND5E050MK-E
Table 15.
Thermal parameters
Area / island (cm
2
)
R1 = R7 (°C/W)
R2 = R8 (°C/W)
R3 (°C/W)
R4 (°C/W)
R5 (°C/W)
R6 (°C/W)
C1 = C7 (W.s/°C)
C2 = C8 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
Footprint
0.001
0.0022
0.025
0.75
0.4
2
6
7.7
9
28
1
2.2
Package and PCB thermal data
2 8
4
5
9
17
8
10
9
17
Doc ID 15532 Rev 2 31/40
Package and packing information
5
VND5E050MJ-E / VND5E050MK-E
Package and packing information
5.1 ECOPACK
®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK
®
is an ST trademark.
5.2 PowerSSO-12 package information
Figure 40. PowerSSO-12 package dimensions
32/40 Doc ID 15532 Rev 2
VND5E050MJ-E / VND5E050MK-E
Table 16.
PowerSSO-12 mechanical data
Symbol
h
L k
X
D
E e
H
Y ddd
A
A1
A2
B
C
5.8
0.25
0.4
0°
1.9
3.6
Min.
1.25
0
1.10
0.23
0.19
4.8
3.8
Package and packing information
Millimeters
Typ.
0.8
Max.
1.62
0.1
1.65
0.41
0.25
5.0
4.0
6.2
0.5
1.27
8°
2.5
4.2
0.1
Doc ID 15532 Rev 2 33/40
Package and packing information
Figure 41. PowerSSO-24 package dimensions
VND5E050MJ-E / VND5E050MK-E
34/40 Doc ID 15532 Rev 2
VND5E050MJ-E / VND5E050MK-E
Table 17.
PowerSSO-24 mechanical data
Symbol
G
G1
H h
L
N
X
Y
A
A2 a1 b c
D
E e e3
Min.
2.15
2.15
0
0.33
0.23
10.10
7.4
10.1
0.55
4.1
6.5
Package and packing information
Millimeters
Typ.
0.8
8.8
0.1
0.06
10.5
0.4
0.85
10deg
4.7
7.1
Max.
2.47
2.40
0.075
0.51
0.32
10.50
7.6
Doc ID 15532 Rev 2 35/40
Package and packing information
5.4 PowerSSO-12 packing information
Figure 42. PowerSSO-12 tube shipment (no suffix)
VND5E050MJ-E / VND5E050MK-E
B
A
C
Base q.ty
Bulk q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
All dimensions are in mm.
100
2000
532
1.85
6.75
0.6
Figure 43. PowerSSO-12 tape and reel shipment (suffix “TR”)
Reel dimensions
Base q.ty
Bulk q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
2500
2500
330
1.5
13
20.2
12.4
60
18.4
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
Tape hole spacing
Component spacing
Hole diameter
Hole diameter
Hole position
Compartment depth
Hole spacing
W
P0 (± 0.1)
P
D (± 0.05)
D1 (min)
F (± 0.1)
K (max)
P1 (± 0.1)
1.5
5.5
4.5
2
12
4
8
1.5
All dimensions are in mm.
End
Top cover tape
No components
500mm min
Components
Empty components pockets saled with cover tape.
No components
500mm min
User direction of feed
Start
36/40 Doc ID 15532 Rev 2
VND5E050MJ-E / VND5E050MK-E
5.5 PowerSSO-24 packing information
Figure 44. PowerSS0-24 tube shipment (no suffix)
Package and packing information
C
B
Base qty
Bulk qty
Tube length (±0.5)
A
B
C (±0.1)
All dimensions are in mm.
49
1225
532
3.5
13.8
0.6
A
Figure 45. PowerSSO-24 tape and reel shipment (suffix “TR”)
Reel dimensions
Base qty
Bulk qty
A (max)
B (min)
C (±0.2)
F
G (+2 / -0)
N (min)
T (max)
1000
1000
330
1.5
13
20.2
24.4
100
30.4
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
Tape hole spacing
Component spacing
Hole diameter
Hole diameter
Hole position
Compartment depth
Hole spacing
W
P0 (±0.1)
D1 (min)
F (±0.1)
K (max)
P1 (±0.1)
24
4
P
12
D (±0.05)
1.55
1.5
11.5
2.85
2
All dimensions are in mm.
End
Top cover tape
No components Components No components
500mm min
500mm min
Empty components pockets sealed with cover tape.
Start
User direction of feed
Doc ID 15532 Rev 2 37/40
Order codes VND5E050MJ-E / VND5E050MK-E
Table 18.
Device summary
Package
PowerSSO-12
PowerSSO-24
Tube
VND5E050MJ-E
VND5E050MK-E
Order codes
Tape and reel
VND5E050MJTR-E
VND5E050MKTR-E
38/40 Doc ID 15532 Rev 2
VND5E050MJ-E / VND5E050MK-E
Table 19.
Document revision history
Date Revision
14-Oct-2009
20-Sep-2013
1
2
Initial release.
Updated Disclaimer.
Changes
Revision history
Doc ID 15532 Rev 2 39/40
VND5E050MJ-E / VND5E050MK-E
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40/40 Doc ID 15532 Rev 2
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