STMicroelectronics VND5025AK-E Datasheet

VND5025AK-E

Double channel high side driver with analog current sense for automotive applications

Features

Max transient supply voltage

Operating voltage range

V

CC

V

CC

Max on-state resistance (per ch.) R

ON

Current limitation (typ) I

LIMH

Off-state supply current I

S

41V

4.5 to 36V

25 m Ω

41 A

2 µA

(1)

1.

Typical value with all loads connected.

PowerSSO-24™

– Electrostatic discharge protection

Application

■

■

All types of resistive, inductive and capacitive loads

Suitable as LED driver

■

■

■

Main

– In-rush current active management by power limitation

– Very low standby current

– 3.0V CMOS compatible input

– Optimized electromagnetic emission

– Very low electromagnetic susceptibility

– In compliance with the 2002/95/EC

European directive

– Package: ECOPACK ®

Diagnostic functionsDoc ID 12581

– Proportional load current sense

– High current sense precision for wide range currents

– Current sense disable

– Thermal shutdown indication

– Very low current sense leakage

Protection

– Undervoltage shut-down

– Overvoltage clamp

– Load current limitation

– Self-limiting of fast thermal transients

– Protection against loss of ground and loss of V

CC

– Thermal shutdown

– Reverse battery protection (see

Application schematic on page 21 )

Table 1.

Device summary

Package

PowerSSO-24™

Description

The VND5025AK-E is a monolithic device made using STMicroelectronics VIPower M0-5 technology, intended for driving resistive or inductive loads with one side connected to ground, and suitable for driving LEDs. Active V

CC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). This device integrates an analog current sense which delivers a current proportional to the load current (according to a known ratio) when CS_DIS is driven low or left open. When CS_DIS is driven high, the

CURRENT SENSE pin is in a high impedance condition. Output current limitation protects the device in overload condition. In case of long overload duration, the device limits the dissipated power to safe level up to thermal shut-down intervention. Thermal shut-down with automatic restart allows the device to recover normal operation as soon as fault condition disappears.

Order codes

Tube

VND5025AK-E

Tape and reel

VND5025AKTR-E

September 2013 Doc ID 12581 Rev 11 1/32 www.st.com

1

2/32

1

2

Contents

Contents

3

4

5

6

VND5025AK-E

Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4

Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.1

GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 21

3.1.1

3.1.2

Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 21

Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 22

3.2

Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.3

MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.4

Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 23

Package and thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1

PowerSSO-24™ thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1

ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.2

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.3

Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Doc ID 12581 Rev 11

VND5025AK-E

List of tables

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Switching (VCC = 13V; Tj = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 9.

Protection and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 10.

Current sense (8V < VCC < 16V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 11.

Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 12.

Electrical transient requirements (part 1/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 13.

Electrical transient requirements (part 2/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 14.

Electrical transient requirements (part 3/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 15.

Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 16.

PowerSSO-24™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 17.

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Doc ID 12581 Rev 11 3/32

4/32

List of figures

List of figures

VND5025AK-E

Figure 1.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2.

Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3.

Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4.

Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 5.

Delay response time between rising edge of output current and rising edge of Current Sense

(CS enabled). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 6.

Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 7.

IOUT/ISENSE vs IOUT

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 8.

Maximum current sense ratio drift vs load current

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 9.

Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 10.

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 11.

Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 12.

High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 13.

Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 14.

Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 15.

Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 16.

Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 17.

On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 18.

On-state resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 19.

Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 20.

ILIMH vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 21.

Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 22.

Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 23.

CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 24.

CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 25.

CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 26.

Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 27.

Maximum turn-off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 23

Figure 28.

PowerSSO-24™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 29.

Rthj-amb vs PCB copper area in open box free air condition (one channel ON) . . . . . . . . 24

Figure 30.

PowerSSO-24™ thermal impedance junction to ambient single pulse (one channel ON) . 25

Figure 31.

Thermal fitting model of a double channel HSD in PowerSSO-24™

(1)

. . . . . . . . . . . . . . . 25

Figure 32.

PowerSSO-24™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 33.

PowerSSO-24™ tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 34.

PowerSSO-24™ tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Doc ID 12581 Rev 11

VND5025AK-E

1

Block diagram and pin description

Block diagram and pin description

Figure 1.

Block diagram

Vcc

GND

INPUT1

INPUT2

V

CC

CLAMP

UNDERVOLTAGE

LOGIC

PwCLAMP 1

DRIVER 1

I

LIM

1

V

DSLIM

1

Pwr

LIM

1

OVERTEMP. 1

I

OUT1

K 1

Pwr

LIM

2

CS_DIS

DRIVER 2

PwCLAMP 2

I

LIM

2

V

DSLIM

2

I

OUT2

OVERTEMP. 2

K 2

OUTPUT1

CURRENT

SENSE1

OUTPUT2

CURRENT

SENSE2

Table 2.

Pin functions

Name

V

CC

OUTPUT

GND

INPUT

1,2

1,2

CURRENT SENSE

1,2

CS_DIS

Function

Battery connection.

Power output.

Ground connection; must be reverse battery protected by an external diode/resistor network.

Voltage controlled input pin with hysteresis, CMOS compatible; controls output switch state.

Analog current sense pin; delivers a current proportional to the load current.

Active high CMOS compatible pin to disable the current sense pin.

Doc ID 12581 Rev 11 5/32

Block diagram and pin description

Figure 2.

Configuration diagram (top view)

V

CC

GND

N.C.

INPUT2

N.C.

INPUT1

N.C.

CURRENT SENSE1

N.C.

CURRENT SENSE2

CS_DIS.

V

CC

5

6

7

8

3

4

1

2

9

10

11

12

20

19

18

17

24

23

22

21

16

15

14

13

OUTPUT2

OUTPUT2

OUTPUT2

OUTPUT2

OUTPUT2

OUTPUT2

OUTPUT1

OUTPUT1

OUTPUT1

OUTPUT1

OUTPUT1

OUTPUT1

TAB = V

CC

VND5025AK-E

Table 3.

Suggested connections for unused and not connected pins

Connection / pin N.C.

Output Input

Floating

Current sense

N.R.

(1)

X X

To Ground Through 1k Ω resistor X N.R.

X

Through 10k Ω resistor

CS_DIS

X

Through 10k Ω resistor

1. Not recommended.

6/32 Doc ID 12581 Rev 11

VND5025AK-E Electrical specification

Figure 3.

Current and voltage conventions

V

CSD

V

IN1

V

IN2

I

CSD

I

IN1

I

IN2

CS_DIS

INPUT1

INPUT2

I

S

GND

V

CC

V

F

I

OUT1

OUTPUT1

I

SENSE1

CURRENT

SENSE1

I

OUT2

V

SENSE1

OUTPUT2

CURRENT

SENSE2

I

SENSE2

V

SENSE2

V

OUT2

V

OUT1

I

GND

V

CC

Note: V

Fn

= V

OUTn

- V

CC

during reverse battery condition.

Stressing the device above the rating listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to the conditions in table below for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality document.

Table 4.

Symbol

Absolute maximum ratings

Parameter

V

CC

-V

CC

-I

GND

I

OUT

- I

OUT

I

IN

I

CSD

-I

CSENSE

V

CSENSE

DC supply voltage

Reverse DC supply voltage

DC reverse ground pin current

DC output current

Reverse DC output current

DC input current

DC current sense disable input current

DC reverse CS pin current

Current sense maximum voltage

Value

41

0.3

200

Internally limited

24

Unit

V mA

A

-1 to 10

200

V

CC

- 41 to +V

CC mA

V

Doc ID 12581 Rev 11 7/32

Electrical specification

Table 4.

Symbol

E

MAX

V

ESD

V

ESD

T j

T stg

Absolute maximum ratings (continued)

Parameter

Maximum switching energy (single pulse)

(L = 0.8mH; R

L

= 0 Ω ; V bat

I

OUT

= I limL

(Typ.))

= 13.5V; T jstart

= 150°C;

Electrostatic discharge

(Human Body Model: R = 1.5k

Ω

; C = 100pF)

- Input

- Current sense

- CS_DIS

- Output

- V

CC

Charge device model (CDM-AEC-Q100-011)

Junction operating temperature

Storage temperature

VND5025AK-E

Value

140

Unit mJ

4000

2000

4000

5000

5000

750

-40 to 150

-55 to 150

V

V

V

V

V

V

°C

Table 5.

Symbol

Thermal data

Parameter

R thj-case

Thermal resistance junction-case (MAX) (with one channel ON)

R thj-amb

Thermal resistance junction-ambient (MAX)

Max Value

1.35

See

Figure 29

Unit

°C/W

8/32 Doc ID 12581 Rev 11

VND5025AK-E Electrical specification

8V<V

CC

<36V; -40°C<T j

<150°C, unless otherwise specified.

Table 6.

Symbol

Power section

Parameter Test conditions

V

CC

V

USD

Operating supply voltage

Undervoltage shutdown

V

USDhyst

Undervoltage shut-down hysteresis

V

I

R clamp

I

L(off)

V

ON

S

F

On-state resistance

Clamp voltage

Supply current

(1)

Off-state output current

(1)

I

OUT

= 3A; T j

= 25°C

I

OUT

= 3A; T j

= 150°C

I

OUT

= 3A; V

CC

= 5V; T j

= 25°C

I

S

= 20 mA

Off-state; V

CC

V

IN

= V

OUT

= 13V; T

= V

SENSE j

= 25°C;

= V

CSD

= 0V

On-state; V

CC

= 13V;

V

IN

= 5V; I

OUT

= 0A

V

IN

= V

OUT

= 0V;

V

CC

= 13V; T j

= 25°C

V

IN

= V

OUT

= 0V;

V

CC

= 13V; T j

= 125°C

Output - V voltage

(1)

CC

diode

-I

OUT

= 4A; T j

= 150°C

1.

For each channel.

2.

PowerMOS leakage included.

Min.

Typ.

Max. Unit

4.5

13 36

3.5

4.5

V

0.5

41

0

0

46

2

(2)

3

0.01

25

50

35

52

5

(2)

6

3

5

0.7

m

V

V

Ω

µA mA

µA

Table 7.

Symbol

Switching (V

CC

= 13V; T j

= 25°C)

Parameter Test conditions Min.

t d(on) t d(off)

Turn-on delay time

Turn-off delay time

(dV

OUT

/dt) on

Turn-on voltage slope

(dV

OUT

/dt) off

Turn-off voltage slope

W

W

ON

OFF

Switching energy losses during t

W ON

Switching energy losses during t

W OFF

R

L

= 4.3

Ω

(see Figure 6 )

R

L

= 4.3

Ω

R

L

= 4.3

Ω

(see Figure 6 )

Typ.

35

50

See Figure 21

See Figure 22

0.45

0.35

Max.

Unit

µs

V/µs mJ

Doc ID 12581 Rev 11 9/32

Electrical specification VND5025AK-E

Table 8.

Symbol

V

IL

I

IL

V

IH

I

IH

V

I(hyst)

Logic input

Parameter

Input low level voltage

Low level input current

Input high level voltage

High level input current

Input hysteresis voltage

V

ICL

Input clamp voltage

V

CSDL

I

CSDL

V

CSDH

I

CSDH

V

CSD(hyst)

CS_DIS low level voltage

Low level CS_DIS current

CS_DIS high level voltage

High level CS_DIS current

CS_DIS hysteresis voltage

V

CSCL

CS_DIS clamp voltage

I

I

I

I

V

V

IN

IN

IN

IN

V

V

Test conditions

= 1mA

= -1mA

CSD

CSD

CSD

CSD

= 0.9V

= 2.1V

= 0.9V

= 2.1V

= 1mA

= -1mA

Min.

Typ.

Max.

Unit

0.9

1

2.1

10

V

µA

V

µA

0.25

5.5

7

V

-0.7

0.9

1

2.1

10

µA

V

µA

0.25

5.5

7 V

-0.7

Table 9.

Symbol

Protection and diagnostics

(1)

Parameter Test conditions Min.

Typ.

Max.

Unit

I

I

LIMH

LIML

DC short circuit current

Short circuit current during thermal cycling

V

CC

= 13V

5V < V

CC

< 36V

V

CC

T

R

= 13V;

< T j

< T

TSD

29 41

16

57

A

T

TSD

T

R

T

RS

Shutdown temperature

Reset temperature

Thermal reset of STATUS

150 175

T

RS

+ 1 T

RS

+ 5

135

200

°C

T

HYST

Thermal hysteresis

(T

TSD

-T

R

)

7

V

DEMAG

V

ON

Turn-off output voltage clamp

Output voltage drop limitation

I

OUT

= 2A;

V

IN

= 0;

L = 6mH

I

OUT

T j

= 0.20.1A;

= -40°C to +150°C

(see Figure 9 )

V

CC

- 41 V

CC

- 46 V

CC

- 52 V

25 mV

1.

To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles.

10/32 Doc ID 12581 Rev 11

VND5025AK-E Electrical specification

Table 10.

Current sense (8V < V

CC

< 16V)

Symbol Parameter Test conditions

K dK

0

LED

K

/K

K

0

1

0

(1) dK

1

/K

1

(1) dK dK

I

V

V

2

3

I

K

/K

K

2

3

/K

2

(1)

3

(1)

SENSE0

OL

SENSE

SENSEH

Min. Typ. Max. Unit

I

I

I

I

I

OUT

OUT

OUT

OUT

/I

/I

/I

SENSE

SENSE

Current Sense ratio drift

SENSE

Current Sense ratio drift

Current Sense ratio drift

OUT

/I

/I

SENSE

SENSE

Current Sense ratio drift

I

OUT

T j

= 0.05A; V

SENSE

= -40°C to 150°C

= 0.5V; V

CSD

= 0V;

1450 3300 5180

I

OUT

T j

= 0.5 A; V

SENSE

= -40°C to 150°C

= 0.5V; V

CSD

= 0V;

1720 3020 4360

I

OUT

T j

= 0.5A; V

SENSE

= -40°C to 150°C

= 0.5V; V

CSD

= 0V;

I

OUT

= 2A; V

SENSE

= 4V;

V

CSD

= 0V;

T j

= -40°C to 150°C

T j

= 25°C to 150°C

-12

1940

2230

2810

2810

+12

3740

3390

%

I

OUT

= 2A; V

SENSE

= 4V;

V

CSD

= 0V;

T j

= -40°C to 150°C

I

OUT

= 3A; V

SENSE

= 4V;

V

CSD

= 0V;

T j

= -40°C to 150°C

T j

= 25°C to150°C

I

OUT

T j

= 3A; V

SENSE

= -40°C to 150°C

= 4V; V

CSD

= 0V;

I

OUT

= 10A; V

SENSE

= 4V;

V

CSD

= 0V;

T j

= -40°C to 150°C

T j

= 25°C to 150°C

I

OUT

= 10A; V

SENSE

= 4V; V

CSD

= 0V;

T j

= -40°C to 150°C

I

OUT

= 0A; V

SENSE

= 0V;

V

CSD

= 5V; V

IN

V

CSD

= 0V; V

IN

= 0V; T j

= -40°C to 150°C

= 5V; T j

= -40°C to 150°C

-10 +10

2250

2400

2790

2790

3450

3180

-7 +7

2610

2650

2760

2760

2970

2870

-4

0

0

+4

1

2

%

%

%

µA

µA Analog Sense leakage current

I

OUT

= 2A; V

SENSE

= 0V;

V

CSD

= 5V; V

IN

= 5V; T j

= -40°C to 150°C 0

Openload onstate current detection threshold

Max analog

Sense output voltage

I

V

IN

OUT

= 5V, I

SENSE

= 3 A; V

CSD

= 5 µA 5

= 0V 5

Analog Sense output voltage in over temperature condition

V

CC

= 13V; R

SENSE

= 3.9k

Ω 9

1

30

µA mA

V

Doc ID 12581 Rev 11 11/32

Electrical specification VND5025AK-E

Table 10.

Current sense (8V < V

CC

< 16V) (continued)

Symbol Parameter Test conditions t t

I

SENSEH

DSENSE1H

DSENSE1L

Analog Sense output current in over temperature condition

V

CC

= 13V; V

SENSE

= 5V

Delay response time from falling edge of CS_DIS pin

V

SENSE

I

SENSE

< 4V, 0.5 < I

OUT

< 10A

= 90% of I

SENSEMAX

(see

Figure 4

)

Delay response time from rising edge of CS_DIS pin

V

SENSE

I

SENSE

< 4V, 0.5 < I

OUT

< 10A

= 10% of I

SENSEMAX

(see

Figure 4

) t

DSENSE2H

Delay response time from rising edge of INPUT pin

V

SENSE

I

SENSE

< 4V, 0.5 < I

OUT

< 10A

= 90% of I

SENSEMAX

(see

Figure 4

)

Δ t

DSENSE2H

Delay response time between rising edge of output current and rising edge of current sense t

DSENSE2L

V

SENSE

< 4V,

I

SENSE

= 90% of I

SENSEMAX,

I

OUT

= 90% of I

(see

Figure 5

)

OUTMAX

, I

OUTMAX

= 3A

Delay response time from falling edge of INPUT pin

V

SENSE

I

SENSE

< 4V, 0.5 < I

OUT

< 10A

= 10% of I

SENSEMAX

(see

Figure 4

)

1.

Parameter guaranteed by design; it is not tested.

Min. Typ. Max. Unit

8

50 100

70 300

µs

200

100 250 mA

5 20

Figure 4.

Current sense delay characteristics

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT t

DSENSE2H t

DSENSE1L t

DSENSE1H t

DSENSE2L

12/32 Doc ID 12581 Rev 11

VND5025AK-E Electrical specification

Figure 5.

Delay response time between rising edge of output current and rising edge of Current Sense (CS enabled)

V

IN

Δ t

DSENSE2H t

I

OUT

90% I

OUTMAX

I

OUTMAX t

I

SENSE I

SENSEMAX

90% I

SENSEMAX t

Figure 6.

Switching characteristics

V

OUT t

Won

80% dV

OUT

/dt

(on) t r

10%

INPUT t d(on) t d(off) t

Woff

90% t f dV

OUT

/dt

(off) t t

Doc ID 12581 Rev 11 13/32

Electrical specification

Figure 7.

I

OUT

/I

SENSE

vs I

OUT

(1)

I out

/ I sense

4500

4000

3500 max Tj = -40 °C to 150 °C

3000 max Tj = 25 °C to 150 °C

2500 min Tj = 25 °C to 150 °C

2000 min Tj = -40 °C to 150 °C

1500 typical value

1000

2 4 6

I

OUT

(A)

8

1.

See

Table 10

for details.

Figure 8.

Maximum current sense ratio drift vs load current

(1)

dk/k(%)

15

10

VND5025AK-E

10

5

0

-5

-10

-15

2 3 4

1.

Parameter guaranteed by design; it is not tested.

5 6

I

OUT

(A)

7 8 9 10

14/32 Doc ID 12581 Rev 11

VND5025AK-E Electrical specification

Table 11.

Truth table

Conditions

Normal operation

Input

L

H

Output

L

H

Sense (V

CSD

= 0V)

(1)

0

Nominal

Over temperature

L

H

L

0

V

SENSEH

Undervoltage

L

H

L

L 0

0

Short circuit to GND (R

SC

Short circuit to V

CC

≤

10m Ω )

H

L

H

L

H

0 if T j

< T

TSD

V

SENSEH

if T j

> T

TSD

0

< Nominal

Negative output voltage clamp L L 0

1.

If the V

CSD

is high, the SENSE output is at a high impedance; its potential depends on leakage currents and external circuit.

Figure 9.

Output voltage drop limitation

V

CC

- V

OUT

T j

= 150 o

C

T j

= 25 o

C

T j

= -40 o

C

V on

V on

/R on(T)

I

OUT

Doc ID 12581 Rev 11 15/32

Electrical specification VND5025AK-E

Table 12.

Electrical transient requirements (part 1/3)

ISO 7637-2:

2004(E)

Test pulse

III

Test levels

(1)

IV

Number of pulses or test times

Burst cycle/pulse repetition time

Min.

Max.

1

2a

-75V

+37V

-100V

+50V

5000 pulses

5000 pulses

0.5s

0.2s

5s

5s

3a -100V -150V 1h 90ms 100ms

3b +75V

-6V

+100V

-7V

1h

1 pulse

90ms 100ms

4

5b

(2)

+65V +87V 1 pulse

1.

The above test levels must be considered referred to V

CC

= 13.5V except for pulse 5b.

2.

Valid in case of external load dump clamp: 40V maximum referred to ground.

Delays and

Impedance

2 ms, 10 Ω

50µs, 2 Ω

0.1µs, 50

Ω

0.1µs, 50

Ω

100ms, 0.01

Ω

400ms, 2 Ω

Table 13.

Electrical transient requirements (part 2/3)

Test level results ISO 7637-2:

2004E

Test pulse III

1

2a

3a

C

C

C

3b C

5b

4

(1)

C

C

1.

Valid in case of external load dump clamp: 40V maximum referred to ground.

VI

C

C

C

C

C

C

Table 14.

Electrical transient requirements (part 3/3)

Class Contents

C

E

All functions of the device performed as designed after exposure to disturbance.

One or more functions of the device did not perform as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.

16/32 Doc ID 12581 Rev 11

VND5025AK-E

Figure 10.

Waveforms

NORMAL OPERATION

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT

UNDERVOLTAGE

V

USDhyst

V

CC

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT

V

USD

INPUT

CS_DIS

LOAD VOLTAGE

LOAD CURRENT

SENSE CURRENT

< Nominal

SHORT TO V

CC

< Nominal

Electrical specification

OVERLOAD OPERATION

T

R

T

TSD

T

RS

T j

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT

Current limitation

Power limitation

SHORTED LOAD

Thermal cycling

I

LIMH

I

LIML

V

SENSEH

NORMAL LOAD

Doc ID 12581 Rev 11 17/32

Electrical specification VND5025AK-E

Figure 11.

Off-state output current

Iloff (uA)

0.5

0.45

0.4

0.35

0.3

0.25

0.2

0.15

0.1

0.05

0

-50 -25

Off State

Vcc=13V

Vin=Vout=0V

0 25 50 75

Tc (°C)

100 125 150 175

Figure 13.

Input clamp voltage

Vicl (V)

7

6.75

6.5

6.25

6

5.75

5.5

Iin=1mA

5.25

5

-50 -25 0 25 50 75

Tc (°C)

100 125 150 175

Figure 15.

Input low level

Vil (V)

2

1.8

1.6

1.4

1.2

1

0.8

0.6

0.4

0.2

0

-50 -25 0 25 50 75

Tc (°C)

100 125 150 175

Figure 12.

High level input current

4

3.5

3

2.5

Iih(uA)

5

4.5

2

1.5

1

0.5

0

-50 -25

Vin=2.1V

0 25 50 75

Tc (°C)

100 125 150 175

Figure 14.

Input high level

Vih (V)

4

3.5

3

2.5

2

1.5

1

0.5

0

-50 -25 0 25 50 75

Tc (°C)

100 125 150 175

Figure 16.

Input hysteresis voltage

Vhyst (V)

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

-50 -25 0 25 50 75

Tc (°C)

100 125 150 175

18/32 Doc ID 12581 Rev 11

VND5025AK-E

Figure 17.

On-state resistance vs T case

Ron (mOhm)

100

90

80

70

Iout=3A

Vcc=13V

60

50

40

30

20

10

0

-50 -25 0 25 50 75

Tc (°C)

100 125 150 175

Figure 19.

Undervoltage shutdown

Vusd (V)

16

10

8

14

12

6

4

2

0

-50 -25 0 25 50 75

Tc (°C)

100 125 150 175

Figure 21.

Turn-on voltage slope

(dVout/dt)on (V/ms)

1000

900

800

700

Vcc=13V

Rl=4.3Ohm

600

500

400

300

200

100

0

-50 -25 0 25 50 75

Tc (°C)

100 125 150 175

Electrical specification

Figure 18.

On-state resistance vs V

CC

Ron (mOhm)

80

70

60

50

40

30

20

10

0

0 5 10

Tc=150°C

Tc= 125°C

Tc= 25°C

Tc= -40°C

15 20

Vcc (V)

25 30 35 40

Figure 20.

I

LIMH

vs T case

Ilimh (A)

100

90

80

70

60

50

40

30

20

10

0

-50 -25

Vcc=13V

0 25 50 75

Tc (°C)

100 125 150 175

Figure 22.

Turn-off voltage slope

(dVout/dt)off (V/ms)

1000

900

800

Vcc=13V

Rl=4.3Ohm

700

600

500

400

300

200

100

0

-50 -25 0 25 50 75

Tc (°C)

100 125 150 175

Doc ID 12581 Rev 11 19/32

20/32

Electrical specification

Figure 23.

CS_DIS high level voltage

Vcsdh (V)

4

3.5

3

2.5

2

1.5

1

0.5

0

-50 -25 0 25 50 75

Tc (°C)

100 125 150 175

Figure 25.

CS_DIS clamp voltage

Vcsdcl (V)

8

7.5

7

Icsd=1mA

6.5

6

5.5

5

4.5

4

-50 -25 0 25 50 75

Tc (°C)

100 125 150 175

VND5025AK-E

Figure 24.

CS_DIS low level voltage

Vcsdl (V)

4

3.5

3

2.5

2

1.5

1

0.5

0

-50 -25 0 25 50 75

Tc (°C)

100 125 150 175

Doc ID 12581 Rev 11

VND5025AK-E Application information

Figure 26.

Application schematic

+5V

R prot CS_DIS

µC

V

CC

C

R prot

R prot

EXT

INPUT

R

CURRENT SENSE

SENSE

GND

V

GND

R

GND

D

GND

OUTPUT

D ld

Note:

3.1

3.1.1

Channel 2 has the same internal circuit as channel 1.

GND protection network against reverse battery

This section provides two solutions for implementing a ground protection network against reverse battery.

Solution 1: resistor in the ground line (R

GND

only)

This first solution can be used with any type of load.

The following formulas indicate how to dimension the R

GND resistor:

1.

R

GND

≤

600mV / (I

S(on)max

)

2. R

GND

≥ (-V

CC

) / (-I

GND

) where -I

GND

is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet.

Power Dissipation in R

GND

(when V

CC

P

D

= (-V

CC

)

2

/ R

GND

< 0 during reverse battery situations) is:

This resistor can be shared among several different HSDs. Please note that the value of this resistor is calculated with formula (1), where I

S(on)max state currents of the different devices.

becomes the sum of the maximum on-

Please note that if the microprocessor ground is not shared by the device ground, the R

GND produces a shift (I

S(on)max

* R

GND

) in the input thresholds and the status output values. This shift varies depending on how many devices are ON in the case of several high-side drivers sharing the same R

GND

.

Doc ID 12581 Rev 11 21/32

22/32

Application information

3.1.2

VND5025AK-E

If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor, then ST suggests to utilize the following Solution 2.

Solution 2: diode (D

GND

) in the ground line

If the device drives an inductive load, insert a resistor (R

GND

= 1k

Ω

) in parallel to D

GND

.

This small signal diode can be safely shared among several different HSDs. Also in this case, the presence of the ground network produces a shift (

≈

600mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift does not vary if more than one HSD shares the same diode/resistor network.

3.2 Load dump protection

D ld

is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the

V

CC

maximum DC rating. The same applies if the device is subject to transients on the V

CC line that are greater than the ones shown in the ISO 7637-2:2004E table.

3.3 MCU I/Os protection

If a ground protection network is used and negative transients are present on the V

CC

line, the control pins are pulled negative. ST suggests to insert an in-line resistor (R prot

) to prevent the µC I/Os pins from latch-up.

The value of these resistors is a compromise between the leakage current of µC and the current required by the HSD I/Os (input levels compatibility) with the latch-up limit of µC

I/Os.

-V

CCpeak

/I latchup

≤

R prot

≤

(V

OHµC

-V

IH

-V

GND

) / I

IHmax

Calculation example:

For V

CCpeak

= -100V and I latchup

≥

20mA; V

OHµC

≥

4.5V

5k Ω ≤

R prot

≤

180k Ω

Recommended values: R prot

= 10k Ω , C

EXT

= 10nF.

Doc ID 12581 Rev 11

VND5025AK-E

3.4

Application information

Maximum demagnetization energy (V

CC

= 13.5V)

Figure 27.

Maximum turn-off current versus inductance (for each channel)

100

C

A

B

10

1

0,1 1 L (mH) 10 100

A: T jstart

= 150°C single pulse

B: T jstart

= 100°C repetitive pulse

C: T jstart

= 125°C repetitive pulse

V

IN

, I

L

Demagnetization Demagnetization Demagnetization

Note: t

Values are generated with R

L

= 0

Ω.

In case of repetitive pulses, T jstart

(at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B.

Doc ID 12581 Rev 11 23/32

Package and thermal data

4 Package and thermal data

4.1 PowerSSO-24™ thermal data

Figure 28.

PowerSSO-24™ PC board

VND5025AK-E

Note: Layout condition of R th

and Z th

measurements (PCB: Double layer, Thermal Vias, FR4 area = 77mm x 86mm, PCB thickness = 1.6mm, Cu thickness = 70µm (front and back side),

Copper areas: from minimum pad layout to 8cm

2

).

Figure 29.

R thj-amb

vs PCB copper area in open box free air condition (one channel

ON)

RTHj_amb(°C/W)

55

50

45

40

35

30

0 2 4 6

PCB Cu heatsink area (cm^2)

8 10

24/32 Doc ID 12581 Rev 11

VND5025AK-E Package and thermal data

Figure 30.

PowerSSO-24™ thermal impedance junction to ambient single pulse (one channel ON)

ZTH (°C/W)

1000

100

10

1

Footprint

2 cm

2

8 cm

2

0.1

0.0001

0.001

0.01

0.1

Time (s)

1 10 100 1000

Equation 1: pulse calculation formula

Z

TH δ = R

TH where

δ

= t

P

/T

⋅ δ

+ Z

THtp

(

1 –

δ )

Figure 31.

Thermal fitting model of a double channel HSD in PowerSSO-24™

(1)

1.

The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered.

Doc ID 12581 Rev 11 25/32

Package and thermal data

Table 15.

Thermal parameters

Area/Island (cm

2

) Footprint

R1 (°C/W)

R2 (°C/W)

R3 (°C/W)

R4 (°C/W)

R5 (°C/W)

R6 (°C/W)

R7 (°C/W)

R8 (°C/W)

C1 (W.s/°C)

C2 (W.s/°C)

C3 (W.s/°C)

C4 (W.s/°C)

C5 (W.s/°C)

C6 (W.s/°C)

C7 (W.s/°C)

C8 (W.s/°C)

0.28

0.9

0.001

0.003

0.025

0.75

1

0.28

0.9

6

7.7

9

28

2.2

0.001

0.003

2

9

17

4

5

VND5025AK-E

8

8

10

9

17

26/32 Doc ID 12581 Rev 11

VND5025AK-E

5

Package and packing information

Package and packing information

5.1 ECOPACK

®

packages

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK

® specifications, grade definitions and product status are available at: www.st.com

.

ECOPACK

®

is an ST trademark.

Figure 32.

PowerSSO-24™ package dimensions

Doc ID 12581 Rev 11 27/32

Package and packing information

Table 16.

PowerSSO-24™ mechanical data

Symbol

Min h k

G

H e e3

F

A

A2

D

E a1 b c

L

O

Q

S

T

U

N

X

Y

2.15

0

0.33

0.23

10.10

7.4

10.1

0°

0.55

4.1

6.5

Millimeters

Typ

0.8

8.8

2.3

1.2

0.8

2.9

3.65

1.0

VND5025AK-E

Max

2.45

2.35

0.1

0.51

0.32

10.50

7.6

0.1

10.5

0.4

8°

0.85

10°

4.7

7.1

28/32 Doc ID 12581 Rev 11

VND5025AK-E Package and packing information

Figure 33.

PowerSSO-24™ tube shipment (no suffix)

C

B

Base Qty

Bulk Qty

Tube length (±0.5)

A

B

C (±0.1)

All dimensions are in mm.

49

1225

532

3.5

13.8

0.6

A

Figure 34.

PowerSSO-24™ tape and reel shipment (suffix “TR”)

REEL DIMENSIONS

Base Qty

Bulk Qty

A (max)

B (min)

C (±0.2)

F

G (+2 / -0)

N (min)

T (max)

1000

1000

330

1.5

13

20.2

24.4

100

30.4

TAPE DIMENSIONS

According to Electronic Industries Association

(EIA) Standard 481 rev. A, Feb. 1986

Tape width

Tape Hole Spacing

Component Spacing

Hole Diameter

Hole Diameter

Hole Position

Compartment Depth

Hole Spacing

W

P0 (±0.1)

D1 (min)

F (±0.1)

K (max)

P1 (±0.1)

24

4

P 12

D (±0.05) 1.55

1.5

11.5

2.85

2

All dimensions are in mm.

End

Top cover tape

No components Components No components

500mm min 500mm min

Empty components pockets sealed with cover tape.

Start

User direction of feed

Doc ID 12581 Rev 11 29/32

Revision history VND5025AK-E

30/32

Table 17.

Document revision history

Date Revision

11-Apr-2006

30-Mar-2007

01-Jun-2007

03-Jul-2007

24-Jul-2007

12-Dec-2007

12-Feb-2008

10-Apr-2008

02-Jul-2009

1

2

3

4

5

6

7

8

9

Changes

Initial release

Reformatted.

Table 4 on page 7 : updated E

MAX

entries.

Table 6 on page 9 : updated V

F

test conditions.

Table 7 on page 9 : set T

j

condition to 25°C”

Table 10 on page 11

: added dK

1

/K

1

, dK

2

/K

2

, dK

3

/K

3

, Δ t

DSENSE2H

, t

DSENSE2H

values and note.

Added

Figure 5: Delay response time between rising edge of output current and rising edge of Current Sense (CS enabled) on page 13 .

Updated

Figure 7: IOUT/ISENSE vs IOUT

(1)

on page 14

.

Added

Figure 8: Maximum current sense ratio drift vs load current

(1) on page 14 .

Table 12 on page 16

: Updated Test Level values III and IV for test pulse 5b and notes.

Added

Section 3.4: Maximum demagnetization energy

(VCC = 13.5V) on page 23

.

Added

ECOPACK® packages information.

Figure 31: Thermal fitting model of a double channel HSD in

PowerSSO-24™

(1)

: added note.

Updated

Figure 1: Block diagram

and Figure 2: Configuration diagram (top view)

.

Updated

Table 16: PowerSSO-24™ mechanical data

.

Updated

Table 10: Current sense (8V < VCC < 16V) :

– added dK

0

/K

0 values

– changed dK

3

/K

3 values from ± 3 to ± 4%

– changed Δ t

DSENSE2H

value from 110 to 200 µs

– added I

OL parameter

Updated

Figure 8: Maximum current sense ratio drift vs load current

(1)

with new dK/K values.

Corrected typing error in Table 10: Current sense (8V < VCC < 16V)

: changed I

OL test condition from V

IN

= 0V to V

IN

= 5V.

Corrected Figure 27: Maximum turn-off current versus inductance (for each channel)

Table 16: PowerSSO-24™ mechanical data

:

– Deleted A (min) value

– Changed A (max) value from 2.47 to 2.45

– Changed A2 (max) value from 2.40 to 2.35

– Changed a1 (max) value from 0.075 to 0.1

– Added F row

– Updated k values

Doc ID 12581 Rev 11

VND5025AK-E Revision history

Table 17.

Document revision history (continued)

Date Revision Changes

23-Jul-2009

23-Sep-2013

10

11

Updated

Figure 32: PowerSSO-24™ package dimensions

.

Updated

Table 16: PowerSSO-24™ mechanical data

:

– Deleted G1 row

– Added O, Q, S, T and U rows

Updated Disclaimer.

Doc ID 12581 Rev 11 31/32

VND5025AK-E

Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice.

All ST products are sold pursuant to ST’s terms and conditions of sale.

Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.

UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED

WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED

WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS

OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

ST PRODUCTS ARE NOT DESIGNED OR AUTHORIZED FOR USE IN: (A) SAFETY CRITICAL APPLICATIONS SUCH AS LIFE

SUPPORTING, ACTIVE IMPLANTED DEVICES OR SYSTEMS WITH PRODUCT FUNCTIONAL SAFETY REQUIREMENTS; (B)

AERONAUTIC APPLICATIONS; (C) AUTOMOTIVE APPLICATIONS OR ENVIRONMENTS, AND/OR (D) AEROSPACE APPLICATIONS

OR ENVIRONMENTS. WHERE ST PRODUCTS ARE NOT DESIGNED FOR SUCH USE, THE PURCHASER SHALL USE PRODUCTS AT

PURCHASER’S SOLE RISK, EVEN IF ST HAS BEEN INFORMED IN WRITING OF SUCH USAGE, UNLESS A PRODUCT IS

EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR “AUTOMOTIVE, AUTOMOTIVE SAFETY OR MEDICAL” INDUSTRY

DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS. PRODUCTS FORMALLY ESCC, QML OR JAN QUALIFIED ARE

DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY.

Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST.

ST and the ST logo are trademarks or registered trademarks of ST in various countries.

Information in this document supersedes and replaces all information previously supplied.

The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.

© 2013 STMicroelectronics - All rights reserved

STMicroelectronics group of companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -

Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com

32/32 Doc ID 12581 Rev 11