STL80N10WF7
Nchannel 100 V, 9.4 mΩ typ., 80 A, STripFET™ F7
Power MOSFET in a PowerFLAT™ 5x6 package
Datasheet - production data
Figure 1: Internal schematic diagram
Features
Order code V
DS
R
DS(on)max
I
D
P
TOT
STL80N10WF7 100 V 11.0 mΩ 80 A 150 W
Best-in-class SOA capability
High current surge capability
Extremely low on-resistance
Applications
Hot-swap
Electronic fuse
Load switch
Description
This N-channel Power MOSFET utilizes the
STripFET™ F7 technology with an enhanced trench gate structure providing a wider SOA capability combined with a very low on-state resistance. The resulting MOSFET ensures the best trade-off between linear mode and switching operations.
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Order code Marking Package Packing
PowerFLAT™ 5x6 STL80N10WF7 80N10WF7 Tape and reel
April 2017 DocID029558 Rev 2
This is information on a product in full production.
1/14 www.st.com
Contents
Contents
STL80N10WF7
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
3 Test circuits ..................................................................................... 8
4 Package information ....................................................................... 9
4.1
4.2
PowerFLAT™ 5x6 type C package information ................................ 9
Pow erFLAT™ 5x6 type C packing information................................ 11
5 Revision history ............................................................................ 13
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STL80N10WF7
1 Electrical ratings
Symbol
V
DS
V
GS
I
D
(1)
I
D
(1)
I
DM
(1)(2)
I
D
(3)
I
D
(3)
I
DM
(3)(2)
P
TOT
(1)
P
TOT
(3)
T
J
T stg
Table 2: Absolute maximum ratings
Parameter
Drain-source voltage
Gate-source voltage
Drain current (continuous) at T c
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
Drain current (continuous) at T pcb
= 25 °C
Drain current (continuous) at T pcb
= 100 °C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
Total dissipation at T pcb
= 25 °C
Operating junction temperature range
Storage temperature range
Notes:
(1)
This value is rated according to R thj-c
.
(2)
Pulse width limited by safe operating area.
(3)
This value is rated according to R thj-pcb
.
Symbol
Table 3: Thermal data
Parameter
R thj-case
R
thj-pcb
(1)
Thermal resistance junction-case
Thermal resistance junction-pcb
Notes:
(1)
When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 s.
Electrical ratings
Value
15
11
60
150
4.8
100
±20
80
59
320
-55 to 175
Unit
A
A
A
W
W
°C
°C
V
V
A
A
A
Value
1.0
31.3
Unit
°C/W
°C/W
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Electrical characteristics
2 Electrical characteristics
(T
C
= 25 °C unless otherwise specified)
Symbol Parameter
Table 4: On /off states
Test conditions
V
(BR)DSS
Drain-source breakdown voltage
V
GS
= 0 V, I
D
= 1 mA
I
DSS
Zero gate voltage drain current
V
GS
= 0 V, V
DS
= 100 V
V
GS
= 0 V, V
DS
= 100 V,
T
C
= 125 °C (1)
I
GSS
Gate-body leakage current
V
GS(th)
Gate threshold voltage
R
DS(on)
Static drain-source on- resistance
V
DS
= 0 V, V
GS
= 20 V
V
DS
= V
GS
, I
D
= 250 µA
V
GS
= 10 V, I
D
= 7.5 A
STL80N10WF7
Min. Typ. Max. Unit
100 V
1 µA
100 µA
100 nA
4.5 V
9.4 11.0 mΩ
2.5
Notes:
(1)
Defined by design, not subject to production test.
Symbol Parameter
Table 5: Dynamic
Test conditions
C iss
C oss
C rss
Q g
Q gs
Q gd
Input capacitance
Output capacitance
Reverse transfer capacitance
Total gate charge
Gate-source charge
Gate-drain charge
V
GS
= 0 V, V
DS
= 50 V, f = 1 MHz
V
DD
= 50 V, I
D
= 15 A,
V
GS
= 0 to 10 V
(see Figure 14: "Test circuit for gate charge behavior" )
Symbol Parameter t d(on)
Turn-on delay time t r
Rise time t d(off)
Turn-off delay time
Table 6: Switching times
Test conditions
V
DD
= 50 V, I
D
= 7.5 A,
R
G
= 4.7
Ω, V
GS
= 10 V t f
Fall time
and Figure 17: "Unclamped inductive waveform" )
Min. Typ. Max. Unit
- 2200 - pF
- 1100 - pF
-
-
-
-
Min. Typ. Max. Unit
-
-
-
21.4
13
35.2
-
-
- ns ns ns
-
38
36
13
9.4
16.2
-
-
-
-
- pF nC nC nC ns
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STL80N10WF7
Symbol Parameter
V
SD
(1)
Forward on voltage t rr
Q rr
Reverse recovery time
Reverse recovery charge
I
RRM
Table 7: Source drain diode
Test conditions
Reverse recovery current
V
GS
= 0 V, I
SD
= 15 A
I
SD
= 15 A, di/dt = 100 A/µs
V
DD
= 80 V (see Figure 15:
"Test circuit for inductive load switching and diode recovery times" )
Electrical characteristics
Min. Typ. Max. Unit
-
-
-
-
-
37
125
1.9
1.2 V ns nC
A
Notes:
(1)
Pulsed: pulse duration = 300 µs, duty cycle 1.5%
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Electrical characteristics
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area
STL80N10WF7
Figure 3: Thermal impedance
Figure 4: Output characteristics Figure 5: Transfer characteristics
Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance
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Figure 8: Capacitance variations
Electrical characteristics
Figure 9: Normalized gate threshold voltage vs temperature
Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature
Figure 12: Source-drain diode forward characteristics
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Test circuits
3 Test circuits
Figure 13: Test circuit for resistive load switching times
STL80N10WF7
Figure 14: Test circuit for gate charge behavior
Figure 15: Test circuit for inductive load switching and diode recovery times
Figure 16: Unclamped inductive load test circuit
Figure 17: Unclamped inductive waveform
Figure 18: Switching time waveform
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4
4.1
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
PowerFLAT™ 5x6 type C package information
Figure 19
: PowerFLAT™ 5x6 type C package outline
Bottom view
Side view
Top view
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Package information
D4
D5
D6 e
E
E2
E3
C
D
D2
D3
A
A1
A2 b
E4
E5
E6
E7
K
L
L1
θ
Dim.
Table 8: PowerFLAT™ 5x6 type C package mechanical data
STL80N10WF7 mm
Min. Typ. Max.
0.80
0.02
0.25
1.00
0.05
0.30
5.80
5.00
4.15
4.05
4.80
0.25
0.15
6.00
5.20
4.20
5.00
0.40
0.30
1.27
6.15
0.50
6.20
5.40
4.45
4.35
5.20
0.55
0.45
5.95
3.50
2.35
0.40
0.08
0.20
0.75
1.05
0.725
0.05
0°
0.325
0.90
0.15
6.35
3.70
2.55
0.60
0.28
0.45
1.05
1.35
1.025
0.25
12°
Figure 20 : PowerFLAT™ 5x6 recommended footprint (dimensions are in mm)
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STL80N10WF7
4.2 PowerFLAT™ 5x6 type C packing information
Package information
Figure 21
: PowerFLAT™ 5x6 tape (dimensions are in mm)
(I) Measured from centreline of sprocket hole
to centreline of pocket.
(II) Cumulative tolerance of 10 sprocket
holes is ±0.20.
(III) Measured from centreline of sprocket
hole to centreline of pocket
Base and bulk quantity 3000 pcs
All dimensions are in millimeters
Figure 22
: PowerFLAT™ 5x6 package orientation in carrier tape
8234350_ Tape_rev_C
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Package information
Figure 23
: PowerFLAT™ 5x6 reel
STL80N10WF7
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STL80N10WF7
5 Revision history
Date
Table 9: Document revision history
Revision Changes
12-Jul-2016
28-Apr-2017
1
2
Initial release.
Updated Table 5: "Dynamic" .
Minor text changes.
Revision history
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STL80N10WF7
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