BALF-NRF01J5
Datasheet
50 Ω ultra thin balun with integrated harmonic filter / conjugate match balun to nRF51822-CTAA/CTAC in WLCSP
Product status
BALF-NRF01J5
Features
• 50 Ω nominal input / conjugate match to Nordic Semiconductor chips nRF51822
WLCSP
• Low insertion loss
• Low amplitude imbalance
• Low phase imbalance
• Small footprint: < 1.2 mm 2
• Extra low profile < 350 μm after reflow
• High RF performance
• RF BOM and area reduction
Applications
• 2.45 GHz impedance matched balun filter
• Optimized for Nordic's chip set nRF51822-CTAA, CTAC
• Wearable applications
Description
This device is an ultraminiature extra thin balun that integrates matching network and harmonics filter.
Matching impedance has been customized for the nRF51822-CTAA and CTAC
WLCSP Nordic Semiconductor circuits.
Based on IPD technology on high resistivity silicium it optimizes the RF performance.
The BALF-NRF01J5 has been tested and approved by Nordic Semiconductor.
STMicroelectronics qualified this product intended to be used in System in Package module based on standard reliability procedure. For more details, please contact ST representatives.
It is the responsibility of the customer to perform qualification reliability verifications as it is related to customer specific application / mission profile and module design / process.
DS12205 - Rev 3 - April 2018
For further information contact your local STMicroelectronics sales office.
www.st.com
1
BALF-NRF01J5
Characteristics
Characteristics
Table 1. Absolute ratings (limiting values)
Symbol Parameter
P
V
ESD
T
IN
OP
Input power RF
IN
ESD ratings human body model (JESD22-A114-C), all I/O one at a time while others connected to GND
ESD ratings charge device model (JESD22-C101-C)
ESD ratings machine model, all I/O
Operating temperature
Value
Min. Typ. Max.
Unit
20 dBm
2000 -
-
V
500 -
200 -
-40 +85 °C
Table 2. Impedances (T amb
= 25 °C)
Symbol
Z
OUT
Z
IN
Parameter
Nominal differential output impedance
Nominal input impedance
Min.
-
-
Value
Typ.
matched
50
Max.
-
-
Unit
Ω
Ω
Symbol f
I
L
R
L
φimb
Aimb
2f0
3f0
Parameter
Frequency range (bandwidth)
Insertion loss in bandwidth
Return loss in bandwidth
Phase imbalance
Amplitude imbalance
2nd harmonic S21 attenuation
3rd harmonic S21 attenuation
Table 3. RF performances (T amb
= 25 °C)
4880 MHz
7320 MHz
9
-7.2
-0.5
12
24
Min.
2400
Value
Typ.
2.2
12
7
0.3
13.5
25
Max.
2540
2.4
7.2
0.5
Unit
MHz dB dB
° dB dB dB
DS12205 - Rev 3 page 2/9
1.1
On-board measurements
Figure 1. Transmission (T amb
= 25 °C)
BALF-NRF01J5
On-board measurements
Figure 2. Insertion loss (T amb
= 25 °C)
Figure 3. Return loss on SE port (T amb
= 25 °C) Figure 4. Return loss on DIFF port (T amb
= 25 °C)
Figure 5. Amplitude imbalance (T amb
= 25 °C) Figure 6. Phase imbalance (T amb
= 25 °C)
DS12205 - Rev 3 page 3/9
2
2.1
BALF-NRF01J5
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
. ECOPACK ® is an ST trademark.
•
•
Ultra thin Flip-Chip 5 bumps package information
Epoxy meets UL94, V0
Lead-free package
Figure 7. Ultra thin Flip-Chip 5 bumps package outline
DS12205 - Rev 3
Parameter
X
A1
B1
Y
A
B
B2
D
T
H
Table 4. Ultra thin Flip-Chip 5 bumps package mechanical data
Description
X dimension of the die
Y dimension of the die
X pitch
Y pitch
Distance from bump to edge of die on X axis
Distance from bump to edge of die on Y axis
Distance from bump to center of die on Y axis
Bump diameter
Substrate thickness
Bump height
Min.
1315
785
202
190
117
Typ.
1345
815
500
400
172.5
207.5
200
227
200
142
Max.
1375
845
Unit
252
210
167
µm page 4/9
BALF-NRF01J5
Ultra thin Flip-Chip 5 bumps package information
Figure 8. Recommended land pattern
Note:
Note:
Screenprinting, stencil windows 290 x 290 x 100 µm3 (coeff 0.725) to achieve minimum component height after PCB reflow, the below recommendations must be followed : in assembly process, a flux must be used, not a solder paste
DS12205 - Rev 3 page 5/9
BALF-NRF01J5
Flip-chip 5 bumps packing information
Figure 9. PCB stack-up recommendation
2.2
Flip-chip 5 bumps packing information
Figure 10. Marking
Note: More packing information is available in the application note:
• AN2348 Flip-Chip: “Package description and recommendations for use”
Figure 11. Footprint - non solder mask defined Figure 12. Footprint - solder mask defined
DS12205 - Rev 3 page 6/9
3
BALF-NRF01J5
Ordering information
Ordering information
Order code
BALF-NRF01J5
Marking
TL
Table 5. Ordering information
Package
Flip-Chip 5 bumps
Weight
0.631 mg
Base qty.
5000
Delivery mode
Tape and reel
DS12205 - Rev 3 page 7/9
BALF-NRF01J5
Revision history
Date
20-Jun-2017
22-Feb-2018
04-Apr-018
Table 6. Document revision history
Revision
1
2
3
Changes
Initial release.
Updated Description and Table 4. Ultra thin Flip-Chip 5 bumps package mechanical data.
U
pdated Table 4. Ultra thin Flip-Chip 5 bumps package mechanical data
.
DS12205 - Rev 3 page 8/9
BALF-NRF01J5
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2018 STMicroelectronics – All rights reserved
DS12205 - Rev 3 page 9/9
